FEATURES Four 8-Bit DACs with Output Amplifiers Skinny 20-Lead DIP, SO
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LC2MOS Quad 8-Bit Converter AD7226
FEATURES Four 8-Bit DACs with Output Amplifiers Skinny 20-Lead DIP, SOIC, SSOP, PLCC Packages Microprocessor-Compatible TTL/CMOS-Compatible User Trims Extended Temperature Range Operation Single Supply Operation Possible APPLICATIONS Process Control Automatic Test Equipment Automatic Calibration Large System Parameters, e.g., Gain/Offset
DATA (8-BIT)
VREF
LATCH
VOUTA
LATCH
VOUTB
LATCH
VOUTC
LATCH CONTROL LOGIC
VOUTD
AD7226
AGND
AGND
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
AD7226 contains four 8-bit voltage-output digital-toanalog converters, with output buffer amplifiers interface logic single monolithic chip. external trims required achieve full specified performance part. Separate on-chip latches provided each four converters. Data transferred into these data latches through common 8-bit TTL/CMOS compatible input port. Control inputs determine which loaded when goes low. control logic speed-compatible with most 8-bit microprocessors. Each converter includes output buffer amplifier capable driving output current. amplifiers' offsets laser-trimmed during manufacture, thereby eliminating requirement offset nulling. Specified performance guaranteed input reference voltages from 12.5 with dual supplies. part also specified single supply operation reference AD7226 fabricated ion-implanted high speed Linear Compatible CMOS (LC2MOS) process, which been specifically developed allow high speed digital logic circuits precision analog circuits integrated same chip.
DAC-to-DAC Matching Since four DACs fabricated same chip same time, precise matching tracking between DACs inherent. Single-Supply Operation voltage mode configuration DACs allows AD7226 operated from single power supply rail. Microprocessor Compatibility AD7226 common 8-bit data with individual latches, providing versatile control architecture simple interface microprocessors. latch enable signals level triggered. Small Size Combining four DACs four amps plus interface logic into 20-pin package allows dramatic reduction board space requirements offers increased reliability systems using multiple converters. pinout aimed optimizing board layout with analog inputs outputs package digital inputs other.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 2003 Analog Devices, Inc. rights reserved.
AD7226-SPECIFICATIONS
DUAL SUPPLY
Parameter STATIC PERFORMANCE Resolution Total Unadjusted Error Relative Accuracy Differential Nonlinearity Full-Scale Error Full-Scale Temperature Coefficient Zero Code Error Zero Code Error Temperature Coefficient REFERENCE INPUT Voltage Range Input Resistance Input Capacitance3 DIGITAL INPUTS Input High Voltage, VINH Input Voltage, VINL Input Leakage Current Input Capacitance Input Coding DYNAMIC PERFORMANCE Voltage Output Slew Rate4 Voltage Output Settling Time4 Digital Crosstalk Minimum Load Resistance POWER SUPPLIES Range SWITCHING CHARACTERISTICS4, Address Write Setup Time, Address Write Hold Time, Data Valid Write Setup Time, Data Valid Write Hold Time, Write Pulsewidth,
(VDD 11.4 16.5 10%, AGND DGND VREF (VDD V)1, unless otherwise noted. Specifications TMIN TMAX unless otherwise noted.)
Versions2 (VDD Binary 11.4/16.5
Unit Bits ppm/C mV/C
Conditions/Comments
VREF Guaranteed Monotonic 16.5 VREF
Occurs when each loaded with Occurs when each loaded with
V/ms secs min/V
VREF Settling Time VOUT Specified Performance Outputs Unloaded; VINL VINH Outputs Unloaded; VINL VINH
NOTES Maximum possible reference voltage. Temperature ranges follows: Version: -40C +85C Version: -40C +85C Guaranteed design. production tested. Sample Tested ensure compliance. Switching Characteristics apply single dual supply operation. Specifications subject change without notice.
REV.
AD7226 SINGLE SUPPLY
Parameter STATIC PERFORMANCE Resolution Total Unadjusted Error Differential Nonlinearity REFERENCE INPUT Input Resistance Input Capacitance3 DIGITAL INPUTS Input High Voltage, VINH Input Voltage, VINL Input Leakage Current Input Capacitance Input Coding DYNAMIC PERFORMANCE Voltage Output Slew Rate4 Voltage Output Settling Time4 Digital Crosstalk Minimum Load Resistance POWER SUPPLIES Range
NOTES Maximum possible reference voltage. Temperature ranges follows: Version: -40C +85C Version: -40C +85C Guaranteed design. production tested. Sample Tested ensure compliance. Specifications subject change without notice.
(VDD AGND DGND VREF unless otherwise noted. specifications TMIN TMAX unless otherwise noted.)
Versions2 Binary 14.25/15.75 Unit Bits Conditions/Comments
Guaranteed Monotonic
Occurs when each loaded with Occurs when each loaded with
V/ms secs min/V
Settling Time VOUT Specified Performance Outputs Unloaded; VINL VINH
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE Temperature Range -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C Total1 Unadjusted Error Package Option2 N-20 P-20A RW-20 Q-20 RS-20
Model AD7226KN AD7226KP AD7226KR AD7226BQ AD7226BRS
NOTES Dual-Supply Operation Plastic DIP; Plastic Leaded Chip Carrier; CERDIP; SOIC; SSOP
AGND -0.3 DGND -0.3 AGND DGND -0.3 AGND DGND -0.3 Digital Input Voltage DGND -0.3 VREF AGND -0.3 VOUT AGND2 VSS, Power Dissipation (Any Package) Derates above mW/C Operating Temperature Commercial Version) -40C +85C Industrial Version) -40C +85C Storage Temperature -65C +150C Lead Temperature (Soldering, secs) 300C
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Outputs shorted AGND provided that power dissipation package exceeded. Typically short circuit current AGND
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7226 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
REV.
AD7226
CONFIGURATIONS SOIC/SSOP
VOUTB VOUTA VREF AGND DGND VOUTC VOUTD
AD7226
VIEW (Not Scale) DB0(LSB) (MSB)
PLCC
VOUTB
VOUTC
VOUTD
DB0(LSB)
AGND DGND (MSB)
VIEW (Not Scale)
VOUTA
AD7226
TERMINOLOGY TOTAL UNADJUSTED ERROR
DIFFERENTIAL NONLINEARITY
This comprehensive specification that includes full-scale error, relative accuracy zero code error. Maximum output voltage VREF (ideal), where (ideal) VREF/ 256. size will vary over VREF range. Hence zero code error will, relative size, increase VREF decreases. Accordingly, total unadjusted error, which includes zero code error, will also vary terms LSB's over VREF range. result, total unadjusted error specified fixed reference voltage
RELATIVE ACCURACY
Differential Nonlinearity difference between measured change ideal change between adjacent codes. specified differential nonlinearity over operating temperature range ensures monotonicity.
DIGITAL CROSSTALK
glitch impulse transferred output converter change digital input code another converters. specified secs measured VREF
FULL SCALE ERROR
Full-Scale Error defined Measured Value Zero Code Error Ideal Value
Relative Accuracy endpoint nonlinearity, measure maximum deviation from straight line passing through endpoints transfer function. measured after allowing zero full-scale error normally expressed LSB's percentage full-scale reading.
REV.
AD7226
CIRCUIT INFORMATION SECTION
single supply operation (VSS AGND), with output approaching AGND (i.e., digital code approaching
AD7226 contains four identical, 8-bit, voltage mode digital-toanalog converters. output voltages from converters have same polarity reference voltage allowing single supply operation. novel switch pair arrangement AD7226 allows reference voltage range from 12.5 Each consists highly stable, thin-film, R-2R ladder eight high speed NMOS, single-pole, double-throw switches. simplified circuit diagram channel shown Figure Note that VREF (Pin AGND (Pin common four DACs.
Figure Amplifier Output Stage
VREF AGND SHOWN VOUT
current load ceases current sink begins resistive load approximately AGND. This occurs NMOS transistors come saturation. This means that, single supply operation, sink capability amplifiers reduced when output voltage near AGND. typical plot variation current sink capability with output voltage shown Figure
Figure Simplified Circuit Diagram
input impedance VREF AD7226 parallel combination four individual reference input impedances. code dependent vary from infinity. lowest input impedance (i.e., occurs when four DACs loaded with digital code 01010101. Therefore, important that reference presents output impedance under changing load conditions. nodal capacitance reference terminals also code dependent typically varies from Each VOUT considered digitally programmable voltage source with output voltage
VOUTX
ISINK
+15V
VOUT
where fractional representation digital input code vary from 255/256. source impedance output resistance buffer amplifier.
SECTION
Figure Variation ISINK with VOUT
Each voltage-mode converter output buffered unity gain, noninverting CMOS amplifier. This buffer amplifier capable developing across load drive capacitive loads 3300 output stage this amplifier consists bipolar transistor from line current load VSS, negative supply output amplifiers. This output stage shown Figure transistor supplies required output current drive mA). current load consists NMOS transistors which normally constant current sink VSS, giving each output current sink capability approximately required. AD7226 operated single dual supply resulting different performance some parameters from output amplifiers.
full sink capability required with output voltages near AGND then brought below thereby maintain current sink indicated Figure Biasing below also gives additional headroom output amplifier which allows better zero code error performance each output. Also improved slew rate negative-going settling time amplifiers (discussed later). Each amplifier offset laser trimmed during manufacture eliminate requirement offset nulling.
DIGITAL SECTION
digital inputs AD7226 both CMOS compatible from 11.4 16.5 logic inputs static protected gates with typical input currents less than Internal input protection achieved on-chip distributed diode from DGND each gate. minimize power supply currents, recommended that digital input voltages driven close supply rails (VDD DGND) practically possible.
REV.
AD7226
INTERFACE LOGIC INFORMATION
Address lines select which will accept data from input port. Table shows selection table four DACs with Figure showing input control logic. When signal LOW, input latches selected transparent output responds activity data bus. data latched into addressed latch rising edge While high analog outputs remain value corresponding data held their respective latches.
Table AD7226 Truth Table
LATCH
LATCH
LATCH
LATCH
AD7226 Control Inputs
AD7226 Operation Operation Device Selected Transparent Latched Transparent Latched Transparent Latched Transparent Latched
Figure Input Control Logic
DATA VINH VINL
ADDRESS VINH VINL
State, High State, Don't Care
NOTES INPUT SIGNAL RISE FALL TIMES MEASURED FROM VDD. 20ns OVER RANGE. TIMING MEASUREMENT REFERENCE LEVEL VINH VINL
SELECTED INPUT LATCH TRANSPARENT WHILE LOW, THUS INVALID DATA DURING THIS TIME CAUSE SPURIOUS OUTPUTS.
Figure Write Cycle Timing Diagram
REV.
Typical Performance Characteristics-AD7226
AD7226K,
VREF -0.5 -1.0 -1.5 -2.0
DIFFERENTIAL NONLINEARITY (LSBs)
TOTAL UNADJUSTED ERROR (LSBs)
VREF
INPUT CODE (DECIMAL EQUIVALENT)
Channel-to-Channel Matching
Differential Nonlinearity VREF
AD7226K,
RELATIVE ACCURACY (LSBs)
VREF
ZERO CODE ERROR (LSBs)
VOUT -0.5 -1.0 -1.5 -2.0 VOUTD VOUTB VOUTC
TEMPERATURE
Relative Accuracy VREF
Zero Code Error Temperature
REV.
AD7226
SPECIFICATION RANGES
order DACs operate their specifications, reference voltage must least below power supply voltage. This voltage differential required correct generation bias voltages switches. AD7226 specified operate over range from (i.e., from +11.4 +16.5 with 10%. Operation also specified single supply. Applying results improved zero code error, improved output sink capability with outputs near AGND improved negative-going settling time. Performance specified over wide range reference voltages from (VDD with dual supplies. This allows range standard reference generators used such AD780, band reference AD584, precision reference. Note that order achieve output voltage range nominal power supply voltage required AD7226.
SETTLING TIME
DATA
+1/2 -1/2
Figure Positive Step Settling Time (VSS
DATA
output stage buffer amplifiers consists bipolar transistor from line constant current load VSS. negative power supply output buffer amplifiers. mentioned section, single supply operation NMOS transistor will come saturation output voltage approaches AGND will resistive load approximately AGND. result, settling time negative-going signals approaching AGND single supply operation will longer than dual supply operation where current load maintained down AGND. Positive-going settling-time affected VSS. settling-time AD7226 limited slew-rate output buffer amplifiers. This seen from Figure which shows dynamic response AD7226 full scale change. Figures show expanded settling-time photographs with output waveforms derived from differential input oscilloscope. Figure shows settling time positive-going step Figure shows settling time negative-going output step.
+1/2
-1/2
Figure Negative Step Settling Time (VSS
GROUND MANAGEMENT
transient voltages between AGND DGND cause noise analog output. This especially true microprocessor systems where digital noise prevalent. simplest method ensuring that voltages AGND DGND equal AGND DGND together AD7226. more complex systems where AGND DGND intertie backplane, recommended that diodes connected inverse parallel between AD7226 AGND DGND pins (IN914 equivalent).
Unipolar Output Operation
DATA
VOUT
This basic mode operation each channel AD7226, with output voltage having same positive polarity +VREF. AD7226 operated single supply (VSS AGND) with positive/negative supplies (see section which outlines advantages having negative VSS). code table unipolar output operation shown Table Note that voltage VREF must never negative with respect DGND order prevent parasitic transistor turn-on. Connections unipolar output operation shown Figure
Figure Dynamic Response (VSS
REV.
AD7226
VREF
With
VOUT
VOUTA
where fractional representation digital word latch Mismatch between causes gain offset errors therefore these resistors must match track over temperature. Once again AD7226 operated single supply from positive/negative supplies. Table shows digital code versus output voltage relationship circuit Figure with
VREF
VOUTB
VOUTC
VOUTD
VREF
+15V
AD7226*
VOUTA
VOUT -15V
AGND
DGND
0.1%
Figure AD7226 Unipolar Output Circuit
AGND DGND
*DIGITAL INPUTS OMITTED CLARITY
Table Unipolar Code Table
Figure AD7226 Bipolar Output Circuit
Latch Contents 1111 1111
Analog Output
Table III. Bipolar (Offset Binary) Code Table
Latch Contents 1111 1000 1000 0111 0000 0000
AGND BIAS
Analog Output
1000
0001
1111 0001 0000 1111 0001 0000
1000
0000
0111
1111
0000
0001
0000
0000
Note: (VREF VREF
Bipolar Output Operation
Each DACs AD7226 individually configured provide bipolar output operation. This possible using external amplifier resistors channel. Figure shows circuit used implement offset binary coding (bipolar operation) with AD7226. this case
VOUT DAVREF (VREF
AD7226 AGND biased above system (AD7226 DGND) provide offset "zero" analog output voltage level. Figure shows circuit configuration achieve this channel AD7226. output voltage, VOUTA, expressed VOUT VBIAS (VIN where fractional representation digital input word 255/256).
REV.
AD7226
VREF
AD7226*
VOUTA
AGND
VBIAS
DGND
generated software with each converter being loaded from separate loop. loops through look-up table producing successive triads sinusoidal values with separation which loaded converters producing three sine wave voltages apart. complete sine wave cycle generated stepping through full look-up table. 256-element sine wave table used then resolution circuit will (360/256). Figure shows typical resulting waveforms. sine waves smoothed filtering converter outputs. fourth converter AD7226, used feedback configuration provide programmable reference voltage itself other three converters. This configuration shown Figure relationship VREF dependent upon digital code upon ratio given formula.
*DIGITAL INPUTS OMITTED CLARITY
Figure AGND Bias Circuit
given VIN, increasing AGND above system will reduce effective VDD-VREF which must least ensure specified operation. Note that because AGND common four DACs, this method biases output voltages DACs AD7226. Note that AD7226 should referenced DGND.
3-PHASE SINE WAVE
where RF/R fractional representation digital word latch Alternatively, given resistance ratio, required value given value VREF determined from expression Figure shows typical plots VREF versus digital code three different values With peak-to-peak sine wave voltage from converter outputs will vary between over digital input code range 255.
VREF VOUTA VOUTB VOUTC VOUTD
circuit Figure shows application AD7226 generation 3-phase sine waves which used control small 3-phase motors. proper codes synthesizing full sine wave stored EPROM, with required phaseshift between three converter outputs being generated software. Data loaded into three converters from sine EPROM microprocessor control logic. Three loops
ADDRESS
MICROPROCESSOR CONTROL LOGIC
SINE EPROM
ADDRESS DECODE
AD7226
DATA
Figure 3-Phase Sine Wave Generation Circuit
VOUTA
VREF
VOUTB
VOUTC
DIGITAL CODE (Decimal Equivalent)
Figure Variation VREF with Feedback Configuration
Figure 3-Phase Sine Wave Output
-10-
REV.
AD7226
STAIRCASE WINDOW COMPARATOR
many test systems, important able determine whether some parameter lies within defined limits. staircase window comparator Figure circuit that used, example, measure thresholds device under test. Upper lower limits both programmably using AD7226. Each adjacent pair comparators forms window programmable size. VTEST lies within window, then output that window will high. With reference 2.56 applied VREF input, minimum window size
VTEST FROM D.U.T. CA339 VREF (HIGH) VOUTA WINDOW WINDOW
VTEST FROM D.U.T.
VREF VOUTA VOUTB WINDOW
AD7226
VOUTC VOUTD AGND
WINDOW
WINDOW
Figure 15a. Overlapping Windows
VREF WINDOW VOUTB VOUTA WINDOW VOUTD
(LOW) VOUTB
AD7226
(HIGH) VOUTC
WINDOW
VOUTC AGND
WINDOW
Figure 15b. Window Structure
WINDOW
+15V
VOUTD AGND
(LOW)
VREF *DIGITAL INPUTS OMITTED CLARITY
WINDOW
AD7226*
VOUTA
Figure 14a. Logic Level Measurement
VREF WINDOW VOUTA VOUTB WINDOW
AGND
DGND
WINDOW VOUTC WINDOW VOUTD WINDOW AGND
Figure Varying Reference Signal
VARYING REFERENCE SIGNAL
Figure 14b. Window Structure
circuit easily adapted allow overlapping windows shown Figure 15a. three outputs from this circuit decoded then five different nonoverlapping programmable windows again defined.
some applications, desirable have varying signal applied reference input AD7226. AD7226 multiplying capability within upper lower limits reference voltage when operated with dual supplies. upper lower limits those required AD7226 achieve linearity specification. Figure shows sine wave signal applied reference input AD7226. input signal frequencies kHz, output distortion typically remains less than 0.1%. Typical bandwidth figure kHz.
REV.
-11-
AD7226
OFFSET ADJUST
+10V
Figure shows AD7226 used provide programmable input offset voltage adjustment AD544 amp. Each output AD7226 used trim input offset voltage AD544. resistor tied provides fixed bias current offset node. symmetrical adjustment, this bias current should equal current other offset node with half-full scale code (i.e., 10000000) DAC. Changing code varies bias current hence provides offset adjust AD544. example, input offset voltage AD544J, which maximum programmably trimmed
VREF
+15V
AD7226*
VOUTA 500k
620k
AGND
DGND -15V *DIGITAL INPUTS OMITTED CLARITY
Figure Offset Adjust AD544
8085A ADDRESS ADDRESS DECODE
6502
ADDRESS
AD7226*
ADDRESS DECODE
AD7226*
8212
ADDRESS/DATA *LINEAR CIRCUITRY OMITTED CLARITY
DATA *LINEAR CIRCUITRY OMITTED CLARITY
Figure AD7226 8085A Interface
6809 ADDRESS ADDRESS DECODE Z-80
Figure AD7226 6502 Interface
ADDRESS ADDRESS DECODE
AD7226*
AD7226*
DATA *LINEAR CIRCUITRY OMITTED CLARITY
DATA *LINEAR CIRCUITRY OMITTED CLARITY
Figure AD7226 6809 Interface
Figure AD7226 Z-80 Interface
-12-
REV.
AD7226
OUTLINE DIMENSIONS 20-Lead Plastic Dual In-Line Package [PDIP] (N-20)
Dimensions shown inches (millimeters)
0.985 (25.02) 0.965 (24.51) 0.945 (24.00)
0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62)
0.180 (4.57)
0.015 (0.38)
0.150 (3.81) 0.135 (3.43) 0.120 (3.05)
0.150 (3.81) 0.130 (3.30) 0.110 (2.79)
0.022 (0.56) 0.018 (0.46) 0.014 (0.36)
0.100 0.060 (1.52) SEATING (2.54) 0.050 (1.27) PLANE 0.045 (1.14)
0.015 (0.38) 0.010 (0.25) 0.008 (0.20)
COMPLIANT JEDEC STANDARDS MO-095-AE CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
20-Lead Ceramic Dual In-Line Package [CERDIP] (Q-20)
Dimensions shown inches (millimeters)
0.005 (0.13)
0.098 (2.49)
0.310 (7.87) 0.220 (5.59)
0.200 (5.08)
1.060 (26.92)
0.060 (1.52) 0.015 (0.38) 0.150 (3.81)
0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20)
0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36)
0.100 (2.54)
0.070 (1.78) SEATING 0.030 (0.76) PLANE
CONTROLLING DIMENSIONS INCHES; MILLIMETERS DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
20-Lead Shrink Small Outline Package [SSOP] (RS-20)
Dimensions shown millimeters
7.50 7.20 6.90
8.20 7.80 7.40
5.60 5.30 5.00
2.00
1.85 1.75 1.65
0.25 0.09 0.95 0.75 0.55
0.05 COPLANARITY 0.10
0.65
0.38 0.22
SEATING PLANE
COMPLIANT JEDEC STANDARDS MO-150AE
REV.
-13-
AD7226
OUTLINE DIMENSIONS
20-Lead Standard Small Outline Package [SOIC] Wide Body (RW-20)
Dimensions shown millimeters (inches)
13.00 (0.5118) 12.60 (0.4961)
7.60 (0.2992) 7.40 (0.2913)
10.65 (0.4193) 10.00 (0.3937)
0.30 (0.0118) 0.10 (0.0039) 1.27 (0.0500)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
COPLANARITY 0.10
0.51 (0.0201) SEATING 0.32 (0.0126) PLANE 0.33 (0.0130) 0.23 (0.0091)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT JEDEC STANDARDS MS-013AC CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS PARENTHESES) ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
20-Lead Plastic Leaded Chip Carrier [PLCC] (P-20A)
Dimensions shown inches (millimeters)
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07)
0.048 (1.21) 0.042 (1.07)
0.20 (0.51) 0.021 (0.53) 0.013 (0.33)
0.020 (0.50)
0.048 (1.21) 0.042 (1.07)
VIEW
(PINS DOWN)
0.050 (1.27)
0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) 0.120 (3.04) 0.090 (2.29)
BOTTOM VIEW
(PINS
0.020 (0.50)
0.356 (9.04) 0.350 (8.89) 0.395 (10.02) 0.385 (9.78)
COMPLIANT JEDEC STANDARDS MO-047AA CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
-14-
REV.
AD7226 Revision History
Location 3/03-Data Sheet changed from REV. REV. Page
Title Revision
3/03-Data Sheet changed from REV. REV.
Edits FEATURES Edits SPECIFICATIONS Edits ORDERING GUIDE Edits ABSOLUTE MAXIMUM RATINGS Edits CONFIGURATIONS Edits SPECIFICATIONS RANGES OUTLINE DIMENSIONS updated RS-20 package added Updated RS-20 package OUTLINE DIMENSIONS
REV.
-15-
-16-
C00987-0-3/03(C)
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