June 1996 (Version 1.0) Features Enhanced, high performance

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June 1996 (Version 1.0) Features Enhanced, high performance

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XC3000A Field Programmable Gate Arrays
June 1996 (Version 1.0)
Features
Enhanced, high performance FPGA family with five device types Improved redesign basic XC3000 FPGA family Logic densities from 1,000 6,000 gates user-definable I/Os Superset industry-leading XC3000 family Identical basic XC3000 structure, out, design methodology, software tools 100% compatible with XC3000, XC3000L, XC3100A bitstreams Improved routing additional features Additional programmable interconnection points (PIPs) Improved access longlines clock enable inputs Most efficient XC3000-class solution bus-oriented designs Advanced CMOS static memory technology quiescent active power consumption Performance specified logic delays, faster than corresponding XC3000 versions XC3000A-specific features output sink source current Error checking configuration bitstream Soft startup starts outputs slew-limited mode upon power-up Easy migration XC3400 series HardWire mask programmed devices high-volume production. Device XC3020A XC3030A XC3042A XC3064A XC3090A Logic Gates 1,500 2,000 3,000 5,000 6,000 Typical Gate Range 1,000 1,500 1,500 2,000 2,000 3,000 4,000 5,000 5,000 6,000 CLBs
Description
XC3000A family offers following enhancements over popular XC3000 family: XC3000A family additional interconnect resources drive I-inputs TBUFs driving horizontal Longlines. Clock Enable input driven from second vertical Longline. These additions result more efficient faster designs when horizontal Longlines used data bussing. During configuration, XC3000A devices check bitstream format stop bits appropriate positions. error terminates configuration pulls INIT Low. When configuration process finished device starts user mode, first activation outputs automatically slew-rate limited. This feature, called Soft Startup, avoids potential ground bounce when outputs turned simultaneously. After start-up, slew rate individual outputs XC3000 family, determined individual configuration option. XC3000A family superset XC3000 family. bitstream used configure XC3000, XC3100 XC3100A device configures XC3000A device exactly same way.
Array
User I/Os Horizontal Configuration Flip-Flops Longlines Data Bits 14,779 22,176 30,784 46,064 64,160
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XC3000A Field Programmable Gate Arrays
XC3000A Switching Characteristics
Xilinx maintains test specifications each product controlled documents. insure most recently released device performance parameters, please request copy current test-specification revision.
XC3000A Operating Conditions
Symbol VIHT VILT VIHC VILC Note: Description Supply voltage relative Commercial +85°C junction Supply voltage relative Industrial -40°C +100°C junction High-level input voltage configuration Low-level input voltage configuration High-level input voltage CMOS configuration Low-level input voltage CMOS configuration Input signal transition time 4.75 5.25 100% Units
junction temperatures above those listed Operating Conditions, delay parameters increase 0.3%
XC3000A Characteristics Over Operating Conditions
Symbol VCCPD ICCPD Description High-level output voltage -4.0 min) Low-level output voltage min) High-level output voltage -4.0 min) Low-level output voltage min) Power-down supply voltage (PWRDWN must Low) Power-down supply current (VCC(MAX) TMAX) 3.86 3.76 0.40 2.30 3020A 3030A 3042A 3064A 3090A 0.40 Units
Commercial Industrial
ICCO
IRIN IRLL
Quiescent FPGA supply current addition ICCPD Chip thresholds programmed CMOS levels Chip thresholds programmed levels Input Leakage Current Input capacitance, packages except PGA175 (sample tested) Pins except XTL1 XTL2 XTL1 XTL2 Input capacitance, (sample tested) Pins except XTL1 XTL2 XTL1 XTL2 pull-up (when selected) (sample tested) Horizontal Longline pull-up (when selected) logic
0.02
0.17
Notes: With output current loads, active input Longline pull-up resistors, package pins GND, FPGA
device configured with MakeBits option. Total continuous output sink current exceed ground pin. Total continuous output source exceed pin. number ground pins varies from XC3020A XC3090A.
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XC3000A Absolute Maximum Ratings
Symbol TSTG TSOL Note: Description Supply voltage relative Input voltage with respect Voltage applied 3-state output Storage temperature (ambient) Maximum soldering temperature 1/16 in.) Junction temperature plastic Junction temperature ceramic -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 +150 +260 +125 +150 Units
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those listed under Recommended Operating Conditions implied. Exposure Absolute Maximum Ratings conditions extended periods time affect device reliability.
XC3000A Global Buffer Switching Characteristics Guidelines
Description Global Alternate Clock Distribution1 Either: Normal input through clock buffer clock input Fast (CMOS only) input through clock buffer clock input TBUF driving Horizontal Longline (L.L.)1 L.L. while (buffer active) L.L. active valid with single pull-up resistor L.L. active valid with pair pull-up resistors L.L. High with single pull-up resistor L.L. High with pair pull-up resistors BIDI Bidirectional buffer delay Speed Grade Symbol Units
TPID TPIDC TPUS TPUF TBIDI
11.0 16.0 10.0
10.0 14.0
Note: Timing based XC3042A, other devices XACT timing calculator.
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XC3000A Switching Characteristics Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Since many internal timing parameters cannot measured directly, they derived from benchmark timing patterns. following guidelines reflect worst-case values over recommended operating conditions. more detailed, more precise, more up-to-date timing information, values provided XACT timing calculator used simulator. Speed Grade Symbol Units
Description Combinatorial Delay Logic Variables outputs Mode Mode
TILO
Sequential delay Clock outputs Clock outputs when returned through function generators drive Mode Mode Set-up time before clock Logic Variables Mode Mode Data Enable Clock Hold Time after clock Logic Variables Data Enable Clock Clock Clock High time Clock time Max. flip-flop toggle rate Reset Direct (RD) width delay from outputs Global Reset (RESET Pad)1 RESET width (Low) delay from RESET outputs
TCKO
TQLO
10.0
TICK TDICK TECCK TCKI TCKDI TCKEC FCLK TRPW TRIO TMRW TMRQ
113.0 16.0 19.0
135.0 14.0 17.0
Notes: Timing based XC3042A, other devices XACT timing calculator.
output delay (TCKO, CLB, plus shortest possible interconnect delay, always longer than Data hold time requirement (TCKDI, same die.
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XC3000A Switching Characteristics Guidelines (continued)
Output (Combinatorial) Input (A,B,C,D,E) Clock Input (Direct Input (Enable Clock) Output (Flip-Flop) TCKO ECCK TCKEC TDICK TCKDI
Input (Reset Direct) TRPW Output (Flip-Flop)
X5424
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XC3000A Field Programmable Gate Arrays
XC3000A Switching Characteristics Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Since many internal timing parameters cannot measured directly, they derived from benchmark timing patterns. following guidelines reflect worst-case values over recommended operating conditions. more detailed, more precise, more up-to-date timing information, values provided XACT timing calculator used simulator. Speed Grade Symbol TPID TPTG TIKRI TPICK TOKPO TOKPO TOPF TOPS TTSHZ TTSHZ TTSON TTSON TOOK TOKO TIOH TIOL FCLK TRRI TRPO TRPO 113.0 24.0 33.0 43.0 14.0 18.0 16.0 10.0 20.0 11.0 21.0 135.0 23.0 29.0 37.0 15.0 12.0 15.0 13.0 12.0 10.0 18.0 14.0 Units
Description Propagation Delays (Input) Direct Registered with latch transparent Clock (IK) Registered Set-up Time (Input) Clock (IK) set-up time Propagation Delays (Output) Clock (OK) (fast) same (slew rate limited) Output (fast) same (slew-rate limited) 3-state begin hi-Z (fast) same (slew-rate limited) 3-state active valid (fast) same (slew -rate limited) Set-up Hold Times (Output) Output clock (OK) set-up time Output clock (OK) hold time Clock Clock High time Clock time Max. flip-flop toggle rate Global Reset Delays (based XC3042A) RESET Registered RESET output (fast) (slew-rate limited)
Notes: Timing measured threshold, with external capacitive loads (incl. test fixture). Typical slew rate limited output rise/fall times approximately four times longer. Voltage levels unused (bonded unbonded) pads must valid logic levels. Each configured with internal pull-up resistor alternatively configured driven output driven from external source. Input set-up time specified with respect internal clock (ik). order calculate system set-up time, subtract clock delay (pad from input set-up time value. Input holdtime with respect internal clock (ik) negative. This means that level changes immediately before internal clock edge (ik) will recognized. TPID, TPTG, TPICK higher XTL2 when configures user input.
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XC3000A Switching Characteristics Guidelines (continued)
Block Input Clock (IK/OK) TIOL Block (RI) RESET Block Output (Direct) Output (Registered) TOKPO TOOK TOKO TRPO TIKRI TRRI TIOH PICK
Output
X5425
TTSON
TSHZ
PROGRAM-CONTROLLED MEMORY CELLS
INVERT
3-STATE INVERT
OUTPUT SELECT
SLEW RATE
PASSIVE PULL
STATE (OUTPUT ENABLE)
FLIP FLOP
OUTPUT BUFFER
DIRECT REGISTERED FLIP FLOP LATCH (GLOBAL RESET) CMOS INPUT THRESHOLD
PROGRAM CONTROLLED MULTIPLEXER PROGRAMMABLE INTERCONNECTION POINT
X3029
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XC3000A Field Programmable Gate Arrays
Product Availability
PINS TYPE CODE XC3020A XC3030A XC3042A XC3064A XC3090A PLAST. PLCC PC44 PLAST. VQFP VQ64 PLAST. PLCC PC68 PLAST. PLCC PC84 CERAM PG84 PLAST. PQFP PQ100 PLAST. TQFP TQ100 PLAST. VQFP VQ100 TOPBRAZED CQFP CB100
PINS TYPE CODE XC3020A XC3030A XC3042A XC3064A XC3090A Note:
PLAST. CERAM. PLAST. TQFP PP132 PG132 TQ144
TOPPLAST. PLAST. CERAM. PLAST. BRAZED PQFP TQFP CQFP PQ160 CB164 PP175 PG175 TQ176
PLAST. CERAM. PQFP PQ208 PG223
Commercial, +85°C
Industrial, -40° +100°C
Ordering Information
Example: XC3020A-6PC84C Device Type Speed Grade Temperature Range Number Pins Package Type
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June 1996 (Version 1.0)

June 1996 (Version 1.0) Features Enhanced, high performance

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