24-Bit, 192kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITA

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24-Bit, 192kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITA

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PCM1742
24-Bit, 192kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER
FEATURES
24-BIT RESOLUTION ANALOG PERFORMANCE (VCC +5V): Dynamic Range: 106dB (PCM1742KE) 100dB (PCM1742E) SNR: 106dB (PCM1742KE) 100dB (PCM1742E) THD+N: 0.002% (PCM1742KE) 0.003% (PCM1742E) Full-Scale Output: 3.1Vp-p 4x/8x OVERSAMPLING DIGITAL FILTER: Stopband Attenuation: -55dB Passband Ripple: ±0.03dB SAMPLING FREQUENCY: 5kHz 200kHz SYSTEM CLOCK: 128, 192, 256, 384, 512, 768fS with Auto Detect ACCEPTS 16-, 18-, 20-, 24-BIT AUDIO DATA DATA FORMATS: Standard, I2S, LeftJustified USER-PROGRAMMABLE MODE CONTROLS: Digital Attenuation: -63dB, 0.5dB/Step Digital De-Emphasis Digital Filter Roll-Off: Sharp Slow Soft Mute Zero Flags Each Output DUAL-SUPPLY OPERATION: Analog, +3.3V Digital TOLERANT DIGITAL INPUTS SMALL SSOP-16 PACKAGE SAME PACKAGE SIZE SOP-8
APPLICATIONS
RECEIVERS MOVIE PLAYERS ADD-ON CARDS HIGH-END AUDIO PLAYERS HDTV RECEIVERS AUDIO SYSTEMS OTHER APPLICATIONS REQUIRING 24-BIT AUDIO
DESCRIPTION
PCM1742 CMOS, monolithic, integrated circuit which includes stereo Digital-to-Analog Converters (DACs) support circuitry small SSOP-16 package. data converters utilize Texas Instrument's enhanced multilevel delta-sigma architecture that employs fourthorder noise shaping 8-level amplitude quantization achieve excellent dynamic performance improved tolerance clock jitter. PCM1742 accepts industry standard audio data formats with 24-bit data, providing easy interfacing audio decoder chips. Sampling rates 200kHz supported. full user-programmable functions accessible through 3-wire serial control port that supports register write functions.
Copyright 2000, Texas Instruments Incorporated
SBAS176
Printed U.S.A. December, 2000
SPECIFICATIONS
specifications +25°C, 5.0V, 3.3V, 44.1kHz, system clock 384fS, 24-bit data, unless otherwise noted. PCM1742E PCM1742KE PARAMETER RESOLUTION DATA FORMAT Audio Data Interface Formats Audio Data Length Audio Data Format Sampling Frequency (fS) System Clock Frequency DIGITAL INPUT/OUTPUT Logic Family Input Logic Level Input Logic Current IIH(1) IIL(1) IIH(2) IIL(2) Output Logic Level VOH(3) VOL(3) DYNAMIC PERFORMANCE(4) PCM1742E THD+N VOUT CONDITIONS Standard, I2S, Left-Justified 16-, 18-, 20-, 24-Bits Selectable MSB-First, Binary Two's Complement 256, 384, 512, 768fS TTL-Compatible -2mA +2mA UNITS Bits
THD+N VOUT -60dB
Dynamic Range
Signal-to-Noise Ratio
Channel Separation
Level Linearity Error PCM1742KE THD+N VOUT
44.1kHz 96kHz 192kHz 44.1kHz 96kHz 192kHz EIAJ, A-Weighted, 44.1kHz A-Weighted, 96kHz A-Weighted, 192kHz EIAJ, A-Weighted, 44.1kHz A-Weighted, 96kHz A-Weighted, 192kHz 44.1kHz 96kHz 192kHz VOUT -90dB 44.1kHz 96kHz 192kHz 44.1kHz 96kHz 192kHz EIAJ, A-Weighted, 44.1kHz A-Weighted, 96kHz A-Weighted, 192kHz EIAJ, A-Weighted, 44.1kHz A-Weighted, 96kHz A-Weighted, 192kHz 44.1kHz 96kHz 192kHz VOUT -90dB
0.003 0.004 0.005 ±0.5 0.002 0.003 0.004 0.65 0.95 ±0.5 ±1.0 ±1.0
0.008
Vp-p
0.006
THD+N VOUT -60dB
Dynamic Range
Signal-to-Noise Ratio
Channel Separation
Level Linearity Error ACCURACY Gain Error Gain Mismatch, Channel-to-Channel Bipolar Zero Error ANALOG OUTPUT Output Voltage Center Voltage Load Impedance DIGITAL FILTER PERFORMANCE Filter Characteristics Sharp Roll-Off Passband Passband Stopband Passband Ripple Stopband Attenuation Stopband Attenuation
VOUT Bipolar Zero Full Scale (0dB) Load
±0.03dB -3dB 0.546fS Stopband 0.546fS Stopband 0.567fS
0.454fS 0.487fS ±0.03
PCM1742
SBAS176
SPECIFICATIONS (Cont.)
specifications +25°C, 5.0V, 3.3V, system clock 384fS 44.1kHz), 24-bit data, unless otherwise noted. PCM1742E PCM1742KE PARAMETER DIGITAL FILTER PERFORMANCE (Cont.) Filter Characteristics Slow Roll-Off Passband Passband Stopband Passband Ripple Stopband Attenuation Delay Time De-Emphasis Error ANALOG FILTER PERFORMANCE Frequency Response POWER SUPPLY REQUIREMENTS(4) Voltage Range, Supply Current, CONDITIONS UNITS
±0.5dB -3dB 0.884fS Stopband 0.884fS 20/fS ±0.1 20kHz 44kHz +3.0 +4.5 44.1kHz 96kHz 192kHz 44.1kHz 96kHz 192kHz 44.1kHz 96kHz 192kHz SSOP-16 -0.03 -0.20 +3.3 +5.0
0.198fS 0.390fS ±0.5 +3.6 +5.5 °C/W
Power Dissipation
TEMPERATURE RANGE Operation Temperature Thermal Resistance
NOTES: Pins (SCK, BCK, LRCK, DATA). Pins 13-15 (MD, ML). Pins (ZEROR, ZEROL). Analog performance specifications tested with Shibasoku #725 Meter with 400Hz 30kHz average mode with 20kHz bandwidth limiting. load connected analog output larger, capacitive coupling. Conditions 192kHz operation are: system clock 128fS oversampling rate 64fS Register
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage, +4.0V +6.5V Ground Voltage Differences ±0.1V Digital Input Voltage -0.3V (6.5V 0.3V) Input Current (except power supply) ±10mA Ambient Temperature Under Bias -40°C +125°C Storage Temperature -55°C +150°C Junction Temperature +150°C Lead Temperature (soldering, +260°C Package Temperature reflow, 10s) +235°C
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit damaged ESD. Burr-Brown recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER SPECIFIED TEMPERATURE RANGE -25°C +85°C PACKAGE MARKING PCM1742E ORDERING NUMBER(1) PCM1742E PCM1742E/2K PCM1742KE PCM1742KE/2K TRANSPORT MEDIA Rails Tape Reel Rails Tape Reel
PRODUCT PCM1742E
PACKAGE SSOP-16
PCM1742KE
SSOP-16
-25°C +85°C
PCM1742KE
NOTE: Models with slash available only Tape Reel quantities indicated (e.g., indicates 2000 devices reel). Ordering 2000 pieces "PCM1742E/2K" will yield single 2000-piece Tape Reel.
PCM1742
SBAS176
BLOCK DIAGRAM
LRCK
Audio Serial Port 4x/8x Oversampling Digital Filter with Function Controller Serial Control Port
Output Low-Pass Filter
VOUTL
DATA
Enhanced Multilevel Delta-Sigma Modulator
VCOM
Output Low-Pass Filter VOUTR
System Clock System Clock Manager
Zero Detect
Power Supply
DGND
CONFIGURATION
VIEW SSOP
ASSIGNMENTS
NAME DATA LRCK DGND VOUTL VOUTR AGND VCOM ZEROR/ ZEROA ZEROL/NA TYPE FUNCTION Audio Data Clock Input.(1) Audio Data Digital Input.(1) L-Channel R-Channel Audio Data Latch Enable Input.(1) Digital Ground Digital Power Supply, +3.3V Analog Power Supply, Analog Output L-Channel. Analog Output R-Channel. Analog Ground Common Voltage Decoupling. Zero Flag Output R-Channel/Zero Flag Output L/R-Channel. Zero Flag Output L-Channel/No Assign. Mode Control Data Input.(2) Mode Control Clock Input.(2) Mode Control Latch Input.(2) System Clock Input.
DATA LRCK DGND VOUTL VOUTR
PCM1742
ZEROL/NA ZEROR/ZEROA VCOM AGND
NOTES: Schmitt-trigger input, tolerant. Schmitt-trigger with internal pull-down, tolerant.
ZEROR
ZEROL
AGND
PCM1742
SBAS176
TYPICAL PERFORMANCE CURVES
specifications +25°C, 5.0V, 3.3V, system clock 384fS 44.1kHz), 24-bit input data, unless otherwise noted.
DIGITAL FILTER
Digital Filter (De-Emphasis Off)
FREQUENCY RESPONSE PASSBAND (Sharp Roll-Off) 0.05 0.04 0.03
FREQUENCY RESPONSE (Sharp Roll-Off)
Amplitude (dB) Amplitude (dB)
0.02 0.01 -0.01 -0.02 -0.03
-100 -120 -140 Frequency
-0.04 -0.05 Frequency
FREQUENCY RESPONSE (Slow Roll-Off)
Amplitude (dB) Amplitude (dB)
TRANSITION CHARACTERISTICS (Slow Roll-Off)
-100 -120 -140 Frequency
Frequency
De-Emphasis
DE-EMPHASIS 32kHz) -1.0 -2.0 -3.0
Level (dB) Error (dB)
DE-EMPHASIS ERROR 32kHz) -0.1 -0.2 -0.3 -0.4 -0.5
-4.0 -5.0 -6.0 -7.0 -8.0 -9.0 -10.0 Frequency (kHz)
Frequency (kHz)
PCM1742
SBAS176
TYPICAL PERFORMANCE CURVES (Cont.)
specifications +25°C, 5.0V, 3.3V, system clock 384fS 44.1kHz), 24-bit input data, unless otherwise noted.
De-Emphasis (Cont.)
DE-EMPHASIS 44.1kHz) -1.0 -2.0 -3.0
Level (dB) Error (dB)
DE-EMPHASIS ERROR 44.1kHz) -0.1 -0.2 -0.3 -0.4 -0.5
-4.0 -5.0 -6.0 -7.0 -8.0 -9.0 -10.0 Frequency (kHz)
Frequency (kHz)
DE-EMPHASIS 48kHz) -1.0 -2.0 -3.0
Level (dB) Error (dB)
DE-EMPHASIS ERROR 48kHz) -0.1 -0.2 -0.3 -0.4 -0.5
-4.0 -5.0 -6.0 -7.0 -8.0 -9.0 -10.0 Frequency (kHz)
Frequency (kHz)
ANALOG DYNAMIC PERFORMANCE
specifications +25°C, 5.0V, 3.3V, 24-bit input data, unless otherwise noted. Conditions 192kHz operation are: system clock 128fS oversampling rate 64fS Register
Supply-Voltage Characteristics
THD+N (VDD 3.3V) -60dB/192kHz, 384fS
THD+N
DYNAMIC RANGE (VDD 3.3V)
-60dB/96kHz, 384fS
Dynamic Range (dB)
44.1kHz, 384fS 96kHz, 384fS 192kHz, 384fS
-60dB/44.1kHz, 384fS 0dB/192kHz, 384fS 0.01 0dB/44.1kHz, 384fS 0.001 0dB/96kHz, 384fS
PCM1742
SBAS176
TYPICAL PERFORMANCE CURVES (Cont.)
specifications +25°C, 5.0V, 3.3V, 24-bit input data, unless otherwise noted. Conditions 192kHz operation are: system clock 128fS oversampling rate 64fS Register
Supply-Voltage Characteristics (Cont.)
(VDD 3.3V) 44.1kHz, 384fS
CHANNEL SEPARATION (VDD 3.3V)
Channel Separation (dB)
96kHz, 384fS
44.1kHz, 384fS
(dB)
192kHz, 384fS
96kHz, 384fS 192kHz, 384fS
Temperature Characteristics
THD+N -60dB/192kHz, 384fS
Dynamic Range (dB)
DYNAMIC RANGE -60dB/96kHz, 384fS
192kHz, 384fS 44.1kHz, 384fS 96kHz, 384fS
THD+N
-60dB/44.1kHz, 384fS 0dB/96kHz, 384fS 0dB/96kHz, 384fS
0.01
0.001
0dB/44.1kHz, 384fS
0.0001 Temperature (°C)
Temperature (°C)
96kHz, 384fS
CHANNEL SEPARATION
Channel Separation (dB)
44.1kHz, 384fS
192kHz, 384fS 44.1kHz, 384fS 96kHz, 384fS
(dB)
Temperature (°C) 192kHz, 384fS
Temperature (°C)
PCM1742
SBAS176
SYSTEM CLOCK RESET FUNCTIONS
SYSTEM CLOCK INPUT PCM1742 requires system clock operating digital interpolation filters multilevel delta-sigma modulators. system clock applied input (pin 16). Table shows examples system clock frequencies common audio sampling rates. Figure shows timing requirements system clock input. optimal performance, important clock source with phase jitter noise. PLL1700 multiclock generator from Texas Instruments excellent choice providing PCM1742 system clock.
POWER-ON RESET FUNCTIONS PCM1742 includes power-on reset function, shown Figure With system clock active, 2.0V (typical 1.6V 2.4V), power-on reset function will enabled. initialization sequence requires 1024 system clocks from time 2.0V. After initialization period, PCM1742 will reset default state, described Mode Control Register section this data sheet. During reset period (1024 system clocks), analog outputs forced bipolar zero level, VCC/2. After reset period, internal register initialized next 1/fS period and, SCK, BCK, LRCK provided continuously, PCM1742 provides proper analog output with unit group delay against input data.
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz) SAMPLING FREQUENCY 8kHz 16kHz 32kHz 44.1kHz 48kHz 88.2kHz 96kHz 192kHz 128fS 24.5760 192fS 36.8640 256fS 2.0480 4.0960 8.1920 11.2896 12.2880 22.5792 24.5760 Note 384fS 3.0720 6.1440 12.2880 16.9344 18.4320 33.8688 36.8640 Note 512fS 4.0960 8.1920 16.3840 22.5792 24.5760 45.1584 49.1520 Note 768fS 6.1440 12.2880 24.5760 33.8688 36.8640 Note Note Note
NOTE: This system clock supported given sampling frequency.
TABLE System Clock Rates Common Audio Sampling Frequencies.
tSCKH System Clock tSCKL System clock pulse cycle time(1) 0.8V 2.0V
System Clock Pulse Width HIGH tSCKH: (min) System Clock Pulse Width tSCKL: (min) NOTE: 1/256fS, 1/384fS, 1/512fS, 1/768fS.
FIGURE System Clock Input Timing.
2.4V
2.0V 1.6V
Reset Internal Reset Don't Care System Clock 1024 System Clocks
Reset Removal
FIGURE Power-On Reset Timing.
PCM1742
SBAS176
AUDIO SERIAL INTERFACE audio serial interface PCM1742 comprised 3-wire synchronous serial port. includes LRCK (pin (pin DATA (pin serial audio clock, used clock serial data present DATA into audio interface's serial shift register. Serial data clocked into PCM1742 rising edge BCK. LRCK serial audio left/right word clock used latch serial data into serial audio interface's internal registers. Both LRCK should synchronous system clock. Ideally, recommended that LRCK derived from system clock input, SCK. LRCK operated sampling frequency, operated times sampling frequency (I2S format except 32fS). Internal operation PCM1742 synchronized with LRCK. Accordingly,
held when sampling rate clock LRCK changed and/or broken least clock cycle. SCK, BCK, LRCK provided continuously after this hold condition, internal operation will resynchronized automatically, less than 3/fS period. this resynchronize period, following 3/fS, analog output forced bipolar zero level, VCC/2. External resetting required. AUDIO DATA FORMATS TIMING PCM1742 supports industry-standard audio data formats, including Standard, I2S, Left-Justified, shown Figure Data formats selected using format bits, FMT[2:0], Control Register default data format 24-bit left justified. formats require Binary Two's Complement, MSB-first audio data. Figure detailed timing diagram serial audio interface.
Standard Data Format: L-Channel HIGH, R-Channel
1/fS
LRCK 64fS) 16-Bit Right-Justified, 48fS 64fS DATA
L-Channel
R-Channel
16-Bit Right-Justified, 32fS DATA
18-Bit Right-Justified DATA 20-Bit Right-Justified DATA 24-Bit Right-Justified DATA
Data Format: L-Channel LOW, R-Channel HIGH
1/fS LRCK L-Channel
R-Channel
64fS) DATA
Left-Justified Data Format: L-Channel HIGH, R-Channel
1/fS
LRCK 64fS) DATA
L-Channel R-Channel
FIGURE Audio Data Input Formats.
PCM1742
SBAS176
LRCK tBCH tBCY DATA tBCL
SYMBOL tBCY tBCH tBCL
PARAMETER Pulse Cycle Time High Level Time Level Time Rising Edge LRCK Edge LRCK Falling Edge Rising Edge DATA Time DATA Hold Time
64fS(1)
UNITS
NOTE: sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.)
FIGURE Audio Interface Timing. SERIAL CONTROL INTERFACE serial control interface 3-wire serial port that operates asynchronously serial audio interface. serial control interface utilized program on-chip mode registers. control interface includes (pin 13), (pin 14), (pin 15). serial data input, used program mode registers, serial clock, used shift data into control port, control port latch clock. REGISTER WRITE OPERATION write operations serial control port 16-bit data words. Figure shows control data word format. most significant must "0". There seven bits, labeled IDX[6:0], that register index address) write operation. least significant eight bits, D[7:0], contain data written register specified IDX[6:0]. Figure shows functional timing diagram writing serial control port. held logic state until register needs written. start register write cycle, logic "0". Sixteen clocks then provided corresponding bits control data word After sixteenth clock cycle completed, logic latch data into indexed mode control register. CONTROL INTERFACE TIMING REQUIREMENTS Figure detailed timing diagram serial control interface. These timing parameters critical proper control port operation.
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
Register Index Address)
Register Data
FIGURE Control Data Word Format MDI.
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 IDX6
FIGURE Register Write Operation.
PCM1742
SBAS176
MODE CONTROL REGISTERS User-Programmable Mode Controls PCM1742 includes number user-programmable functions that accessed control registers. registers programmed using Serial Control Interface that previously discussed this data sheet. Table lists
available mode control functions, along with their reset default conditions associated register index. Register mode control register shown Table III. Each register includes index address) indicated IDX[6:0] bits.
tMHH tMLS tMCY tMDS tMCH tMCH tMCL tMLH
SYMBOL tMCY tMCL tMCH tMHH tMLS tMLH tMDH tMDS
PARAMETER Pulse Cycle Time Level Time High Level Time High Level Time Falling Edge Rising Edge Hold Time(1) Hold Time Time
Note
UNITS
NOTES: rising edge rising edge. (min), Sampling Rate.
FIGURE Control Interface Timing.
FUNCTION RESET DEFAULT CONTROL REGISTER INDEX, IDX[6:0]
Digital Attenuation Control, -63dB 0.5dB Steps Soft Mute Control Oversampling Rate Control 128fS) Operation Control De-Emphasis Function Control De-Emphasis Sample Rate Selection Audio Data Format Control Digital Filter Roll-Off Control Zero Flag Function Select Output Phase Select Zero Flag Polarity Select
0dB, Attenuation Mute Disabled 64fS Oversampling DAC1 DAC2 Enabled De-Emphasis Disabled 44.1kHz 24-Bit Left Justified Sharp Roll-Off L-/R-Channel Independent Normal Phase High
AT1[7:0], AT2[7:0] MUT[2:0] OVER DAC[2:1] DM12 DMF[1:0] FMT[2:0] AZRO DREV ZREV
TABLE User-Programmable Mode Controls.
(B8-B14) REGISTER
IDX6 IDX6 IDX6 IDX6 IDX6 IDX6 IDX6
IDX5 IDX5 IDX5 IDX5 IDX5 IDX5 IDX5
IDX4 IDX4 IDX4 IDX4 IDX4 IDX4 IDX4
IDX3 IDX3 IDX3 IDX3 IDX3 IDX3 IDX3
IDX2 IDX2 IDX2 IDX2 IDX2 IDX2 IDX2
IDX1 IDX1 IDX1 IDX1 IDX1 IDX1 IDX1
IDX0 IDX0 IDX0 IDX0 IDX0 IDX0 IDX0
AT17 AT27
AT14 AT24 DM12
AT13 AT23
AT12 AT22 FMT2 AZRO
AT11 AT21 MUT2 DAC2 FMT1 ZREV
AT10 AT20 MUT1 DAC1 FMT0 DREV
AT16 AT15 AT26 AT25 OVER DMF1 DMF0
TABLE III. Mode Control Register Map.
PCM1742
SBAS176
REGISTER DEFINITIONS
Register Register IDX6 IDX6 IDX5 IDX5 IDX4 IDX4 IDX3 IDX3 IDX2 IDX2 IDX1 IDX1 IDX0 IDX0 AT17 AT27 AT16 AT26 AT15 AT25 AT14 AT24 AT13 AT23 AT12 AT22 AT11 AT21 AT10 AT20
ATx[7:0]
Digital Attenuation Level Setting where corresponding output VOUTL VOUTR Default Value: 1111 1111B Each channel (VOUTL VOUTR) includes digital attenuator function. attenuation level from -63dB, 0.5dB steps. Changes attenuation levels made incrementing decrementing, step (0.5dB), every 8/fS time interval until programmed attenuator setting reached. Alternatively, attenuation level infinite attenuation, mute. attenuation data each channel individually. attenuation level using formula below. Attenuation Level (dB) (ATx[7:0]DEC 255) where: ATx[7:0]DEC through for: ATx[7:0]DEC through 128, attenuator infinite attenuation.
following table shows attenuator levels various settings. ATx[7:0] 1111 1111 1111 1000 1000 1000 1000 1111B 1110B 1101B 0011B 0010B 0001B 0000B 0000 0000B
Register IDX6 IDX5 IDX4 IDX3 IDX2
Decimal Value
Attenuator Level Setting 0dB, Attenuation (default) -0.5dB -1.0dB -62.0dB -62.5dB -63.0dB Mute Mute
IDX1
IDX0
OVER
MUT2 MUT1
MUTx
Soft Mute Control Where corresponding output VOUTL VOUTR Default Value: MUTx MUTx Mute Disabled (default) Mute Enabled
Mute bits, MUT1 MUT2, used enable disable Soft Mute function corresponding outputs, VOUTL VOUTR. Soft Mute function incorporated into digital attenuators. When Mute disabled (MUTx attenuator operate normally. When Mute enabled setting MUTx digital attenuator corresponding output will decreased from current setting infinite attenuation setting attenuator step (0.5dB) time. This provides "pop"-free muting output. OVER Oversampling Rate Control Default Value: OVER OVER Oversampling (default) 128x Oversampling
OVER used control oversampling rate delta-sigma DACs. OVER setting recommended when oversampling rate 192kHz (system clock 192fS).
PCM1742
SBAS176
REGISTER
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
DMF1
DMF0
DM12
DAC2 DAC1
DACx
Operation Control where corresponding output VOUTL VOUTR Default Value: DACx DACx Operation Enabled (default) Operation Disabled
operation controls used enable disable outputs, VOUTL VOUTR. When DACx corresponding output will generate audio waveform dictated data present DATA pin. When DACx corresponding output will bipolar zero level, VCC/2. DM12 Digital De-Emphasis Function Control Default Value: DM12 DM12 De-Emphasis Disabled (default) De-Emphasis Enabled
DM12 used enable disable Digital De-Emphasis function. Refer Typical Performance Curves this data sheet more information. DMF[1:0] Sampling Frequency Selection De-Emphasis Function Default Value: DMF[1:0] De-Emphasis Same Rate Selection 44.1kHz (default) 48kHz 32kHz Reserved
DMF[1:0] bits used select sampling frequency used Digital De-Emphasis function when enabled.
REGISTER
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
FMT2
FMT1
FMT0
FMT[2:0]
Audio Interface Data Format Default Value: FMT[2:0] bits used select data format serial audio interface. following table shows available format options. FMT[2:0] Audio Data Format Selection 24-Bit Standard Format, Right-Justified Data 20-Bit Standard Format, Right-Justified Data 18-Bit Standard Format, Right-Justified Data 16-Bit Standard Format, Right-Justified Data Format, 24-bits Left-Justified Format, 24-Bits (default) Reserved Reserved
PCM1742
SBAS176
Register (Cont.) Digital Filter Roll-Off Control Default Value: Sharp Roll-Off (default) Slow Roll-Off
allows user select digital filter roll-off that best suited their application. filter roll-off selections available: Sharp Slow. filter responses these selections shown Typical Performance Curves section this data sheet.
REGISTER
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AZRO
ZREV DREV
DREV
Output Phase Select Default Value: DREV DREV Normal Output (default) Inverted Output
DREV used output phase VOUTL VOUTR. ZREV Zero Flag Polarity Select Default Value: ZREV ZREV Zero Flag Pins HIGH Zero Detect (default) Zero Flag Pins Zero Detect
ZREV allows user select active polarity Zero Flag pins. AZRO Zero Flag Function Select Default Value: AZRO AZRO L-/R-Channel Independent Zero Flag (default) L-/R-Channel Common Zero Flag
AZRO allows user select function Zero Flag pins. AZRO Pin11: ZEROR; Zero Flag Output R-Channel Pin12: ZEROL; Zero Flag Output L-Channel AZRO Pin11: ZEROA; Zero Flag Output L-/R-Channel Pin12: Assign
PCM1742
SBAS176
ANALOG OUTPUTS
PCM1742 includes independent output channels: VOUTL VOUTR. These unbalanced outputs, each capable driving 3.1Vp-p typical into AC-coupled load. internal output amplifiers VOUTL VOUTR biased common-mode bipolar zero) voltage, equal VCC/2. output amplifiers include continuous-time filter that helps reduce out-of-band noise energy present outputs, noise shaping characteristics PCM1742's delta-sigma DACs. frequency response this filter shown Figure itself, this filter
ANALOG FILTER PERFORMANCE (100Hz-10MHz) Response (dB) Frequency (kHz)
enough attenuate out-of-band noise acceptable level many applications, therefore, external low-pass filter required provide sufficient out-of-band noise rejection. Further discussion post-filter circuits provided Applications Information section this data sheet. VCOM OUTPUT unbuffered common-mode voltage output pin, VCOM (pin 10), brought decoupling purposes. This nominally biased voltage level equal VCC/2. This used bias external circuits. example using VCOM external biasing applications shown Figure ZERO FLAGS Zero Detect Condition Zero Detection each output channel independent from other. data given channel remains level 1024 sample periods LRCK clock periods), Zero Detect condition exists that channel. Zero Output Flags Given that Zero Detect condition exists more channels, Zero Flag pins those channels will logic state. There Zero Flag pins each channel: ZEROL (pin ZEROR (pin 11). These pins used
FIGURE Output Filter Frequency Response.
PCM1742 VOUTx
10µF
where OPA2353
Filtered Output
VCOM 10µF
Using VCOM Bias Single-Supply Filter Stage
PCM1742
OPA337 VCOM 10µF
Buffered VCOM
Using Voltage Follower Buffer VCOM when Biasing Multiple Nodes 10µF INA134 Using INA134 DC-Coupled Output Low-Pass Filter Stage
PCM1742 VOUTx VCOM
49.9k
SENSE
FIGURE Biasing External Circuits Using VCOM Pin.
PCM1742
SBAS176
operate external mute circuits, used status indicators microcontroller, audio signal processor, other digitally controlled functions. active polarity Zero Flag output inverted setting ZREV Control Register "1". reset default active high output, ZREV L-channel R-channel common Zero Flag selected setting AZRO Control Register "1". reset default L-channel R-channel independent Zero Flag, AZRO
APPLICATIONS INFORMATION
CONNECTION DIAGRAMS basic connection diagram shown Figure with necessary power-supply bypassing decoupling components. Texas Instruments recommends using component values shown Figure designs.
OPA2134
VOUT
FIGURE Dual-Supply Filter Circuit. series resistors 100) recommended SCK, LRCK, BCK, DATA inputs. series resistor combines with stray device input capacitance form low-pass filter that reduces high-frequency noise emissions helps dampen glitches ringing present clock data lines.
POWER SUPPLIES GROUNDING PCM1742 requires analog supply (VCC) +3.3V digital supply (VDD). supply (VCC) used power analog output filter circuitry, while +3.3V (VDD) supply used power digital filter serial interface circuitry. best performance, +3.3V (VDD) supply should derived from (VCC) supply using linear regulator, shown Figure REG1117-3.3 from Texas Instruments ideal choice this application. Proper power-supply bypassing shown Figure 10µF capacitors should tantalum aluminum electrolytic. OUTPUT FILTER CIRCUITS Delta-sigma DACs utilize noise-shaping techniques improve in-band Signal-to-Noise Ratio (SNR) performance expense generating increased out-of-band noise above Nyquist Frequency, fS/2. out-of-band noise must low-pass filtered order provide optimal converter performance. This accomplished combination on-chip external low-pass filtering. Figures 9(a) show recommended external lowpass active filter circuits single- dual-supply applications. These circuits second-order Butterworth filters using Multiple FeedBack (MFB) circuit arrangement that reduces sensitivity passive component variations over frequency temperature. more information regarding active filter design, please refer Burr-Brown Applications Bulletin AB-034 (SBFA001), available from site http://www.ti.com. Since overall system performance defined quality DACs their associated analog output circuitry, high-quality audio amps recommended active filters. OPA2353 OPA2134 dual amps from Texas Instruments recommended with PCM1742, Figures 9(a)
Audio Data Input
DATA LRCK DGND VOUTL VOUTR
ZEROL/NA ZEROR/ZEROA VCOM AGND
System Clock
Mode Control
10µF
+3.3V Regulator
Zero Mute Control
10µF
10µF
Post
Post
L-Chan
R-Chan
FIGURE Basic Connection Diagram.
PCM1742
SBAS176
LAYOUT GUIDELINES
typical floor plan PCM1742 shown Figure ground plane recommended, with analog digital sections being isolated from another using split circuit board. PCM1742 should oriented with digital pins facing ground plane split/cut allow short, direct connections digital audio interface control signals originating from digital section board.
Separate power supplies recommended digital analog sections board. This prevents switching noise present digital supply from contaminating analog power supply degrading dynamic performance PCM1742. cases where common supply must used analog digital sections, inductance choke, ferrite bead) should placed between analog digital supply connections avoid coupling digital switching noise into analog circuitry. Figure shows recommended approach single-supply applications.
Digital Power DGND
Analog Power AGND +5VA
Digital Logic Audio Processor DGND PCM1742 AGND Output Circuits Digital Ground
DIGITAL SECTION
ANALOG SECTION
Analog Ground
Return Path Digital Signals
FIGURE Recommended Layout.
Power Supplies Choke Ferrite Bead AGND
Digital Logic Audio Processor
DGND PCM1742 AGND
Output Circuits
Common Ground DIGITAL SECTION ANALOG SECTION
FIGURE Single-Supply Layout.
PCM1742
SBAS176
THEORY OPERATION
delta-sigma section PCM1742 based 8-level amplitude quantizer fourth-order noise shaper. This section converts oversampled input data 8-level delta-sigma format. block diagram 8-level delta-sigma modulator shown Figure This 8-level delta-sigma modulator advantage stability clock jitter sensitivity over typical
one-bit (2-level) delta-sigma modulator. combined oversampling rate delta-sigma modulator interpolation filter 64fS. theoretical quantization noise performance 8-level delta-sigma modulator shown Figure enhanced multilevel delta-sigma architecture also advantages input clock jitter sensitivity multilevel quantizer, with simulated jitter sensitivity, shown Figure
8-Level Quantizer
64fS
FIGURE 8-Level Delta-Sigma Modulator.
QUANTIZATION NOISE SPECTRUM (64x Oversampling) QUANTIZATION NOISE SPECTRUM (128x Oversampling)
Amplitude (dB)
-100 -120 -140 -160 -180 Frequency (fS)
Amplitude (dB)
-100 -120 -140 -160 -180 Frequency (fS)
FIGURE Quantization Noise Spectrum.
PCM1742
SBAS176
JITTER DEPENDENCE (64x Oversampling) Dynamic Range (dB) Jitter (ps)
FIGURE Jitter Sensitivity.
PERFORMANCE PARAMETERS MEASUREMENT
This section provides information measure dynamic performance parameters PCM1742. cases, Audio Precision System Cascade equivalent audio measurement system utilized perform testing.
TOTAL HARMONIC DISTORTION NOISE Total Harmonic Distortion Noise (THD+N) significant figure merit audio DACs, since takes into account both harmonic distortion noise sources within specified measurement bandwidth. true value distortion noise referred THD+N. Figure shows test setup THD+N measurements. PCM1742, THD+N measured with full-scale, 1kHz digital sine wave test stimulus input DAC. digital generator 24-bit audio word length sampling frequency 44.1kHz 96kHz. digital generator output taken from unbalanced S/PDIF connector measurement system. S/PDIF data transmitted coaxial cable digital audio receiver DEM-DAI1742 demo board. receiver then configured output 24-bit data either leftjustified data format. audio interface format programmed match receiver output format. analog output then taken from post filter connected analog analyzer input measurement system. analog input band limited using filters resident analyzer. resulting THD+N measured analyzer displayed measurement system.
Evaluation Board DEM-DAI1742 S/PDIF Receiver 2nd-Order Low-Pass Filter f-3dB 54kHz 108kHz
PCM1742
S/PDIF Output
Digital Generator 0dBFS, 1kHz Sine Wave
Analyzer Display Mode
20kHz Apogee Filter
Band Limit 22Hz 30kHz
Notch Filter 1kHz
FIGURE Test Setup THD+N Measurements.
PCM1742
SBAS176
DYNAMIC RANGE Dynamic range specified A-Weighted, THD+N measured with -60dBFS, 1kHz digital sine wave stimulus input DAC. This measurement designed give good indicator will perform given low-level input signal. measurement setup dynamic range measurement shown Figure similar THD+N test setup discussed previously. differences include band limit filter selection, additional A-Weighting filter, -60dBFS input level.
IDLE CHANNEL SIGNAL-TO-NOISE RATIO test provides measure noise floor DAC. input "0"s data, DAC's Infinite Zero Detect Mute function must disabled (default condition power PCM1742). This ensures that delta-sigma modulator output connected output amplifier circuit that idle tones present) observed effect measurement. dither function digital generator must also disabled ensure "0"s data stream input DAC. measurement setup identical that used dynamic range, with exception input signal level (see notes provided Figure 18).
Evaluation Board DEM-DAI1742 S/PDIF Receiver PCM1742(1) 2nd-Order Low-Pass Filter f-3dB 54kHz
S/PDIF Output
Digital Generator Full-Scale, Dither (SNR) -60dBFS, 1kHz Sine Wave (Dynamic Range)
Analyzer Display Mode
A-Weight Filter(1)
Band Limit 22Hz 22kHz Option A-Weighting(2)
Notch Filter 1kHz
NOTES: Infinite Zero Detect Mute disabled. Results without A-Weighting will approximately worse.
FIGURE Test Setup Dynamic Range Measurements.
PCM1742
SBAS176
PACKAGE OPTION ADDENDUM
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE PCM1742E PCM1742E/2K PCM1742KE PCM1742KE/2K STATUS(1) ACTIVE ACTIVE ACTIVE ACTIVE PACKAGE TYPE SSOP SSOP SSOP SSOP PACKAGE DRAWING PINS PACKAGE 2000 2000
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video Imaging Wireless Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless

24-Bit, 192kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITA

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