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9080 Data Sheet
version 0.93 February 1997
Website/FTP Site: http://www.plxtech.com Email: apps@plxtech.com Phone: 408-774-9060 FAX: 408-774-1269
Technology, Inc., Potrero Ave., Sunnyvale, 94086, Phone: 408-774-9060, Fax: 408-774-2169, Web: www.plxtech.com. retains right make changes these specifications time, without notice. Products have minor variations this specification known errata. assumes liability whatsoever, including infringement patent copyright, sale products. Technology, Inc., 1997.
TABLE CONTENTS
TABLE CONTENTS
GENERAL DESCRIPTION APPLICATIONS 9080. 1.1.1 Adapter Cards 1.1.2 Embedded Systems MAJOR FEATURES COMPATIBILITY 9080 WITH 9060, 9060ES, 9060SD 1.3.1 Compatibility. 1.3.2 Register Compatibility. COMPARISON 9060, 9060ES, 9060SD, 9080 OPERATION CYCLES 2.1.1 Target Command Codes. 2.1.2 Master Command Codes
2.1.2.1 Master Command Codes. 2.1.2.2 Direct Local Command Codes.
LOCAL CYCLES 2.2.1 Local Direct Master. 2.2.2 Local Direct Slave.
2.2.2.1 Ready/Wait State Control 2.2.2.2 Burst Mode Continuous Burst Mode (BTERM "Burst Terminate" Mode). 2.2.2.2.1 Burst Mode 2.2.2.2.2 Continuous Burst Mode (BTERM# "Burst Terminate" Mode) 2.2.2.2.3 Partial Lword Accesses 2.2.2.3 Recovery States. 2.2.2.4 Local Read Accesses. 2.2.2.5 Local Write Accesses. 2.2.2.6 Direct Slave Write Accesses-8- 16-Bit Buses 2.2.2.7 Local Data Parity 2.2.2.8 Local Little/Big Endian 2.2.2.8.1 Local Bus-Big Endian Mode 2.2.2.8.2 Local Bus-Big Endian Mode 2.2.2.8.3 Local Bus-Big Endian Mode
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FUNCTIONAL DESCRIPTION. RESET 3.1.1 Input RST# 3.1.2 Local Input LRESETi# 3.1.3 Local Output LRESETo# 3.1.4 Software Reset. 9080 INITIALIZATION. 3.2.1 EEPROM Initialization. 3.2.2 Local Initialization EEPROM. 3.3.1 Short EEPROM Load 3.3.2 Long EEPROM Load 3.3.3 Extra Long EEPROM Load. 3.3.4 Recommended EEPROMs INTERNAL REGISTER ACCESS 3.4.1 Access Internal Registers 3.4.2 Local Access Internal Registers DIRECT DATA TRANSFER MODES 3.5.1 Direct Master Operation (Local Master Target).
3.5.1.1 Decode 3.5.1.2 FIFOs 3.5.1.3 Memory Access 3.5.1.4 IO/CFG Access. 3.5.1.5 3.5.1.6 (PCI Configuration Type Type Cycles) 3.5.1.7 Direct Master Lock 3.5.1.8 Master/Target Abort 3.5.1.9 Write Invalidate.
3.5.2 Direct Slave Operation (PCI Master Local Access)
3.5.2.1 Local Address Mapping 3.5.2.1.1 Byte Enables. 3.5.2.1.2 Local Initialization Software 3.5.2.1.3 Initialization Software 3.5.2.2 Deadlock BREQo 3.5.2.2.1 Backoff 3.5.2.2.2 Software/Hardware Solution Systems without Backoff Capability. 3.5.2.2.3 Software Solutions Deadlock
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3.5.2.3 Direct Slave Lock.
3.5.3 Direct Slave Priority OPERATION. 3.6.1 Non-Chaining Mode 3.6.2 Chaining Mode DMA. 3.6.3 Data Transfers.
3.6.3.1 Local Transfer 3.6.3.2 Local Transfer 3.6.3.3 Unaligned Transfers.
3.6.4 Demand Mode 3.6.5 Priority 3.6.6 Arbitration
3.6.6.1 Transfer (EOT0# EOT1#) Input. 3.6.6.2 Local Latency Pause Timers
BREQ INPUT. DOORBELL REGISTERS. MAILBOX REGISTERS 3.10 INTERRUPTS. 3.10.1 Interrupts (INTA#)
3.10.1.1 Local Interrupt Input. 3.10.1.2 Master/Target Abort Interrupt
3.10.2 Local Interrupts (LINTo#)
3.10.2.1 Local Doorbell Interrupt 3.10.2.2 Local Doorbell Interrupt 3.10.2.3 Built Self Test Interrupt (BIST). 3.10.2.4 Channel Interrupts
3.10.3 SERR# (PCI NMI). 3.10.4 Local LSERR# (Local NMI) 3.11 COMPATIBLE MESSAGE UNIT. 3.11.1 Inbound Messages 3.11.2 Outbound Messages. 3.11.3 Pointer Management 3.11.4 Inbound Free List FIFO. 3.11.5 Inbound Post List FIFO. 3.11.6 Outbound Post List FIFO 3.11.7 Outbound Free List FIFO.
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REGISTERS REGISTER DEFINITIONS SUMMARY. 4.1.1 Register Differences between 9080 9060, 9060ES, 9060SD REGISTER ADDRESS MAPPING 4.2.1 Configuration Registers. 4.2.2 Local Configuration Registers 4.2.3 Runtime Registers 4.2.4 Registers 4.2.5 Messaging Queue Registers. CONFIGURATION REGISTERS 4.3.1 (PCIIDR; PCI:00h, LOC:00h) Configuration Register
4.3.1.1 (PCICR; PCI:04h, LOC:04h) Command Register.
4.3.2 (PCISR; PCI:06h, LOC:06h) Status Register. 4.3.3 (PCIREV; PCI:08h, LOC:08h) Revision Register. 4.3.4 (PCICCR; PCI:09-0Bh, LOC:09-0Bh) Class Code Register 4.3.5 (PCICLSR; PCI:0Ch, LOC:0Ch) Cache Line Size Register. 4.3.6 (PCILTR; PCI:0Dh, LOC:0Dh) Latency Timer Register. 4.3.7 (PCIHTR; PCI:0Eh, LOC:0Eh) Header Type Register 4.3.8 (PCIBISTR; PCI:0Fh, LOC:0Fh) Built-In Self Test (BIST) Register 4.3.9 (PCIBAR0; PCI:10h, LOC:10h) Base Address Register Memory Accesses Local, Runtime, Registers 4.3.10 (PCIBAR1; PCI:14h, LOC:14h) Base Address Register Accesses Local, Runtime, Registers 4.3.11 (PCIBAR2; PCI:18h, LOC:18h) Base Address Register Memory Accesses Local Address Space 4.3.12 (PCIBAR3; PCI:1Ch, LOC:1Ch) Base Address Register Memory Accesses Local Address Space 4.3.13 (PCIBAR4; PCI:20h, LOC:20h) Base Address Register. 4.3.14 (PCIBAR5; PCI:24h, LOC:24h) Base Address Register. 4.3.15 (PCICIS; PCI:28h, LOC:28h) Cardbus Pointer. 4.3.16 (PCISVID; PCI:2Ch, LOC:2Ch) Subsystem Vendor 4.3.17 (PCISID; PCI:2Eh, LOC:2Eh) Subsystem 4.3.18 (PCIERBAR; PCI:30h, LOC:30h) Expansion Base Register 4.3.19 (PCIILR; PCI:3Ch, LOC:3Ch) Interrupt Line Register. 4.3.20 (PCIIPR; PCI:3Dh, LOC:3Dh) Interrupt Register. 4.3.21 (PCIMGR; PCI:3Eh, LOC:3Eh) Min_Gnt Register 4.3.22 (PCIMLR; PCI:3Fh, LOC:3Fh) Max_Lat Register
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LOCAL CONFIGURATION REGISTERS. 4.4.1 (LAS0RR; PCI:00h, LOC:80h) Local Address Space Range Register Local 4.4.2 (LAS0BA; PCI:04h, LOC:84h) Local Address Space Local Base Address (Remap) Register. 4.4.3 (LARBR; PCI:08h ACh, LOC:88h 12Ch) Local/DMA Arbitration Register 4.4.4 (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Register 4.4.5 (EROMRR; PCI:10h, LOC:90h) Expansion Range Register. 4.4.6 (EROMBA; PCI:14h, LOC:94h) Expansion Local Base Address (Remap) Register BREQo Control 4.4.7 (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion Region Descriptor Register. 4.4.8 (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register Direct Master 4.4.9 (DMLBAM; PCI:20h, LOC:A0h) Local Base Address Register Direct Master Memory. 4.4.10 (DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register Direct Master IO/CFG 4.4.11 (DMPBAM; PCI:28h, LOC:A8h) Base Address (Remap) Register Direct Master Memory 4.4.12 (DMCFGA; PCI:2Ch, LOC:ACh) Configuration Address Register Direct Master IO/CFG. 4.4.13 (LAS1RR; PCI:F0h, LOC:170h) Local Address Space Range Register Local 4.4.14 (LAS1BA; PCI:F4h, LOC:174h) Local Address Space Local Base Address (Remap) Register 4.4.15 (LBRD1; PCI:F8h, LOC:178h) Local Address Space Region Descriptor Register RUNTIME REGISTERS. 4.5.1 (MBOX0; PCI:40h 78h, LOC:C0h) Mailbox Register 4.5.2 (MBOX1; PCI:44h 7Ch, LOC:C4h) Mailbox Register 4.5.3 (MBOX2; PCI:48h, LOC:C8h) Mailbox Register 4.5.4 (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register 4.5.5 (MBOX4; PCI:50h, LOC:D0h) Mailbox Register 4.5.6 (MBOX5; PCI:54h, LOC:D4h) Mailbox Register 4.5.7 (MBOX6; PCI:58h, LOC:D8h) Mailbox Register 4.5.8 (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register 4.5.9 (P2LDBELL; PCI:60h, LOC:E0h) Local Doorbell Register. 4.5.10 (L2PDBELL; PCI:64h, LOC:E4h) Local Doorbell Register. 4.5.11 (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status. 4.5.12 (CNTRL; PCI:6Ch, LOC:ECh) EEPROM Control, Command Codes, User Control, Init Control Register. 4.5.13 (PCIHIDR; PCI:70h, LOC:F0h) Permanent Configuration Register. 4.5.14 (PCIHREV; PCI:74h, LOC:F4h) Permanent Revision Register. REGISTERS 4.6.1 (DMAMODE0; PCI:80h, LOC:100h) Channel Mode Register. 4.6.2 (DMAPADR0; PCI:84h, LOC:104h) Channel Address Register. 4.6.3 (DMALADR0; PCI:88h, LOC:108h) Channel Local Address Register.
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4.6.4 (DMASIZ0; PCI:8Ch, LOC:10Ch) Channel Transfer Size (Bytes) Register. 4.6.5 (DMADPR0; PCI:90h, LOC:110h) Channel Descriptor Pointer Register. 4.6.6 (DMAMODE1; PCI:94h, LOC:114h) Channel Mode Register. 4.6.7 (DMAPADR1; PCI:98h, LOC:118h) Channel Address Register. 4.6.8 (DMALADR1; PCI:9Ch, LOC:11Ch) Channel Local Address Register 4.6.9 (DMASIZ1; PCI:A0h, LOC:120h) Channel Transfer Size (Bytes) Register 4.6.10 (DMADPR1; PCI:A4h, LOC:124h) Channel Descriptor Pointer Register 4.6.11 (DMACSR0; PCI:A8h, LOC:128h) Channel Command/Status Register 4.6.12 (DMACSR1; PCI:A9h, LOC:129h) Channel Command/Status Register 4.6.13 (DMAARB; PCI:ACh, LOC:12Ch) Arbitration Register 4.6.14 (DMATHR; PCI:B0h, LOC:130h) Threshold Register. MESSAGING QUEUE REGISTERS 4.7.1 (OPLFIS; PCI:30h, LOC:B0) Outbound Post List FIFO Interrupt Status Register 4.7.2 (OPLFIM; PCI:34h, LOC:B4) Outbound Post List FIFO Interrupt Mask Register 4.7.3 (IQP; PCI:40h) Inbound Queue Port 4.7.4 (OQP; PCI:44h) Outbound Queue Port. 4.7.5 (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration Register 4.7.6 (QBAR; PCI:C4h, LOC:144h) Queue Base Address Register 4.7.7 (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer Register 4.7.8 (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer Register 4.7.9 (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer Register 4.7.10 (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer Register 4.7.11 (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer Register. 4.7.12 (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer Register 4.7.13 (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer Register. 4.7.14 (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer Register. 4.7.15 (QSR; PCI:E8h, LOC:168h) Queue Status/Control Register. DESCRIPTION. SUMMARY PINOUT COMMON MODES MODE PINOUT. MODE PINOUT MODE PINOUT. ELECTRICAL SPECIFICATIONS.
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PACKAGE MECHANICAL DIMENSIONS. PACKAGE MECHANICAL DIMENSIONS TYPICAL MASTER ADAPTER .100 9080 MODE, MODE, MODE) .101 TIMING DIAGRAMS .102 LIST TIMING DIAGRAMS.102
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9080
ACCELERATOR
FEBRUARY 1997 VERSION 0.93 PRELIMINARY
COMPATIBLE MASTER INTERFACE CHIP ADAPTERS EMBEDDED SYSTEMS
FEATURES
Version compliant Master Interface chip adapters embedded systems Compatible Messaging Unit Volt signaling, volt core, low-power CMOS 208-pin PQFP independent channels local memory to/from host data transfers Eight programmable FIFOs zero wait state burst operation Local data transfers MB/sec Programmable local supports nonmultiplexed 32-bit address/data, multiplexed bit, slave accesses local devices Local runs asynchronously Eight mailbox doorbell registers Performs Endian/Little Endian conversion Upward compatibility with 9060/9060ES/9060SD (See compatibility notes)
GENERAL DESCRIPTION
9080 provides compact, high performance master interface adapter boards embedded systems. programmable local chip configured directly connect wide variety processors, controllers memory subsystems. 9080 contains Intelligent (I2O) messaging unit that allows high performance compatible software implementations protocol specification. Users 9060, 9060ES 9060SD chips upgrade their products support I2O, Volts other features with little change existing hardware software. 9080 provides independent chaining channels with bidirectional FIFOs supporting zero wait state burst transfers between host local memory. Slave transfers performed through third FIFO. fourth FIFO allows local processor other controllers perform direct master transfers bus. 9080 also allows local processor configure other devices system.
Boot
Local Memory
Device (LAN, Disk, Video, etc.)
Local
9080
Registers Serial EEPROM
Local Run-Time
Local Interface
FIFOs Control:
Unaligned Transfer
Interface
Figure 1-1. Typical Adapter Block Diagram
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9080
GENERAL DESCRIPTION
Internal Registers
Config. Local Config. Run-Time Messaging
EEPROM Initialization
State Machines
Initiator (for Direct Master Xfers)
FIFOs
Dir. Master Write Dir. Master Read Dir. Slave Write Dir. Slave Read DMA1 PCI/Loc DMA1 Loc/PCI DMA0 PCI/Loc DMA0 Loc/PCI
Local State Machines
Local Slave (for Direct Master Xfers) Local Master (for Direct Slave Xfers) Local Master (For Xfers) Local Master (For Xfers)
Local Interface: Select Width 8,16, Endian Conversion Select Muxed non-Muxed Addr/Data
Interface Arbiter
Target (for Direct Slave Xfers) Initiator (For Xfers) Initiator (For Xfers)
Control Logic
Messaging
Chaining
Unaligned Xfer
Figure 1-2. 9080 Internal Block Diagram
APPLICATIONS 9080
1.1.1 Adapter Cards
Major adapter card applications 9080 include high performance communications, networking, disk control, multimedia video adapters. 9080 moves data between host adapter local several ways. First, local host processor program controller 9080 move data between adapter memory host bus. Second, 9080 perform "Direct Master Transfers," whereby local controller accesses directly through master transfer. 9080 also supports slave transfers which another device master. Finally, 9080 contains complete messaging unit
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with mailbox registers, doorbell registers queue management pointers that used message passing under protocol custom protocol.
1.1.2 Embedded Systems
Another application 9080 embedded systems, such network hubs routers, printer engines industrial equipment. this configuration, four above-mentioned data transfer modes used. addition, 9080 supports Type Type configuration cycles, which allows embedded embedded system host configure other devices system.
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9080
GENERAL DESCRIPTION
MAJOR FEATURES
Compliant. 9080 compliant with aspects specification version 2.1. Messaging Unit. 9080 incorporates messaging unit. This enables adapter embedded system communicate with other I2O-supported devices. messaging unit fully compatible with extension Version specification. Dual Independent Programmable Controllers with Bidirectional FIFOs. 9080 provides independently programmable controllers with bidirectional FIFOs each channel. Each channel supports both nonchaining chaining modes demand mode DMA, Transfer (EOT) mode. Direct Master. 9080 supports both memory mapped burst transfer accesses mapped single transfer accesses from Local Master. 9080 also supports interlock ("LOCK#") cycles. Bidirectional FIFOs both Read- Write-enable high-performance bursting local buses. Host Capability. direct master mode, 9080 generate Type Type configuration cycles. Direct Slave. 9080 supports both memory mapped mapped burst accesses from Local Master. Bidirectional FIFOs both Read- Write-enable high-performance bursting local buses. Programmable Local Modes. 9080 master interface chip that connects three local types, selected through mode pins. 9080 connected local with similar design with little glue logic. Table lists three modes. Table 1-1. Programmable Local Modes
Mode Description 32-bit address/32-bit data, nonmultiplexed 32-bit address/32-bit data, multiplexed 32-bit address/16-bit data, multiplexed
Interrupt Generator. 9080 generate local interrupts from several sources. Clock. 9080 local interface runs from local clock generates necessary internal clocks. This clock runs asynchronously clock. There buffered clock (BPCLKo) local side use. BPCLKo connected LCLK. Volt Volt Operation. 9080 provides either Volt Volt signaling bus. signaling environment requires VCC. local environment requires VCC. Serial EEPROM Interface. 9080 contains optional serial EEPROM interface that used load configuration information. This useful loading information that unique particular adapter (such Network Vendor ID). Mailbox Registers. 9080 contains eight mailbox registers that accessed from either local bus. Doorbell Registers. 9080 includes doorbell registers. generates interrupts from local bus. other generates interrupts from local bus. Unaligned Transfer Support. 9080 transfer data byte boundary. Big/Little Endian Conversion. 9080 supports dynamic switching between Endian Little Endian operations Direct Slave, Direct Master, DMA, internal register accesses local side. Note: always Little Endian.
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9080
GENERAL DESCRIPTION
COMPATIBILITY 9080 WITH 9060, 9060ES, 9060SD
9080 upward compatible with 9060, 9060ES 9060SD, except noted Table Section 4.1, "New Register Definitions Summary." contains features 9060, well messaging unit, Endian conversion state machine deeper FIFOs.
Table 1-2. Compatibility
9060/ES/SD Name CLKSEL EE1MC Description EEPROM Clock Select Optional EEPROM clock source 9080 Name PCIVOLT EESEL Description 1=5.0 0=3.3 EEPROM Select 1=93CS46 bit) 0=93CS56 bit)
1.3.1 Compatibility
When upgrading from 9060, 9060ES 9060SD, observe following definitions listed Table 1-2.
1.3.2 Register Compatibility
registers implemented 9060/ES/SD implemented 9080. There limited number definitions several registers. Section 4.1, "New Register Definitions Summary."
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9080
GENERAL DESCRIPTION
COMPARISON 9060, 9060ES, 9060SD, 9080
Table 1-3. Comparison 9060, 9060ES, 9060SD, 9080
Feature Number Channel(s) Local Address Spaces Direct Master Mode Mailbox Registers Doorbell Registers FIFOs FIFO Depth-Direct Slave Write, Direct Master Write, Read Write FIFO Depth -Direct Slave Read, Direct Master Read, Read Write LLOCKo# Lock Cycles WAITI# Wait State Generation BPCLKO Pin; Buffered Clock DREQ DACK Pins Demand Mode Support Register Addresses 9060 Eight Lwords bytes) Lwords bytes) 9060ES Four Lwords bytes) Lwords bytes) Identical except 9060ES registers Tables were added Signals deleted: DREQ0 (PIN DACK0 (PIN Input signals added: WAITI (PIN BIGEND# (PIN Output signals added: BPCLK (PIN 168) LLOCKo (PIN 9060SD Four Lwords bytes) Lwords bytes) (Channel only) Identical, except 9060SD register Tables were added Signals deleted: BREQ0 (PIN DMPAF# (PIN DREQ0 (PIN DACK0 (PIN BTERMo# (PIN Input signals added: WAITI (PIN BIGEND# (PIN (PIN MODE, modes) Output signals added: BPCLK (PIN 168) LLOCKo (PIN Big/Little Endian Conversion Spec. Deferred Reads Programmable Prefetch Counter Write Invalidate Cycle Additional Device Vendor Register Messaging Unit Signaling 9080 Eight Lwords (128 bytes) Lwords bytes) Identical except 9080 additional related registers 30H, 34H, were remapped Signals changed: PCIVOLT (PIN 170) EESEL (PIN 175)
Pinout
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9080
OPERATION
OPERATION
CYCLES
9080 compliant with Specification v2.1. Refer spec specific features Bus.
2.1.2.1 Master Command Codes
controllers 9080 generate memory cycles listed Table 2-2. Table 2-2. Master Command Codes
Command Type Memory Read Code (C/BE[3:0]#) 0110 (6h) 0111 (7h) 1100 (Ch) 1110 (Eh) 1111 (Fh)
2.1.1 Target Command Codes
target, 9080 allows access 9080 internal registers local bus, using commands listed Table 2-1. Table 2-1. Target Command Codes
Command Type Read Write Memory Read Memory Write Memory Read Multiple Memory Read Line Memory Write Invalidate Configuration Read Configuration Write Code (C/BE[3:0]#) 0010 (2h) 0011 (3h) 0110 (6h) 0111 (7h) 1100 (Ch) 1110 (Eh) 1111 (Fh) 1010 (Ah) 1011 (Bh)
Memory Write Memory Read Multiple Memory Read Line Memory Write Invalidate
2.1.2.2 Direct Codes
Local
Command
direct local accesses, 9080 generate cycles listed Table through Table Table 2-3. Local Memory Access
Command Type Memory Read Memory Write Memory Read Multiple Memory Read Line Code (C/BE[3:0]#) 0110 (6h) 0111 (7h) 1100 (Ch) 1110 (Eh)
read write accesses 9080 byte, word long word accesses. memory commands aliased basic memory commands. accesses 9080 decoded long word boundary. byte enables used determine which bytes read written. access with illegal byte enable combinations terminated with Target Abort.
Table 2-4. Local Access
Command Type Read Write Code (C/BE[3:0]#) 0010 (2h) 0011 (3h)
Table 2-5. Local Configuration Access
Command Type Code (C/BE[3:0]#) 1010 (Ah) 1011 (Bh)
2.1.2 Master Command Codes
9080 access perform transfers Direct Master Local transfers. During Direct master transfer, command code assigned 9080 internal register location (PCI [6Ch])(Loc [ECh]) bits [15:0] will used command code.
Configuration Memory Read Configuration Memory Write
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9080
OPERATION
LOCAL CYCLES
9080 connects host several local processor types: 32-bit nonmultiplexed mode) 32-bit multiplexed mode) 16-bit multiplexed mode)
2.2.2.2 Burst Mode Continuous Burst Mode (BTERM "Burst Terminate" Mode)
Note: BTERM refers 9080 internal register bit. BTERM# refers 9080 external signal.
2.2.2.2.1 Burst Mode
Bursting enabled BTERM input enabled, bursting start boundary continue address boundary described Table 2-6. After data boundary transferred, 9080 generates address cycle (ADS#). Table 2-6. Burst Mode
Mode Burst 32-bit bus-4 Lwords quad Lword boundary (LA3, 16-bit bus-4 words quad word boundary (LA2, 8-bit bus-4 bytes quad byte boundary (LA1, 16-bit bus-8 words quad Lword boundary (LA3,
9080 operates three modes, selected through mode pins, corresponding three types-
2.2.1 Local Direct Master
Local cycles continuous single burst cycles (programmable 9080 internal registers). local target, 9080 allows access 9080 internal registers bus. modes, local direct master accesses 9080 must non-pipelined bus. mode, local direct master accesses 9080 must non-pipelined bus.
2.2.2 Local Direct Slave
Master read/write local (PCI 9080 target local master).
2.2.2.2.2 Continuous Burst Mode (BTERM# "Burst Terminate" Mode)
BTERM mode enables 9080 perform long bursts devices that accept longer than Lword bursts. 9080 generates address cycle then continues burst data. device requires address cycle after certain address boundary, assert BTERM# input cause 9080 generate address cycle. BTERM# input acknowledges current data transfer requests that address cycle generated (ADS#). address will next data transfer. BTERM mode enabled, 9080 asserts BLAST# only FIFOs become FULL/EMPTY transfer complete. Note: BTERM# input signal asserted, BLAST# will asserted until conditions described above met.
2.2.2.1 Ready/Wait State Control
READY input disabled, external READY input effect wait states local access. Wait states between data cycles generated internally wait state counter. wait state counter initialized with configuration register value start each data access. READY input enabled, READY input effect until wait state counter READY input then controls number additional wait states. BTERM input sampled until wait state counter
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2.2.2.2.3 Partial Lword Accesses
9080
OPERATION
2.2.2.7 Local Data Parity
Lword accesses which byte enables asserted broken into single address data cycles, listed Table 2-7. Table 2-7. Partial Lword Accesses
Register Value (PCI 18h)(LOC 98h) Burst Enable BTERM Enable Result (Number Transfers) Single Cycle (Default) Single Cycle Burst Lwords time Continuous Burst Mode
There data parity each byte lane 9080 data (DP[3:0]). Even data parity generated each lane during local reads from 9080 during 9080 master writes local bus. Even data parity checked during local writes 9080 during 9080 reads from local bus. Parity checked each byte lane with asserted byte enable. PCHK# asserted clock cycle following data being checked parity error detected. Generation local data parity optional. signals data parity pins effect operation 9080. parity checking generation independent local parity checking generation.
2.2.2.3 Recovery States
modes, 9080 inserts recovery state between last data transfer next address cycle. 9080 does support 80960J feature using READY input recovery states. additional recovery states added READY input remains asserted during last data cycle.
2.2.2.8 Local Little/Big Endian
Little Endian (that data long word aligned lowermost byte lane). Byte (address appears AD[7:0], Byte appears AD[15:8], Byte appears AD[23:16] Byte appears AD[31:24]. 9080 local programmed operate Little Endian mode. Endian mode, 9080 transposes data byte lanes. Data transferred shown Table through Table 2-11.
2.2.2.4 Local Read Accesses
local read accesses, 9080 reads only bytes corresponding byte enables requested initiator.
2.2.2.8.1 Local Bus-Big Endian Mode
2.2.2.5 Local Write Accesses
local writes, only bytes specified master controller 9080 written. Access 16-bit results Lword being broken into multiple local transfers. each transfer, byte enables encoded 80960C provide local address bits [LA1:LA0].
Data long word aligned uppermost byte lane. Byte appears Local Data [31:24], Byte appears Local Data [23:16], Byte appears Local Data [15:8] Byte appears Local Data [7:0].
2.2.2.8.2 Local Bus-Big Endian Mode
local bus, 9080 programmed upper lower word lane. Byte lanes burst order listed Table Table 2-9.
2.2.2.6 Direct Slave 16-Bit Buses
Write
Accesses-
Direct access 16-bit results Lword being broken into multiple local transfers. each transfer, byte enables encoded 80960C provide local address bits [LA1:LA0].
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Table 2-8. Upper Word Lane Transfer
Burst Order First Transfer Byte Lane Byte appears Local Data [31:24] Byte appears Local Data [23:16] Second Transfer Byte appears Local Data [31:24] Byte appears Local Data [23:16]
9080
OPERATION
each following transfer types, 9080 local independently programmed operate Little Endian Endian mode: Local accesses 9080 configuration registers Direct Slave accesses Local Address Space Direct Slave accesses Local Address Space Direct Slave accesses expansion Channel accesses local Channel accesses local
Table 2-9. Lower Word Lane Transfer
Burst Order First Transfer Byte Lane Byte appears Local Data [15:8] Byte appears Local Data [7:0] Second Transfer Byte appears Local Data [15:8] Byte appears Local Data [7:0]
2.2.2.8.3 Local Bus-Big Endian Mode
local bus, 9080 programmed upper lower byte lane. Byte lanes burst order listed Table 2-10 Table 2-11. Table 2-10. Upper Byte Lane Transfer
Burst Order First transfer Second transfer Third transfer Fourth transfer Byte Lane Byte appears Local Data [31:24] Byte appears Local Data [31:24] Byte appears Local Data [31:24] Byte appears Local Data [31:24]
local configuration accesses, input used dynamically change Endian mode. Note: always Little Endian mode.
Table 2-11. Lower Byte Lane Transfer
Burst Order First Transfer Second Transfer Third Transfer Fourth Transfer Byte Lane Byte appears Local Data [7:0] Byte appears Local Data [7:0] Byte appears Local Data [7:0] Byte appears Local Data [7:0]
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9080
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
RESET
3.1.1 Input RST#
RST# input causes outputs float, resets entire 9080 causes local reset output, LRESETo#, asserted.
serial EEPROM initialization, 9080 response local processor hold READYo#.
3.2.2 Local Initialization
9080 issues RETRY accesses until "Local Init Done bit" Init Control Register set. "Init Done bit" programmable through local configuration accesses. this going local processor, then input should tied low. Holding input externally forces Local Init Done 9080 default values used serial EEPROM present local "Init Status" holding input local processor.
3.1.2 Local Input LRESETi#
When asserted, LRESETi# input resets local portion 9080, clears local configuration registers causes LRESETo# output asserted.
EEPROM
After reset, 9080 attempts read serial EEPROM determine presence. active start indicates serial EEPROM present (PCI 9080 supports 93CS46 (1K) 93CS56 (2K), selectable EESEL pin). (Refer manufacturer's data sheet particular serial EEPROM being used.) first word then checked verify serial EEPROM programmed. first word bit) blank serial EEPROM 9080 will default values instead. serial EEPROM read programmed from local bus. Bits [27:24] serial EEPROM Control Register controls 9080 pins that enable reading writing serial EEPROM data bits. (Refer manufacturer's data sheet particular serial EEPROM being used.) 9080 three serial EEPROM load options: Short Load Mode-The SHORT# input pulled down 9080 loads Lwords from serial EEPROM Long Load Mode-The SHORT# input pulled "Local Region Descriptor Register [LOC 98h]" 9080 loads Lwords from serial EEPROM Extra Long Load Mode-The SHORT# input pulled "Local Region Descriptor Register [LOC 98h]" during Long Load from serial EEPROM 9080 loads Lwords from serial EEPROM
3.1.3 Local Output LRESETo#
LRESETo# asserted when RST# input asserted, LRESETi# input asserted, software reset Init Control Register
3.1.4 Software Reset
host software reset Init Control Register reset 9080 assert LRESETo# output. configuration registers will reset. When software reset set, 9080 responds accesses, local accesses. 9080 remains this reset condition until host clears bit. Note: local side cannot clear this reset because local reset state.
9080 INITIALIZATION
9080 configuration registers programmed optional serial EEPROM and/or local processor. Note: internal configuration register also accessed host processor after power initialization.
3.2.1 EEPROM Initialization
During serial EEPROM initialization, 9080 response target accesses RETRY. During
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SECTION 3.3.1 Short EEPROM Load
9080
FUNCTIONAL DESCRIPTION
registers listed Table loaded from serial EEPROM after reset de-asserted SHORT# low. serial EEPROM organized words bit). 9080 first loads (Most Significant Word (bits [31:16])), starting from most significant (bit 31). 9080 then loads (Least Significant Word (bits [15:0])), starting again from most significant (bit 15). Therefore, 9080 will load Device Vendor class code, forth. five 32-bit words stored sequentially serial EEPROM. Table 3-1. Short EEPROM Load Registers
EEPROM Offset EEPROM Value 9080 10B5 0680 0002 0000 0100 xxxx xxxx xxxx xxxx Description Device Vendor Class Code Class Code, Revision Maximum Latency, Minimum Grant Interrupt Pin, Interrupt Line Routing Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined)
3.3.2 Long EEPROM Load
registers listed Table loaded from serial EEPROM after reset de-asserted SHORT# high. serial EEPROM organized words bit). 9080 first loads (Most Significant Word (bits [31:16])), starting from most significant (bit 31). 9080 then loads (Least Significant Word (bits [15:0])), starting again from most significant (bit 15). Therefore, 9080 will load Device Vendor class code, forth. serial EEPROM value entered into DATA programmer order shown below. value shown examples must modified each particular application. 16-bit words listed table stored sequentially serial EEPROM. Note: internal register values serial EEPROM values read written using PLXMON.EXE PLXMON95.EXE, provided Technology.
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Table 3-2. Long EEPROM Load Registers
EEPROM Offset EEPROM Value 9080 10B5 0680 0001 0000 0100 xxxx xxxx xxxx xxxx FFF0 0000 1000 0001 11E4 0000 0000 0000 FFF0 0000 1000 0010 4DC3 04C3 FF00 0000 4000 0000 7000 0000 0000 183F 0000 0000 Description Device Vendor Class Code
9080
FUNCTIONAL DESCRIPTION
Class Code, Revision Maximum Latency, Minimum Grant Interrupt Pin, Interrupt Line Routing Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined) Range Local Address Space Range Local Address Space Local Base Address (Remap) Local Address Space Local Base Address (Remap) Local Address Space Local Arbitration Register Local Arbitration Register Local Big/Little Endian Descriptor Register Local Big/Little Endian Descriptor Register Range Local Expansion Range Local Expansion Local Base Address (Remap) Local Expansion Local Base Address (Remap) Local Expansion Region Descriptors Local Accesses Region Descriptors Local Accesses range Direct Master range Direct Master Local Base Address Direct Master Memory Local Base Address Direct Master Memory Local Address Direct Master IO/CFG Local Address Direct Master IO/CFG Base Address (Remap) Direct Master Base Address (Remap) Direct Master Configuration Address Register Direct Master IO/CFG Configuration Address Register Direct Master IO/CFG
Note: There unused bytes EEPROM that used user-defined applications.
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SECTION 3.3.3 Extra Long EEPROM Load
9080
FUNCTIONAL DESCRIPTION
Extra Long Load mode provided 9080 load more Lwords from EEPROM. "Local Region Descriptor [LOC 98h]", following Lword registers loaded addition normal Long Load process (refer Section 3.3.2). "Local Region Descriptor [LOC 98h]" must during Long Load Process. (Refer Table 3-3.) Table 3-3. Extra Long EEPROM Load Registers
EEPROM Offset EEPROM Value 9080 10B5 FFf0 0000 1000 0001 0000 05C3 0000 0000 Description Subsystem Subsystem Vendor Range Local Address Space Range Local Address Space Local Base Address (Remap) Local Address Space Local Base Address (Remap) Local Address Space Region Descriptors (Space Local Accesses Region Descriptors (Space Local Accesses
INTERNAL REGISTER ACCESS
9080 chip provides several internal registers, allowing maximum flexibility interface design performance. register types accessible from both local buses, including following: Configuration Registers Local Configuration Registers Mailbox Registers Doorbell Registers Registers Messaging Queue Registers (I2O)
Figure illustrates these registers accessed.
Master Local Master
9080
Configuration Registers Local Configuration Registers
Interrupt
Base Address local expansion Base Address local expansion
Registers Mailbox Registers
Clear
Local Doorbell Register Local Doorbell Register Messaging Queue Registers
Clear
Note: There unused bytes EEPROM that used user-defined applications.
3.3.4 Recommended EEPROMs
(National NM93CS46 compatible) (National NM93CS56 compatible) device used. Refer Table Section "Pin Description," EEPROM control descriptions. Figure 3-1. 9080 Internal Register Access
3.4.1 Access Internal Registers
9080 "PCI configuration registers" accessed from with configuration Type cycle. 9080 internal registers accessed memory cycle, with address that matches base address specified Base Address Memory Mapped Configuration Register 9080. They also accessed cycle, with
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Local Interrupt
SECTION
9080
FUNCTIONAL DESCRIPTION
Address Decode Mode
address matching base address specified Base Address Mapped Configuration Register 9080. read write accesses 9080 registers byte, word long word accesses. memory accesses 9080 registers burst non-burst. 9080 responds with Disconnect burst accesses 9080 registers.
9080
compare
LA31 LA30 LA29
9080
(9080 Chip Select)
3.4.2 Local Access Internal Registers
local processor access internal registers 9080 through either internal external address decode logic. 9080 provides Address Decode Mode (ADMODE) that selects whether internal address decode logic used whether designer will supply external chip select from external address decoder. Figure illustrates dual address decode logic works. Address Decode Mode internal 9080 address decode logic enabled. this mode, 9080 internal registers selected when local address bits LA[31:29] match input address select pins S[2:0]. Address Decode Mode 9080 responds local access when asserted through external chip select logic. Note that must decoded while ADS# low. local read write accesses 9080 registers byte, word long word accesses. local accesses 9080 registers burst nonburst. modes, accesses must nonpipelined bus. 9080 READYo# indicates data transfer complete. mode, accesses must nonpipelined bus. 9080 READYo# indicates data transfer complete.
9080 Internal Register Chip Select
9080 Internal Register Chip Select
Figure 3-2. Dual Address Decode Mode
DIRECT DATA TRANSFER MODES
Figure Figure illustrate direct data transfer modes.
Host
System Chipset
Physical System Memory
Address Translation DMA, Memory, Cycles Interrupts Software Protocol
Local Memory
Local
Host accesses Local Memory Direct Slave Local accesses System Memory Direct Master System Memory Local Memory
Figure 3-3. Direct Master, Direct Slave,
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Mailbox Registers read written from both sides Doorbell Registers clear interrupts
clear
9080
FUNCTIONAL DESCRIPTION
3.5.1.3 Memory Access
clear
Mailbox Mailbox Mailbox Mailbox Mailbox Mailbox Mailbox Mailbox
Local Local
Used Passing: Commands Pointers Status
local processor read write memory read write "Local Base Address Direct Master Memory Register." 9080 will convert local read/write access read/write cycles. Local Address space starts from Direct Master Local Base Address range. remap (PCI Base Address) defines starting address. (Refer Example Section 3.5.2.1). Writes-The 9080 continues accept writes return READYo# until write FIFO full. then holds READYo# until space becomes available write FIFO. programmable Direct Master FIFO "almost full" status output provided (DMPAF#). Reads-The 9080 holds READYo# while gathering Lword from bus. Programmable prefetch modes available prefetch enabled: prefetch NONE, continuous until Direct Master cycle ends. read cycle terminated when local BLAST# input asserted. Unused read data flushed from FIFO. 9080 does prefetch read data single cycle Direct Master reads (local BLAST# input asserted during first data phase). this case, 9080 reads single Lword. Direct Master single cycle reads, 9080 asserts same byte enables asserted local bus. multiple cycle reads, 9080 reads entire long words (all byte enables asserted), regardless local byte enables.
Figure 3-4. Mailbox/Doorbell Message Passing
3.5.1 Direct Master Operation (Local Master Target)
9080 supports direct access either local processor intelligent controller. Five registers used define local access: Range Local Base Address Direct Master Memory Register Local Base Address Direct Master IO/CFG Register Configuration Address Register Direct Master IO/CFG Base Address
3.5.1.1 Decode
Range register specifies local address bits decoding Local access. local processor perform only memory cycles. Therefore, Local Base Address Direct Master Memory Register used decode access memory space Local Base Address Direct Master IO/CFG Register used decode access space configuration cycle access.
3.5.1.4 IO/CFG Access
When Local Direct Master access made, Configuration Address Register's Configuration Enable determines configuration access made bus. Local burst accesses broken into single address/data cycles. 9080 does prefetch read data reads. Direct Master Configuration cycles, 9080 asserts same byte enables asserted local bus.
3.5.1.2 FIFOs
Direct Master memory access bus, 9080 Lword (128 byte) write FIFO Lword byte) read FIFO. FIFOs enable local operate independently allows high-performance bursting local buses.
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SECTION 3.5.1.5
9080
FUNCTIONAL DESCRIPTION
3.5.1.8 Master/Target Abort
9080 Master/Target abort logic enables local master perform Direct Master poll devices determine whether devices exist (typically when local performs configuration cycles bus). Master, Target Abort, Retry Time-out encountered during transfer, 9080 asserts LSERR# (can used NMI). local master waiting READYo#, asserted along with BTERMo#. local master's interrupt handler take appropriate application specific action. then clear abort bits Status Register 9080 clear LSERR# interrupt re-enable Direct Master transfers. local master attempting burst read from non-responding device (Master/Target abort), receives READYo# BTERMo# first cycle only. local processor cannot terminate burst cycle, cause local processor hang. local must then reset from local watch-dog timer asserting RESETi#. local master cannot terminate cycle with BTERMo#, should perform burst cycles when attempting determine device exists.
Configuration Enable clear, single access made bus. local address, remapped decode address bits local byte enables encoded provide address output with read write command during address cycle. writes, data loaded into write FIFO READYo# returned Local bus. reads, 9080 holds READYo# while gathering Lword from bus.
3.5.1.6 (PCI Configuration Type Type Cycles)
Configuration Enable set, access made bus. addition enabling configuration (bit (PCI [2Ch])(Loc [ACh]), user must provide register information. register number (bit [7:2]) device number (bit [15:11]) must modified read/write cycle must performed before other registers devices accessed. Configuration Address Register selects Type command, bits [10:0] from register copied address bits [10:0]. Bits [15:11] "device number" translated into single being address bits [31:11]. address bits [31:11] used device select. Type command, bits [23:0] copied from register bits [23:0] address. address bits [31:24] configuration read write command code output with address during address cycle. writes, local data loaded into write FIFO READYo# returned. reads, 9080 holds READYo# while gathering Lword from bus.
3.5.1.9 Write Invalidate
9080 programmed perform Direct Master write invalidate cycles through Base Address (Remap) Register Command Code Register. Write Invalidate mode, 9080 waits until local writes Lwords before starting access. This ensures that Lword write completes ownership, required write invalidate target with cache line size Lwords. Note: Before write invalidate cycle, command code Direct Master must modified (PCI [6Ch])(Loc [ECh]) cache line size (PCI [0Ch])(Loc [0Ch]) must match target cache line size.
3.5.1.7 Direct Master Lock
9080 supports direct local exclusive accesses (locked atomic operations). locked operation must start with local input LLOCK# being asserted during Direct Master read cycle. Refer timing Section "Timing Diagrams." Locked operations enabled disabled using Base Address Direct Master Register.
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9080
FUNCTIONAL DESCRIPTION
Master
Local Processor
Local Range Direct Master Local Base Address Direct Master Memory Base Address (Remap) Direct Master
Initialize Local Direct Master Access Registers
Local Base Address Direct Master IO/CFG Address Register Direct Master IO/CFG Command Register
Type Enabled Local Access
Access
FIFOs
Deep Write Deep Read
Local Memory Address Space
Base Address
Local Base Address Direct Master Memory Space
Memory Command
Range
Local Base Address Direct Master IO/CFG
Command
Range
Command Type
Address Register
Figure 3-5. Direct Master Access
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9080
FUNCTIONAL DESCRIPTION
write while read pending(RETRY reads) Write flush pending read
3.5.2 Direct Slave Operation (PCI Master Local Access)
9080 supports both memory mapped burst transfer accesses mapped single transfer accesses local from bus. Base Address registers provided location adapter memory space. addition, local mapping registers allow address translation from address space local address space. There three spaces available: Space Space Expansion space
9080 also supports cached read mode, where prefetched data read from 9080 internal FIFO instead from local side. address must subsequent previous address must 32bit aligned (next address current address 9080 programmed keep generating wait state(s), de-asserting TRDY#, write FIFO becomes full. 9080 also programmed keep local bus, LHOLD asserted, Direct Slave Write FIFO becomes empty Direct Slave Read FIFO becomes full. local dropped either case when Local Latency Timer enabled expires. 9080 supports on-the-fly Endian conversion Space Space expansion space. local Big/Little Endian either using BIGEND# input programmable internal register configuration. When BIGEND# asserted, overwrites internal register configuration. Note: always Little Endian.
Expansion space intended support bootable device host. Each local space programmed operate bit, bit, local width. 9080 internal wait state generator external wait state input (READYi#). READYi# disabled enabled with internal configuration register. local bus, independent bus, Burst long data available (Continuous Burst Mode) Burst Lwords time Perform continuous single cycle, with without wait state(s)
3.5.2.1 Local Address Mapping
Three local address spaces-Space Space expansion ROM-are accessible from bus. Each space defined three registers: Local Address Range Local Base Address Base Address
single cycle Direct Slave reads, 9080 reads single local Lword partial Lword. 9080 disconnects after transfer Direct Slave accesses. highest data transfer rate, 9080 supports posted write programmed prefetch data during Burst Read. prefetch size, when enabled, Lwords, until stops requesting. 9080 will prefetch enabled drop local after prefetch counter reached. continuous prefetch mode, 9080 prefetches long FIFO space available terminates prefetch when terminates request. read prefetching disabled, 9080 disconnects after read transfer. local side extremely slow, 9080 programmed through Local Arbitration Mode register perform delayed reads, specified specification 2.1. addition delayed read, 9080 supports following specification features.
fourth register, Region Descriptors Local Accesses Register, defines local characteristics both regions. (Refer Figure 3-6.)
3.5.2.1.1 Byte Enables
LBE[3:0]# (pins 139, 140, 141, 142) encoded based configured width, follows: 32-Bit Bus-For 32-bit bus, four byte enables indicate which four bytes active during data cycle. BE3# Byte Enable 3-LD[31:24] BE2# Byte Enable 2-LD[23:16] BE1# Byte Enable 1-LD[15:8] BE0# Byte Enable 0-LD[7:0]
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9080
FUNCTIONAL DESCRIPTION
16-Bit Bus-For 16-bit bus, BE3#, BE1# BE0# encoded provide BHE#, LA1, BLE#, respectively. BE3# Byte High Enable (BHE#)-LD[15:8] BE2# used BE1# Address (LA1) BE0# Byte Enable (BLE#)- LD[7:0]
3.5.2.1.2 Local Initialization Software
Range-Specifies which address bits decoding access local space. Each bits corresponds address bit. corresponds Address Write value bits that must included decode others. Remap Local Addresses into Local Address Space-The bits this register remap (replace) address bits used decode Local Address bits. Local Region Description-Specifies local characteristics.
8-Bit Bus-For 8-bit bus, BE1# BE0# encoded provide LA0, respectively. BE3# used BE2# used BE1# Address (LA1) BE0# Address (LA0)
Each Local Address space defined part reset initialization described next section.
3.5.2.1.3 Initialization Software
reset software determines much address space required writing value ones Base Address register then reading back value. 9080 return zeroes "don't care" address bits, effectively specifying address space required. software then maps Local Address space into Address space programming Base Address register. (Refer Figure 3-6.)
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SECTION
Master
Initialize Base Address Registers
9080
FUNCTIONAL DESCRIPTION
Local Processor
Range Local Address Space
Local Base Address (Remap) Local Address Space
Initialize Local Direct Access Registers
Region Descriptors Local Accesses
Range Local Expansion
Local Base Address (Remap) Local Expansion
Region Descriptors Local Accesses
Local Hardware Characteristics
Base Address Local Address Space Base Address Local Expansion
Access
FIFOs
Deep Write Deep Read
Local Access
Address Space
Base Address Local Base Address
Local Memory
Range
Figure 3-6. Direct Slave Access Local
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SECTION
9080
FUNCTIONAL DESCRIPTION
Example local address space 12300000h through 123FFFFFh accessible from addresses 78900000h through 789FFFFFh. Local initialization software sets Range Local Base Address Registers follows: Range-FFF00000h decode upper address bits) Local Base Address (remap)-123XXXXXh (Local Base Address local accesses) (Bit Space Enable bit, must recognized host)
3.5.2.2 Deadlock BREQo
deadlock situation occur when master wants access 9080 local same time master local 9080 wants access bus. types deadlock situations occur: PARTIAL DEADLOCK-A master local performing direct master access device other than device that concurrently trying access local bus. FULL DEADLOCK-A master local performing direct master access same device that concurrently trying access local bus. This applies only direct ("pass through") master slave accesses through 9080. Deadlock will occur transfers through 9080 controller mailboxes. PARTIAL DEADLOCK, access local times (the Target Retry Timer, which programmable through Local Region Description Local Accesses Register) 9080 responds with RETRY. specification requires that master release request (de-asserts REQ#) minimum clocks after receiving RETRY. This allows arbiter grant 9080 that complete direct master access free local bus. Possible solutions described below cases which arbiter does function described (PCI architecture dependent), waiting time-out undesirable, FULL DEADLOCK condition exists. FULL DEADLOCK, only solution back local master.
Initialization software writes ones Base Address, then reads back again. 9080 returns value FFF00000h. software then writes Base Address register Base Address-789XXXXXh (PCI Base Address access Local Address space)
direct access local bus, 9080 Lword (128 byte) write FIFO Lword byte) read FIFO. FIFOs enable local operate independently bus. 9080 programmed return RETRY response throttle TRDY# transaction attempting write 9080 local when FIFO full. read transactions from 9080 local bus, 9080 holds TRDY# while gathering local Lword returned. read accesses mapped memory space, 9080 prefetches Lwords (has continuous prefetch mode) from local bus. Unused read data flushed from FIFO. read accesses mapped space, 9080 does prefetch read data. Rather, breaks each read burst cycle into single address/data cycle local bus. period time 9080 holds TRDY# programmed, Target Retry Timer, Local Region Descriptor register. 9080 issues RETRY transaction master when programmed time period expires. This occurs when 9080 cannot gain control local return TRDY# within programmed time period.
3.5.2.2.1 Backoff
9080 contains (BREQo) that indicates possible deadlock condition exists. 9080 starts BREQo timer (can reprogrammed, using registers) when detects following conditions: master local performing direct master access bus. master trying access memory device local gaining access (that received LHOLDA). timer expires 9080 still received LHOLDA, 9080 asserts BREQo.
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SECTION
9080
FUNCTIONAL DESCRIPTION
External logic this signal perform backoff. backoff cycle device/bus architecture dependent. External logic (arbiter) assert necessary signals cause local master release local (backoff). After backing local master, grant 9080 asserting LHOLDA). 9080 considers direct master access terminated when detects LHOLDA. then proceeds with direct slave access. When this access complete 9080 releases local bus, external logic release backoff local master resume cycle that interrupted backoff cycle. write FIFO 9080 retains data acknowledged (that last data which READYo# asserted LHOLDA asserted). Read FIFO 9080 retains data read from (single burst read) returns data Local Master when Local Master returns with same request before backoff. After backoff condition ends, local master restarts last cycle with ADS#. writes, data following this ADS# should data that acknowledged 9080 prior backoff cycle (that last data which READYo# asserted LHOLDA asserted). (The 9080 will assert READYo# signal when local backoff acknowledged, "assert LHOLDA".)
3.5.2.2.3 Software Solutions Deadlock
host software local software combination mailbox registers, doorbell registers, interrupts, direct local accesses direct local accesses avoid deadlock.
3.5.2.3 Direct Slave Lock
9080 supports direct local exclusive accesses (locked atomic operations). locked operation local results entire address space space expansion space being locked until they released master. 9080 asserts LLOCKo# during first clock atomic operation (address cycle) de-asserts minimum clock, following last access atomic operation. LLOCKo# de-asserted after 9080 detects FRAME# LOCK# deasserted same time. Refer timing diagrams Section "Timing Diagrams." Locked operations enabled disabled with Local Region Descriptor Local Accesses Register. responsibility external arbitration logic monitor LLOCKo# enforce meaning atomic operation. example, local master initiates locked operation, local arbiter choose grant local other masters until locked operation complete.
3.5.3 Direct Slave Priority
3.5.2.2.2 Software/Hardware Solution Systems without Backoff Capability
adapters that support backoff, possible deadlock solution follows: host software, external local hardware, general purpose output USERO general purpose input (USERI) used host software prevent deadlock. USERO request that external arbiter grant local master except 9080. status output from local arbiter connected general purpose input USERI indicate that local master owns local bus. input read host determine that local master currently owns local bus. host then direct slave access. When host done, clears USERO. devices that support preempt, USERO used preempt current master device. current local master device completes current cycle gives local (de-asserts LHOLD). Direct Slave accesses have higher priority than accesses. Direct Slave accesses preempt transfers. When 9080 controller owns local bus, LHOLD output LHOLDA input asserted LDSHOLD output de-asserted. When Direct Slave access occurs, 9080 gives local within Lword transfers de-asserting LHOLD floating local outputs. After 9080 samples LHOLDA input de-asserted, requests local Direct Slave transfer asserting LHOLD LDSHOLD. When 9080 receives LHOLDA, drives performs Direct Slave transfer. Upon completion Direct Slave transfer, 9080 gives local de-asserting both LHOLD LDSHOLD floating local outputs. After 9080 samples LHOLDA de-asserted local pause timer zero, requests local transfer re-asserting LHOLD. When receives LHOLDA, drives continues with transfer.
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SECTION
9080
FUNCTIONAL DESCRIPTION
OPERATION
9080 supports independent channels capable transferring data from local from local bus. Each channel consists controller bi-directional FIFO. Both channels support chaining non-chaining transfers, Demand Mode DMA, Transfer (EOT) pins.
direction. host local processor then sets control initiate transfer. 9080 will arbitrate local buses transfer data. Once transfer complete, 9080 generates interrupt either local processor host (programmable). done internal register pooled indicate status transfer. registers accessible from local bus. (Refer Figure 3-7.)
3.6.1 Non-Chaining Mode
host processor local processor sets local address, address, transfer count transfer
Mode Non-Chaining
Mode Register
Host Memory
Memory Block Transfer
Transfer Parameters
Address Register Local Address Register Transfer Size (byte count) Register Descriptor Pointer Register (set direction only)
Local Memory
Memory Block Transfer
Command/Status Register
Enable bits Command/Status Register Initiate Transfer
Figure 3-7. Non-Chaining Initialization
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SECTION 3.6.2 Chaining Mode
Chaining operates follows:
9080
FUNCTIONAL DESCRIPTION
Host Processor Local Processor sets descriptor blocks local host memory that composed address, local address, transfer count, transfer direction address next descriptor block. Host Local Processor then sets address initial descriptor block descriptor pointer register 9080 initiates transfer setting control bit. 9080 loads first descriptor block initiates data transfer. 9080 continues load descriptor blocks
transfer data until detects chain next descriptor pointer register. 9080 programmed interrupt local processor setting "Interrupt after Terminal Count" host upon completion each block transfer after block transfers complete (done) (refer Figure 3-8). chaining descriptors located local memory, controller programmed clear transfer size completion each DMA. (Refer "DMA Clear Count Mode"). Note: descriptor local memory memory, both (first descriptor local memory, second descriptor memory).
Mode Chaining First Address First Local Address First Descriptor Pointer Register (First only requires Descriptor Pointer) Descriptor Pointer Register
Local Host Memory
Mode Register
First Transfer Size (byte count) Next Descriptor Pointer
Host Memory
Address Local Address Transfer Size (byte count) Next Descriptor Pointer
First Memory Block Transfer
Command/Status Register Enable bits Command/Status Register Initate Transfer
Chain Specification First Memory Block Transfer Next Memory Block Transfer
Next Memory Block Transfer
Figure 3-8. Chaining Initialization
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SECTION 3.6.3 Data Transfers
9080
FUNCTIONAL DESCRIPTION
9080 controller programmed transfer data from local side side from side local side. Refer Figure Figure 3-12 description operation.
3.6.3.1 Local Transfer
Interrupt Generation (Programmable)
Local Interrupt Generation (Programmable)
Done Chaining: Terminal Count Current Descriptor
Unload FIFO with Write Cycles
FIFO
Arbitration Local Arbitration
Load FIFO with Local Read Cycles
Done Chaining: Terminal Count Current Descriptor
Chaining Mode Descriptors:
Chaining Mode Descriptors:
start each block transfer, Chaining mode only, loads Registers reading four Lwords from address specified Next Descriptor Pointer Register. Arbitration: GNT# REQ# LHOLDA LHOLD
start each block transfer, Chaining mode only, loads Registers reading four Lwords from address specified Next Descriptor Pointer Register. Local Arbitration:
Releases control whenever FIFO becomes empty, latency timer expires GRANT de-asserts, Disconnect received, Direct Local request pending. Rearbitrates control when preprogrammed number entries FIFO becomes available, after clocks disconnect received.
Releases control local whenever FIFO becomes full, terminal count reached, local latency timer expires, BREQ input asserted, Direct Local request pending. Rearbitrates control local when preprogrammed number empty entries FIFO becomes available. latency timer expired, waits until pause timer expires.
Figure 3-9. Local Data Transfer Operation
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SECTION 3.6.3.2 Local Transfer
Interrupt Generation (Programmable)
9080
FUNCTIONAL DESCRIPTION
Local Interrupt Generation (Programmable)
Done Chaining: Terminal Count Current Descriptor
Load FIFO with Read Cycles
FIFO
Arbitration Local Arbitration
Unload FIFO with Local Write Cycles
Done Chaining: Terminal Count Current Descriptor
Chaining Mode Descriptors:
Chaining Mode Descriptors:
start each block transfer, Chaining mode only, loads Registers reading four Lwords from address specified Next Descriptor Pointer Register. Arbitration: GNT# REQ# LHOLDA LHOLD
start each block transfer, Chaining mode only, loads Registers reading four Lwords from address specified Next Descriptor Pointer Register. Local Arbitration:
Releases control whenever FIFO becomes full, terminal count reached, latency timer expires GRANT de-asserts, Disconnect received, Direct Local request pending. Rearbitrates control when preprogrammed number empty entries FIFO becomes available, after clocks disconnect received.
Releases control local whenever FIFO becomes empty, local latency timer expires, BREQ input asserted, Direct Local request pending. Rearbitrates control local when preprogrammed number entries becomes available FIFO terminal count reached. latency timer expired, waits until pause timer expires.
Figure 3-10. Local Data Transfer Operation
3.6.3.3 Unaligned Transfers
unaligned local transfers, 9080 reads partial Lword from local bus. then continues read Lwords from local bus. Lwords assembled, aligned address loaded into FIFO. local transfers, Lwords read from loaded into FIFO. local side, Lwords assembled from FIFO, aligned local address written local bus. both local buses, byte enables writes determine start transfer. last transfer, byte enables specify bytes written. reads Lwords.
Mode, user sets configuration registers controller initiates transfer. controller transfers data when asserts DREQ[1:0]# input channel. controller then asserts DACK[1:0]# indicate that current local transfer response DREQ[1:0]# input. controller continues transfer data until reaches transfer count until DREQ[1:0]# de-asserted. minimum transfer size DREQ[1:0]# input Lword bits). This result multiple transfers 16-bit bus. Refer timing diagrams Section "Timing Diagrams."
3.6.5 Priority
Channel priority, Channel priority, rotating priority specified Arbitration Register.
3.6.4 Demand Mode
Configuration Registers specifies that channel operates Demand Mode. Demand
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SECTION 3.6.6 Arbitration
9080
FUNCTIONAL DESCRIPTION
BREQ INPUT
When 9080 owns local bus, both LHOLD output LHOLDA input asserted. When 9080 samples BREQ asserted during transfer Direct Slave write transfer, gives local within Lword transfers de-asserting LHOLD floating local outputs BREQ gated disabled, gating enabled Local Latency Timer expires. Local Arbiter grant local another local master. After 9080 samples that LHOLDA de-asserted local pause timer zero, re-asserts LHOLD request local bus. When 9080 receives LHOLDA, drives continues from where left off.
9080 controller releases control local (de-asserts LHOLD) when following occurs: FIFOs full local transfer FIFOs empty local transfer Local Latency Timer expires enabled) BREQ input asserted (BREQ enabled disabled, gated with latency timer before 9080 gives local bus) Direct Slave access pending input received enabled)
controller releases control when following occurs: FIFOs full empty When Latency Timer expires loses grant signal receives Target Disconnect response
DOORBELL REGISTERS
There doorbell interrupt/status registers 9080. assigned interface while other assigned local interface. local processor generate interrupt writing number other than zeroes local doorbell register. host generate local interrupt writing number other than zeroes local doorbell register.
de-asserts request (REQ#) minimum clocks.
3.6.6.1 Transfer (EOT0# EOT1#) Input
When asserted, current transfer terminates, regardless transfer size. Local transfers will terminate after current cycle. transfer will terminate immediately transfer from local. transfer from local PCI, 9080 finishes transferring data internal FIFO terminates transfer
MAILBOX REGISTERS
There eight mailbox registers 9080 that written read from both buses. These registers used pass command status information directly between local devices. local interrupt generated, enabled, when host writes first four mailbox registers.
3.6.6.2 Local Latency Pause Timers
Local Latency Timer Local Pause Timer programmable with Arbitration Register. local latency timer expires, 9080 completes current Lword transfer releases LHOLD. After programmable Pause Timer expires, reasserts LHOLD. When receives LHOLDA, continues transfer. transfer continues until FIFO empty local transfer until full local transfer.
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FUNCTIONAL DESCRIPTION
3.10 INTERRUPTS
Parity Error Master Abort Retrys Target Abort Messaging Queue
[12]
Done Terminal Count Doorbells
LSERR#
[17]
Mailboxes Done Terminal Count Doorbells Master Abort Retrys Target Abort LINTi#
[12] [10]
[16]
LINTo#
BIST
[23]
Messaging Queue
Done Terminal Count
[11]
INTA#
represent register (LOC [E8h]) [7:6] register (LOC [168h]) [10] register (LOC [100h]) register (LOC [E110h]) [18] register (LOC [E8h]) [17] register (LOC [100h]) [5:4] register (LOC [168h]) [10] register (LOC [114h]) register (LOC [124h]) [19] register (LOC [E8h]) [17] register (LOC [114h]) register (LOC [B0h]) register (LOC [B4h])
Messaging Queue Done Terminal Count
[17]='0' then LINTo# generated [17]='1' then INTA# generated.
Figure 3-11. Interrupt Error Sources
3.10.1 Interrupts (INTA#)
9080 Interrupt (INTA#) generated following: Local doorbell register Local interrupt input Master/target abort status condition 0/Ch Done 0/Ch Terminal Count reached Messaging Outbound Post Queue Empty
3.10.1.1 Local Interrupt Input
Asserting Local input LINTi# generate interrupt. host processor read 9080 Interrupt Control/Status Register determine that interrupt pending LINTi# being asserted. interrupt remains asserted long LINTi# asserted Local Interrupt input enabled. Adapter specific action taken host processor cause local release LINTi#.
INTA#, individual sources interrupt, enabled disabled with 9080 Interrupt Control/Status Register. Interrupt Control/Status Register also provides interrupt status each source interrupt. 9080 interrupt level output. interrupt cleared disabling interrupt enable clearing cause(s) interrupt.
3.10.1.2 Master/Target Abort Interrupt
9080 sets master abort target abort status configuration register when detects master target abort. These status bits cause INTA# asserted interrupts enabled. interrupt remains asserted long master target abort bits remain Configuration Status Register master/target abort interrupt enabled. Type configuration access
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FUNCTIONAL DESCRIPTION
de-asserts
local access clear master abort target abort interrupt bits Configuration Status Register. Bits [26:24] Interrupt Control/Status Register latched time target abort interrupt master abort interrupt. They provide information master when abort occurred. 9080 updates these bits whenever abort occurs.
register), 9080 automatically READYo# prevent local accesses.
3.10.2.2 Local Doorbell Interrupt
master generate local interrupt writing Local Doorbell Register. Local processor then read 9080 Interrupt Control/Status Register determine that doorbell interrupt pending. then read 9080 Local Doorbell Register. Each Local Doorbell register individually controlled. Bits Doorbell Register only side. From side, writing position sets that writing position effect. Bits Local Doorbell Register only cleared from local side. From local side, writing position clears that writing position effect. Note: local side cannot clear Doorbell Interrupt, Local Doorbell Register. interrupt remains asserted long Local Doorbell Register bits Local Doorbell interrupt enabled. prevent race conditions when local accessing Doorbell Register configuration register), 9080 automatically issues RETRY bus.
3.10.2 Local Interrupts (LINTo#)
9080 Local Interrupt (LINTo#) generated following: Local Doorbell/Mailboxes Register access BIST interrupt, done interrupt terminal count reached abort interrupt messaging outbound post queue empty
LINTo#, individual sources interrupt, enabled disabled with 9080 Interrupt Control/Status Register. Interrupt Control/Status Register also provides interrupt status each source interrupt. 9080 local interrupt level output. interrupt cleared disabling interrupt enable source clearing cause interrupt.
3.10.2.1 Local Doorbell Interrupt
local master generate interrupt writing Local Doorbell Register. host processor then read 9080 Interrupt Control/Status Register determine that doorbell interrupt pending. then read 9080 Local Doorbell Register. Each Local Doorbell register individually controlled. Bits Doorbell Register only local side. From local side, writing position sets that writing position effect. Bits Local Doorbell Register only cleared from side. From side, writing position clears that writing position effect. interrupt remains asserted long Local Doorbell Register bits Doorbell interrupt enabled. prevent race conditions when accessing Doorbell Register configuration
3.10.2.3 Built Self Test Interrupt (BIST)
master generate local interrupt performing Type configuration write BIST register. local processor then read 9080 Interrupt Control/Status Register determine that BIST interrupt pending. interrupt remains asserted long BIST interrupt enabled. local then resets when BIST complete. Host software fail device reset after seconds. Note: 9080 does have internal BIST.
3.10.2.4 Channel Interrupts
channel generate local interrupt when done (transfer complete) after transfer complete descriptor chaining mode. mode register determines whether generate local interrupt. local processor then read 9080 Interrupt Control/Status Register determine whether
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FUNCTIONAL DESCRIPTION
channel interrupt pending. Done Status Control/Status Register used determine whether interrupt done interrupt result transfer descriptor chain that complete
3.11 COMPATIBLE MESSAGE UNIT
Messaging Unit supplies paths messages, inbound FIFOs receive messages from primary outbound FIFOs pass messages primary bus. Refer Architecture Specification v1.5 details. Figure 3-12 Figure 3-13 illustrate information about architecture.
hardware changes required host side Message Frames Host Physical System Memory
Mode Register channel enables done interrupt. chaining mode, Next Descriptor Pointer Register channel (loaded from local memory) specifies whether generate interrupt transfer current descriptor. channel interrupt cleared writing Clear Interrupt Command/Status Register.
Inbound Queue Outbound Queue Must Have: Memory Messaging Unit
3.10.3 SERR# (PCI NMI)
9080 generates SERR# pulse parity checking enabled Command Register detects address parity error Generate SERR# Interrupt Control/Status Register written. SERR# output enabled disabled with Command Register.
Local Memory Message Frames
Intelligent processor
Figure 3-12. System Architecture
Current Architecture
Specific Module
Architecture
3.10.4 Local LSERR# (Local NMI)
LSERR# interrupt output asserted Target Abort Master Abort status Status Configuration Register, parity error status Status Configuration Register, messaging outbound free queue overflows. parity error checking enabled Command Register, 9080 sets Master Detected Parity Error Status Status Register detects following: parity error during 9080 master read signal PERR# being asserted during 9080 master write
Hardware Device Module
Messaging Layer
Hardware
Operating System Master Hardware Device Module
Hardware
Figure 3-13. Software Architecture
3.11.1 Inbound Messages
Inbound messages reside pool message frames (minimum 64-byte frames) allocated shared local (IOP) memory. inbound message queue comprised pair rotating FIFOs implemented local memory. Inbound Free List FIFO holds message frame addresses (MFA) available message frames local memory. Inbound Post List FIFO holds currently-posted messages. inbound circular FIFOs accessed external agents through Inbound Queue Port location address space. Inbound Queue Port, when
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9080 sets parity error Status Register detects data parity error during 9080 master read, data parity error during slave write access 9080 address parity error. 9080 Interrupt Control/Status Register used individually enable disable LSERR# abort parity error. LSERR# level output that remains asserted long Abort Parity Error Status bits set.
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SECTION
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FUNCTIONAL DESCRIPTION
read external agent, returns Inbound Free List FIFO MFA. external agent places message frame into Inbound Post List FIFO writing inbound queue port location.
3.11.2 Outbound Messages
Outbound messages reside pool message frames (minimum 64-byte frames) allocated shared (Host System) memory. outbound message queue comprised pair rotating FIFOs implemented local memory. Outbound Free List FIFO holds message frame addresses (MFA) available message frames system memory. Outbound Post List FIFO holds currently posted messages. outbound circular FIFOs accessed external agents through Outbound Queue Port location address space. Outbound Queue Port, when read external agent, returns Outbound Post List FIFO MFA. external agent places free message frames into Outbound Free List FIFO writing free into Outbound Queue Port location. Memory circular FIFOs themselves must allocated local (IOP) memory. queues base address contained Queue Base Address Register (QBAR). Each FIFO entry data value. Each read write queue must single 32-bit access. circular FIFOs range size from entries entries. four FIFOs must same size contiguous. Therefore, total amount local memory needed circular FIFOs ranges from FIFO size specified Messaging Queue Configuration Register (MQCR). starting address each FIFO based Queue base Address FIFO Size, listed Table 3-4. Table 3-4. Queue Starting Address
FIFO Inbound Free List Inbound Post List Outbound Post List Outbound Free List Starting Address QBAR QBAR FIFO Size) QBAR FIFO Size) QBAR FIFO Size)
processor must initialize Inbound Post Free Head Pointer Registers, Inbound Post Free Tail Pointer Registers, Outbound Post Free Head Pointer Registers, Outbound Post Free Tail Pointer Registers with initial offset according FIFO size configured. Messaging Unit will automatically Queue Base Address offset each head tail pointer register. software then enable I2O. After initialization, local software should write pointers managed hardware. empty flags queues disabled (MQCR head tail pointers equal. This occurs independently head tail pointers set. empty flag cleared, signifying empty, only queues enabled pointers become equal. empty flag cleared queues enabled, empty flag will only tail pointer incremented head tail pointers become equal. Full flags always cleared when queues disabled head tail pointers equal. full flag when queues enabled, head pointer incremented, head tail pointers become equal. Each circular FIFO head pointer tail pointer, which offsets from Queue Base Address. Writes FIFO occur head FIFO reads occur from tail. head tail pointers incremented either local processor hardware. unit that writes FIFO also maintains pointer. pointers incremented after FIFO access. Both pointers wrap around first address circular FIFO when they reach FIFO size, that head tail pointers "chase" each other around around circular FIFO. will wrap pointers automatically pointers that maintains. software must wrap pointers that maintains. Whenever they equal, FIFO empty. prevent overflow conditions, specifies that number message frames allocated should less than equal number entries FIFO. (Refer Figure 3-14 additional information.) Each inbound specified offset from start shared local (IOP) memory region start message frame. Each outbound specified offset from Host memory location 0x00000000h start message frame shared Host memory. Since actual address, message frames themselves need
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3.11.3 Pointer Management
FIFOs always reside shared local (IOP) memory allocated initialized IOP. Before enabling (MQCR register local
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FUNCTIONAL DESCRIPTION
contiguous. allocates initializes inbound message frames shared memory using suitable memory allocation technique. Host allocates initializes outbound message frames shared Host memory using suitable memory allocation technique. Message frames minimum bytes length. uses "push" (write preferred) memory model. That means that will write messages data shared Host memory, Host will write messages data shared memory. Software should make burst transfers whenever possible ensure efficient message passing. Additional information message passing implementation found Architecture Specification v1.5.
free (available) message frame into Inbound Free List FIFO writing into FIFO location pointed Queue Base Register Inbound Free Head Pointer Register. local processor must then increment Inbound Free Head Pointer Register. master (Host another IOP) obtain free message frame reading Inbound Queue Port Address (40h first Memory Base Address Register). FIFO empty free inbound message frames currently available, head tail pointers equal), returns value (FFFFFFFFh). FIFO empty (head tail pointers equal), reads pointed Queue Base Register Inbound Free Tail Pointer Register, returns value increments Inbound Free Tail Pointer Register. Inbound Free Queue empty, queue prefetching enabled (QSR Register then next entry FIFO will read from local into prefetch register. data next read from this queue will then provided prefetch register, thus reducing number wait states.
3.11.4 Inbound Free List FIFO
local processor allocates inbound message frames shared memory place address
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High Address Local Memory
FUNCTIONAL DESCRIPTION
Write External Agent Read Outbound Queue Port Outbound Free List FIFO Incremented 9080 hardware Head Pointer Tail Pointer
Incremented local processor
Local Processor
Read
Outbound Queue
Write Outbound Post List FIFO Incremented local processor Head Pointer Tail Pointer
Incremented 9080 hardware
Write External Agent Read Inbound Queue Port Inbound Post List FIFO Incremented 9080 hardware Head Pointer Tail Pointer
Incremented local processor
Local Processor
Read
Inbound Queue
Write Inbound Free List FIFO Incremented local processor Head Pointer Tail Pointer
Incremented 9080 hardware Address Local Memory
Figure 3-14. Circular FIFO Operation
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SECTION 3.11.5 Inbound Post List FIFO
9080
FUNCTIONAL DESCRIPTION
Register, returns value increments Outbound Post Tail Pointer Register. 9080 generates Interrupt when Outbound Post Head Pointer Register equal Outbound Post Tail Pointer Register. Outbound Post List FIFO Interrupt Outbound Post List FIFO Interrupt Status (OPLFIS) Register indicates interrupt status. When pointers become equal, both interrupt Outbound Post List FIFO interrupt automatically cleared. pointers become equal when master (Host another IOP) reads enough FIFO entries empty FIFO. interrupt masked Outbound Post List FIFO Interrupt Mask (OPLFIM) Register).
master (Host another IOP) write message into available message frame shared local (IOP) memory. then post that message writing message frame address (MFA) Inbound Queue Port Address (40h first Memory Base Address Register). When port written, writes Inbound Post List FIFO location pointed Queue Base Register FIFO Size Inbound Post Head Pointer Register. After writes Inbound Post List FIFO, increments Inbound Post Head Pointer Register. Inbound Post Tail Pointer Register points Inbound Post List FIFO location which holds oldest posted message. tail pointer maintained local processor. After local processor reads oldest MFA, remove from Inbound Post List FIFO incrementing Inbound Post Tail Pointer Register. 9080 generates local Interrupt when Inbound Post List FIFO empty. Inbound Post List FIFO Interrupt Queue Status/Control Register (QSR) indicates interrupt status. interrupt clears when Inbound Post List FIFO empty. interrupt masked Inbound Post List FIFO Interrupt Mask Bit. prevent race conditions from time write transaction received until data written local memory Inbound Post Head Pointer Register incremented, direct slave access 9080 issued RETRY.
3.11.7 Outbound Free List FIFO
master (Host another IOP) allocates outbound message frames shared memory place address free (available) message frame into Outbound Free List FIFO writing message frame address (MFA) Outbound Queue Port Address (44h first Memory Base Address Register). When port written, writes Outbound Free List FIFO location pointed Queue Base Register FIFO Size) Outbound Free Head Pointer Register. After writes Outbound Free List FIFO, increments Outbound Free Head Pointer Register. When needs free outbound message frame, must first check whether there free frames available. Outbound Free List FIFO empty (outbound free head tail pointers equal), must wait Host place additional outbound free message frames Outbound Free List FIFO. Outbound Free List FIFO empty (head tail pointers equal), obtain oldest free outbound message frame reading location pointed Queue Base Register FIFO Size) Outbound Free Tail Pointer Register. After reads MFA, must increment Outbound Free Tail Pointer Register. prevent overflow conditions, specifies that number message frames allocated should less than equal number entries FIFO. will also check overflows Outbound Free List FIFO When head pointer incremented becomes equal tail pointer, Outbound Free List FIFO full, generates local LSERR (NMI)
3.11.6 Outbound Post List FIFO
local master (IOP) write message into available message frame shared Host memory. then post that message writing message frame address (MFA) Outbound Post List FIFO location pointed Queue Base Register Outbound Post Head Pointer Register FIFO Size). local processor should then increment Outbound Post Head Pointer Register. master obtain oldest posted message reading Outbound Queue Port Address (44h first Memory Base Address Register). FIFO empty more outbound messages posted, head tail pointers equal), returns value (FFFFFFFFh). Outbound Post List FIFO empty (head tail pointers equal), reads pointed Queue Base Register FIFO Size) outbound Post Tail Pointer
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FUNCTIONAL DESCRIPTION
interrupt. interrupt recorded Queue Status Control (QSR) Register. From time that write transaction received until data written into local memory Table 3-5. Circular FIFO Summary
FIFO Name Inbound Free List FIFO Inbound Post List FIFO Outbound Post List FIFO Outbound Free List FIFO Port Inbound Queue Port (Host read) Inbound Queue Port (Host write) Outbound Queue Port (Host read) Outbound Queue Port (Host write) Generate Interrupt? Yes, when FIFO empty
Outbound Free Head Pointer Register incremented, direct slave access 9080 issued RETRY.
Generate Local Interrupt Yes, when Port written Yes, (LSERR) when FIFO full
Head Pointer Maintained Local processor hardware Local processor hardware
Tail Pointer Maintained hardware Local processor hardware Local processor
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REGISTERS
REGISTERS
REGISTER DEFINITIONS SUMMARY
Refer descriptions following sections full explanation. Table 4-1. Registers Definitions Summary
Offset Local Offset 12Ch Register LARBR Bits LBRD0 DMPBAM 15:14 OPLFIS OPLFIM INTCSR 31:28 100h DMAMODE0 114h DMAMODE1 140h 144h 148h 14Ch 150h 154h 158h 15Ch 160h 164h 168h 170h 174h 178h MQCR QBAR IFHPR IFTPR IPHPR IPTPR OFHPR OFTPR OPHPR OPTPR LAS1RR LAS1BA LBRD1 Description PCIREQMODE output. Cached read mode. Single read mode removed. Extend almost full flag five bits (fifth contiguous). CDMPFLIMIT output; prefetch past boundary Direct master read prefetch size control. Remap select. Direct master write delay. outbound post list FIFO interrupt status register. outbound post List FIFO interrupt mask register. inbound queue port register. outbound queue port register. Move DMA0INTSEL output DMAMODE0. Change reserved. Move DMA1INTSEL output DMAMODE1. Change reserved. Mailbox interrupt enable 9060. Mailbox interrupts 9060. Clear byte count chaining descriptor. C0_INTSEL output. 0=local int., 1=PCI int. Clear byte count chaining descriptor. C1_INTSEL output. 0=local int., 1=PCI int. messaging queue configuration register. queue base address register. inbound free head pointer. inbound free tail pointer. inbound post head pointer. inbound post tail pointer. outbound free head pointer. outbound free tail pointer. outbound post head pointer. outbound post tail pointer. queue status register. Local Address Space Range Register local. Local Address Space Local Base Address (Remap). Local Address Space Region Descriptor.
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4.1.1 Register Differences between 9080 9060, 9060ES, 9060SD
Table 4-2. Register Differences between 9080 9060
Register PCIIDR PCICR PCISR PCICLSR PCIBAR0 PCIBAR1 PCIBAR3 PCISVID PCISID LARBR LARBR LARBR LARBR LARBR LARBR LARBR LARBR LARBR BIGEND EROMBA LBRD0 LBRD0 LBRD0 LBRD0 LBRD0 DMPBAM DMPBAM DMPBAM DMPBAM DMPBAM LAS1RR LAS1BA LBRD1 MBOX0 MBOX1 PCI/Local Offset 00/00 04/04 06/06 0C/0C 10/10 14/14 1C/1C 2C/2C 2E/2E AC/88, AC/88, AC/88, AC/88, AC/88, AC/88, AC/88, AC/88, AC/88, 0C/8C 14/94 18/98 18/98 18/98 18/98 18/98 28/A8 28/A8 28/A8 28/A8 28/A8 F0/170 F4/174 F8/178 78/C0 7C/C4 Bits 31:16 31:0 15:0 15:0 31:0 14:11 17:16 15:14 31:0 31:0 31:0 31:0 31:0 Description Default changed from 9060 9080 Memory Write Invalidate supported User definable added Cache line size used Memory Write Invalidate Register Bank size changed from Register Bank size changed from Base address register local address space Subsystem Vendor register Subsystem register Local/DMA Arbitration Register accessible from Local Direct Slave Give mode Direct Slave Lock Enable Request Mode Mode Read/No Write Mode Read with Write Flush Mode Local Latency Timer with BREQ Read/No Flush Mode Big/Little Endian Descriptor Register BREQo Timer Resolution control Local width programmable mode Read Prefetch Count Enable Read Prefetch Count Local width programmable mode Extra long EEPROM load Direct Master Read Prefetch Size Control Programmable Almost Full Flag increased bits Direct Master Prefetch Limit Remap select Direct Master Write Delay Local Address Space Range Register Local Address Space Local Base Address Register (Remap) Local Address Space Region Descriptor Register MBOX0 moved address when Messaging Queue enabled MBOX1 moved address when Messaging Queue enabled
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Table 4-2. Register Differences between 9080 9060 (continued)
Register INTCSR INTCSR INTCSR INTCSR INTCSR PCIHIDR PCIHREV DMAMODE0 DMAMODE0 DMAMODE0 DMAMODE0 DMAMODE0 DMAMODE0 DMADPR0 DMAMODE1 DMAMODE1 DMAMODE1 DMAMODE1 DMAMODE1 DMADPR1 DMACSR0 DMACSR1 DMATHR OPQIS OPQIM MQCR QBAR IFHPR IFTPR IPHPR IPTPR OFHPR OFTPR OFHPR OPTPR PCI/Local Offset 68/E8 68/E8 68/E8 68/E8 68/E8 70/F0 74/F4 80/100 80/100 80/100 80/100 80/100 80/100 90/110 94/114 94/114 94/114 94/114 94/114 A4/124 A8/128 A9/129 B0/130 30/B0 34/B4 C0/140 C4/144 C8/148 CC/14C D0/150 D4/154 D8/158 DC/15C E0/160 E4/164 E8/168 Bits 31:0 15:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 Description Mailbox Interrupt Enable Mailbox Interrupt Status Mailbox Interrupt Status Mailbox Interrupt Status Mailbox Interrupt Status Permanent Configuration Register Permanent Revision Register Write Invalidate Mode Channel transfers Write Invalidate Mode (End Transfer) Input Enable Stop Data Transfer Mode Clear Count Mode Interrupt Select Descriptor Location Selector (PCI Local) Write Invalidate Mode (End Transfer) Input Enable Stop Data Transfer Mode Clear Count Mode Interrupt Select Descriptor Location Selector (PCI Local) Channel Done Channel Done Changed thresholds accommodate word write FIFOs Outbound Post Queue Interrupt Status Register Outbound Post Queue Interrupt Mask Register Inbound Queue Port Outbound Queue Port Messaging Queue Configuration Register Queue Base Address Register Inbound Free Head Pointer Register Inbound Free Tail Pointer Register Inbound Post Head Pointer Register Inbound Post Tail Pointer Register Outbound Free Head Pointer Register Outbound Free Tail Pointer Register Outbound Post Head Pointer Register Outbound Post Tail Pointer Register Queue Status/Control Register
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Table 4-3. Register Differences between 9080 9060ES
Register PCIIDR PCISR PCICLSR PCIBAR0 PCIBAR1 PCIBAR3 PCISVID PCISID LARBR LARBR LARBR LARBR LARBR LARBR BIGEND BIGEND BIGEND EROMBA LBRD0 LBRD0 LBRD0 LBRD0 DMPBAM DMPBAM DMPBAM DMPBAM DMPBAM LAS1RR LAS1BA LBRD1 MBOX0 MBOX1 MBOX4 MBOX5 MBOX6 MBOX7 P2LDBELL L2PDBELL INTCSR PCI/Local Offset 00/00 06/06 0C/0C 10/10 14/14 1C/1C 2C/2C 2E/2E AC/88, AC/88, AC/88, AC/88, AC/88, AC/88, 0C/8C 0C/8C 0C/8C 14/94 18/98 18/98 18/98 18/98 28/A8 28/A8 28/A8 28/A8 28/A8 F0/170 F4/174 F8/178 78/C0 7C/C4 50/D0 54/D4 58/D8 5C/DC 60/E0 64/E4 68/E8 Bits 31:16 31:0 15:0 15:0 20:19 17:16 15:14 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:8 31:8 Description Default changed from 906E 9080 User definable added Cache line size used Memory Write Invalidate Register Bank size changed from Register Bank size changed from Base address register local address space Subsystem Vendor register Subsystem register Channel Priority Request Mode Read/No Write Mode Read with Write Flush Mode Local Latency Timer with BREQ Read/No Flush Mode Direct Slave Endian Mode Channel Endian Mode Channel Endian Mode BREQo Timer Resolution control Local width programmable mode Single Read Access Mode removed Local width programmable mode Extra long EEPROM load Direct Master Read Prefetch Size Control Programmable Almost Full Flag increased Direct Master Prefetch Limit Remap select Direct Master Write Delay Local Address Space Range Register Local Address Space Local Base Address Register (Remap) Local Address Space Region Descriptor Register MBOX0 moved address when Messaging Queue enabled MBOX1 moved address when Messaging Queue enabled MBOX4 added MBOX5 added MBOX6 added MBOX7 added more doorbell bits added local doorbell register more doorbell bits added local doorbell register Mailbox Interrupt Enable
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Table 4-3. Register Differences between 9080 9060ES (continued)
Register INTCSR INTCSR INTCSR INTCSR INTCSR INTCSR INTCSR INTCSR INTCSR INTCSR CNTRL CNTRL PCIHREV DMAMODE0 DMAPADR0 DMALADR0 DMASIZ0 DMADPR0 DMAMODE1 DMAPADR1 DMALADR1 DMASIZ1 DMADPR1 DMACSR0 DMACSR1 DMATHR OPQIS OPQIM MQCR QBAR IFHPR IFTPR IPHPR IPTPR OFHPR OFTPR OFHPR OPTPR PCI/Local Offset 68/E8 68/E8 68/E8 68/E8 68/E8 68/E8 68/E8 68/E8 68/E8 68/E8 6C/EC 6C/EC 74/F4 80/100 84/104 88/108 8C/10C 90/110 94/114 98/108 9C/11C A0/120 A4/124 A8/128 A9/129 B0/130 30/B0 34/B4 C0/140 C4/144 C8/148 CC/14C D0/150 D4/154 D8/158 DC/15C E0/160 E4/164 E8/168 Bits 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 Description Channel interrupt enable Channel interrupt enable Channel interrupt status Channel interrupt status Channel active during abort Channel active during abort Mailbox Interrupt Status Mailbox Interrupt Status Mailbox Interrupt Status Mailbox Interrupt Status Read command Write command Permanent Revision Register Channel Mode Register Channel Address Register Channel Local Address Register Channel Size Register Channel Descriptor Pointer Register Channel Mode Register Channel address Register Channel Local address Register Channel Size Register Channel Descriptor Pointer Register Channel Command/Status Channel Command/Status Threshold Register Outbound Post Queue Interrupt Status Register Outbound Post Queue Interrupt Mask Register Inbound Queue Port Outbound Queue Port Messaging Queue Configuration Register Queue Base Address Register Inbound Free Head Pointer Register Inbound Free Tail Pointer Register Inbound Post Head Pointer Register Inbound Post Tail Pointer Register Outbound Free Head Pointer Register Outbound Free Tail Pointer Register Outbound Post Head Pointer Register Outbound Post Tail Pointer Register Queue Status/Control Register
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REGISTERS
Table 4-4. Register Differences between 9080 9060SD
Register PCIIDR PCISR PCIBAR0 PCIBAR1 PCISVID PCISID LARBR LARBR LARBR BIGEND BIGEND EROMBA EROMBA EROMBA LBRD0 LBRD0 LBRD0 DMRR DMLBAM DMLBAI DMPBAM LAS1RR LAS1BA LBRD1 LBRD1 MBOX0 MBOX1 MBOX4 MBOX5 MBOX6 MBOX7 INTCSR INTCSR INTCSR INTCSR PCIHREV PCI/Local Offset 00/00 06/06 10/10 14/14 2C/2C 2E/2E AC/88, AC/88, AC/88, 0C/8C 0C/8C 14/94 14/94 14/94 18/98 18/98 18/98 1C/9C 20/A0 24/A4 28/A8 F0/170 F4/174 F8/178 F8/178 40,78/C0 7C/C4 50/D0 54/D4 58/D8 5C/DC 68/E8 68/E8 68/E8 68/E8 74/F4 Bits 31:16 15:0 15:0 31:0 17:16 31:16 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 Description Default changed from 906D 9080 User definable added Register Bank size changed from Register Bank size changed from Subsystem Vendor register Subsystem register Local/DMA Arbitration Register accessible from Request Mode Read/No Flush Mode Direct Master Endian Mode Channel Endian Mode Direct Slave BREQo Delay Clocks Local BREQo Enable BREQo Timer Resolution control Local width programmable mode Single Read Access Mode removed Local width programmable mode Local Range Register Direct Master Local Base Address Register Direct Master Memory Local Base Address Register Direct Master IO/CFG Base Address (Remap) Register Direct Master Memory Local Address Space Range Register 30/B0 9060SD Local Address Space Local Base Address Register (Remap) 34/B4 9060SD Local Address Space Region Descriptor Register 38/B8 9060SD Single Read Access Mode removed MBOX0 moved address when Messaging Queue enabled MBOX1 moved address when Messaging Queue enabled MBOX4 added MBOX5 added MBOX6 added MBOX7 added Channel interrupt enable Channel interrupt active Direct Master active during abort Channel active during abort Permanent Revision Register
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REGISTERS
Table 4-4. Register Differences between 9080 9060SD (continued)
Register DMAMODE0 DMAPADR0 DMALADR0 DMASIZ0 DMADPR0 DMACSR0 DMATHR OPQIS OPQIM MQCR QBAR IFHPR IFTPR IPHPR IPTPR OFHPR OFTPR OFHPR OPTPR PCI/Local Offset 80/100 84/104 88/108 8C/10C 90/110 A8/128 B0/130 30/B0 34/B4 C0/140 C4/144 C8/148 CC/14C D0/150 D4/154 D8/158 DC/15C E0/160 E4/164 E8/168 Bits 31:0 31:0 31:0 31:0 31:0 15:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 Description Channel Mode Register Channel Address Register Channel Local Address Register Channel Transfer Size Register Channel Descriptor Pointer Register Channel Command/Status Register Channel Thresholds Outbound Post Queue Interrupt Status Register Outbound Post Queue Interrupt Mask Register Inbound Queue Port Outbound Queue Port Messaging Queue Configuration Register Queue Base Address Register Inbound Free Head Pointer Register Inbound Free Tail Pointer Register Inbound Post Head Pointer Register Inbound Post Tail Pointer Register Outbound Free Head Pointer Register Outbound Free Tail Pointer Register Outbound Post Head Pointer Register Outbound Post Tail Pointer Register Queue Status/Control Register
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REGISTERS
REGISTER ADDRESS MAPPING
4.2.1 Configuration Registers
Table 4-5. Configuration Registers
Register Address Local Access (Offset from Chip Select Address) ensure software compatibility with other versions 9080 family ensure compatibility with future enhancements, write zero unused bits. PCI/Local Writable EEPROM Writable
Max_Lat BIST
Local Revision Local [15:0], Local Local
Device Status Class Code Header Type
Vendor Command
Latency Timer
Cache Line Size
Base Address Memory Mapped Configuration Registers Base Address Mapped Configuration Registers Base Address Local Address Space Base Address Local Address Space Unused Base Address Unused Base Address Cardbus Pointer (Not Supported) Subsystem Subsystem Vendor
Base Address Local Expansion Reserved Reserved Min_Gnt Interrupt Interrupt Line
[7:0], Local
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SECTION 4.2.2 Local Configuration Registers
Table 4-6. Local Configuration Registers
(Offset from Base Address) Local Access (Offset from Chip Select Address) 170h 174h 178h
9080
REGISTERS
ensure software compatibility with other versions 9080 family ensure compatibility with future enhancements, write zero unused bits.
PCI/Local Writable
EEPROM Writable
Range Local Address Space Local Base Address (Remap) Local Address Space Local/DMA Arbitration Register Big/Little Endian Descriptor Register Range Local Expansion
Local Base Address (Remap) Local Expansion BREQo control Local Region Descriptors (Space Expansion ROM) Local Accesses Range Direct Master Local Base Address Direct Master Memory Local Base Address Direct Master IO/CFG Base Address (Remap) Direct Master Configuration Address Register Direct Master IO/CFG Range Local Address Space Local Base Address (Remap) Local Address Space Local Region Descriptor (Space Local Accesses
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SECTION 4.2.3 Runtime Registers
Table 4-7. Runtime Registers
(Offset from Base Address) Local Access (Offset from Chip Select Address)
9080
REGISTERS
ensure software compatibility with other versions 9080 family ensure compatibility with future enhancements, write zero unused bits.
PCI/Local Writable
EEPROM Writable
Mailbox Register Mailbox Register
Mailbox Register Mailbox Register Mailbox Register Mailbox Register Mailbox Register Mailbox Register Local Doorbell Register Local Doorbell Register Interrupt Control Status EEPROM Control, Command Codes, User Control, Init Control Device Unused Mailbox Register Mailbox Register
Vendor Revision
Note: Mailbox registers always accessible addresses 78h/C0h 7Ch/C4. When feature disabled (bit register mailbox registers also accessible addresses 9060 compatibility. When feature enabled, Inbound Outbound Queue pointers accessed addresses replacing mailbox registers address space.
©PLX Technology, Inc., 1997
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SECTION 4.2.4 Registers
Table 4-8. Registers
(Offset from Base Address) Local Access (Offset from Chip Select Address) 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h 128h Reserved
9080
REGISTERS
ensure software compatibility with other versions 9080 family ensure compatibility with future enhancements, write zero unused bits.
PCI/Local Writable
EEPROM Writable
Mode Address Local Address Transfer Byte Count Descriptor Pointer Mode Address Local Address Transfer Byte Count Descriptor Pointer Channel Command/Status Register Local/DMA Arbitration Register Threshold Register
Channel Command/Status Register
12Ch 130h
©PLX Technology, Inc., 1997
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SECTION 4.2.5 Messaging Queue Registers
Table 4-9. Messaging Queue Registers
(Offset from Base Address) Local Access (Offset from Chip Select Address) 140h 144h 148h 14Ch 150h 154h 158h 15Ch 160h 164h 168h
9080
REGISTERS
ensure software compatibility with other versions 9080 family ensure compatibility with future enhancements, write zero unused bits.
PCI/Local Writable
EEPROM Writable
Outbound Post Queue Interrupt Status Outbound Post Queue Interrupt Mask Inbound Queue Port Outbound Queue Port Messaging Unit Configuration Register Queue Base Address Register Inbound Free Head Pointer Register Inbound Free Tail Pointer Register Inbound Post Head Pointer Register Inbound Post Tail Pointer Register Outbound Free Head Pointer Register Outbound Free Tail Pointer Register Outbound Post Head Pointer Register Outbound Post Tail Pointer Register Queue Status/Control Register
Note When messaging enabled (bit register Master (Host another IOP) uses Inbound Queue Port read MFAs from Inbound Free List FIFO write MFAs Inbound Post List FIFO. uses Outbound Queue Port read MFAs from Outbound Post List FIFO write MFAs Outbound Free List FIFO. Note Each Inbound Message Frame Address (MFA) specified offset from Base Address (programmed register PCIBAR0 offset 10H) start message frame. This means that inbound message frames should reside Base Address memory space. Note Each Outbound Message Frame Address (MFA) specified offset from system address 0x00000000h. Outbound physical address frame shared system memory. Note Inbound Outbound Queues reside Local Address Space programming register. They need shared memory.
©PLX Technology, Inc., 1997
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SECTION
9080
REGISTERS
CONFIGURATION REGISTERS
registers written read from byte, word long word accesses.
4.3.1 (PCIIDR; PCI:00h, LOC:00h) Configuration Register
Table 4-10. (PCIIDR; PCI:00h, LOC:00h) Configuration Register
Field 15:0 Description Vendor Identifies manufacturer device. Defaults issued vendor (10B5h) EEPROM present local initialization) asserted low. Device Identifies particular device. Defaults part number interface chip (PCI 9080) EEPROM present local initialization) asserted low. Read Write Local/ EEPROM Local/ EEPROM Value after Reset 10B5h 9080h
31:16
4.3.1.1 (PCICR; PCI:04h, LOC:04h) Command Register
Table 4-11. (PCICR; PCI:04h, LOC:04h) Command Register
Field Description Space. value allows device respond space accesses. value disables device from responding space accesses. Memory Space. value allows device respond memory space accesses. value disables device from responding memory space accesses. Master Enable. value allows device behave master. value disables device from generating master accesses. Special Cycle. (This supported.) Memory Write/Invalidate. (Refer Mode Registers (DMAMODE0, DMAMODE1) Palette Snoop. (This supported.) Parity Error Response. value indicates parity error ignored operation continues. value indicates parity checking enabled. Wait Cycle Control. Controls whether device does address/data stepping. value indicates device never does stepping. value indicates device always does stepping. Note: Hardcoded SERR# Enable. value enables SERR# driver. value disables driver. Fast Back-to-Back Enable. Indicates what type fast back-to-back transfers Master perform bus. value indicates fast back-to-back transfers occur agent bus. value indicates fast back-to-back transfers only occur same agent previous cycle. Reserved. Read Write Value after Reset
15:10
©PLX Technology, Inc., 1997
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9080
REGISTERS
4.3.2 (PCISR; PCI:06h, LOC:06h) Status Register
Table 4-12. (PCISR; PCI:06h, LOC:06h) Status Register
Field Description Reserved. high, supports User Definable Features. This only written from local side. read-only from side. Fast Back-to-Back Capable. When this indicates adapter accept fast back-to-back transactions. value indicates adapter cannot. Master Data Parity Error Detected. This when three conditions met: 9080 asserted PERR# itself observed PERR# asserted; 9080 master operation which error occurred; Parity Error Response Command Register set. Writing this clears (0). DEVSEL Timing. Indicates timing DEVSEL# assertion. value medium.) Target Abort. When this this indicates 9080 signaled target abort. Writing this clears (0). Received Target Abort. When this indicates 9080 received target abort signal. Writing this clears (0). Master Abort. When this indicates 9080 generated master abort signal. Writing this clears (0). Signaled System Error. When this indicates 9080 reported system error SERR# signal. Writing this clears (0). Detected Parity Error. When this indicates 9080 detected parity error, even parity error handling disabled (the Parity Error Response Command Register clear). three conditions cause this set. 9080 detected parity error during address phase; 9080 detected data parity error when target write; 9080 detected data parity error when performing master read operation. Writing this clears (0). Read Write Local Yes/Clr Value after Reset
10:9
Yes/Clr Yes/Clr Yes/Clr Yes/Clr Yes/Clr
4.3.3 (PCIREV; PCI:08h, LOC:08h) Revision Register
Table 4-13. (PCIREV; PCI:08h, LOC:08h) Revision Register
Field Description Revision silicon revision 9080. Read Write Local/ EEPROM Value after Reset Current
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9080
REGISTERS
4.3.4 (PCICCR; PCI:09-0Bh, LOC:09-0Bh) Class Code Register
Table 4-14. (PCICCR; PCI:09-0Bh, LOC:09-0Bh) Class Code Register
Field 15:8 23:16 Description Register Level Programming Interface. Queue Ports 44h. Subclass Code. Other Bridge Device, Device. Base Class Code. Bridge Device, Intelligent controller. Read Write Local/ EEPROM Local/ EEPROM Local/ EEPROM Value after Reset
4.3.5 (PCICLSR; PCI:0Ch, LOC:0Ch) Cache Line Size Register
Table 4-15. (PCICLSR; PCI:0Ch, LOC:0Ch) Cache Line Size Register
Field Description System cache line size units 32-bit words. Read Write Value after Reset
4.3.6 (PCILTR; PCI:0Dh, LOC:0Dh) Latency Timer Register
Table 4-16. (PCILTR; PCI:0Dh, LOC:0Dh) Latency Timer Register
Field Description Latency Timer. Specifies units clocks, amount time 9080, master, burst data bus. Read Write Value after Reset
©PLX Technology, Inc., 1997
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SECTION
9080
REGISTERS
4.3.7 (PCIHTR; PCI:0Eh, LOC:0Eh) Header Type Register
Table 4-17. (PCIHTR; PCI:0Eh, LOC:0Eh) Header Type Register
Field Description Configuration Layout Type. Specifies layout bits through configuration space. Only encoding defined. other encodings reserved. Header Type. value indicates multiple functions. value indicates single function. Read Write Local Local Value after Reset
4.3.8 (PCIBISTR; PCI:0Fh, LOC:0Fh) Built-In Self Test (BIST) Register
Table 4-18. (PCIBISTR; PCI:0Fh, LOC:0Fh) Built-In Self Test (BIST) Register
Field Description value indicates device passed test. Nonzero values indicate device failed. Device specific failure codes encoded nonzero value. Reserved. Device returns writes invoke BIST. Generates interrupt local bus. Local resets when BIST complete. Software should fail device BIST complete after seconds. Refer Runtime registers interrupt control/status. Returns device supports BIST. Returns device BIST compatible. Local Read Write Local Value after Reset
©PLX Technology, Inc., 1997
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SECTION
9080
REGISTERS
4.3.9 (PCIBAR0; PCI:10h, LOC:10h) Base Address Register Memory Accesses Local, Runtime, Registers
Table 4-19. (PCIBAR0; PCI:10h, LOC:10h) Base Address Register Memory Accesses Local, Runtime, Registers
Field Description Memory Space Indicator. value indicates register maps into memory space. value indicates register maps into space. Note: Hardcoded
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