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AS29F002

2 Megabit 5V CMOS Flash EEPROM Preliminary information Features

AS29F002
2 Megabit 5V CMOS Flash EEPROM Preliminary information Features
- One 16K two 8K one 32K and three 64K byte sectors - Boot code sector architecture-T (top) or B (bottom) - Erase any combination of sectors or full chip
· Low power consumption
- Automatically programs / verifies data at specified address
· JEDEC standard software, packages and pinouts
- 40-pin TSOP - 44-pin SO
· Detection of program / erase cycle completion
- DQ7 DATA polling - DQ6 toggle bit
· Automated on-chip erase algorithm
- Automatically preprograms / erases chip or specified sectors
· Erase suspend / resume
- Supports reading data from a sector not being erased
· 10, 000 write / erase cycle endurance · Hardware RESET pin
- Resets internal state machine to read mode
· Low VCC write lock-out below 3.2V
Logic block diagram
VCC VSS RESET Program / erase control Command register CE OE Program voltage generator Chip enable Output enable Logic STB Data latch Sector protect switches Erase voltage generator DQ0-DQ7
Pin arrangement
40-pin TSOP
A16 A15 A14 A13 A12 A11 A9 A8 WE RESET NC NC NC A7 A6 A5 A4 A3 A2 A1 NC RY / BY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE DQ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET WE A8 A9 A11 A12 A13 A14 A15 A16 A17 NC VSS A10 DQ7 NC DQ6 NC DQ5 NC DQ4 VCC
44-pin SO
Input / output buffers
Address latch
STB VCC detector Timer
Y decoder
Y gating
NC DQ1 NC DQ2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
X decoder
Cell matrix
NC DQ3 NC
A0-A17
A17 VSS NC NC A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 OE VSS CE A0
Selection guide
29F002-70 Maximum access time Maximum chip enable access time Maximum output enable access time tAA tCE tOE 70 70 30 29F002-90 90 90 35 29F002-120 120 120 50 Unit ns ns ns
ALLIANCE SEMICONDUCTOR
AS29F002
Functional description
AS29F002
Flexible sector architecture
Bottom boot sector architecture (AS29F002B) Sector 0 1 2 3 4 5 6 00000h-03FFFh 04000h-05FFFh 06000h-07FFFh 08000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh Size (Kbytes) 16 8 8 32 64 64 64 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-37FFFh 38000h-39FFFh 3A000h-3BFFFh 3C000h-3FFFFh Top boot sector architecture (AS29F002T) Size (Kbytes) 64 64 64 32 8 8 16
ID Sector address table
Operating modes
Mode ID read MFR code ID read part code Read Standby Output disable Write Enable sector protect Sector unprotect Verify sector protect Temporary sector unprotect Hardware reset CE L L L H L L L L L X X OE L L L X H H VID VID L X X WE H H H X H L Pulse / L Pulse / L H X X A0 L H A0 X X A0 L L L X X A1 L L A1 X X A1 H H H X X A6 L L A6 X X A6 L H L X X A9 VID VID A9 X X A9 VID VID VID X X RESET H H H H H H H H H VID L DQ Code Code DOUT HI-Z HI-Z DIN X X Code X HI-Z
AS29F002
Mode definitions
Output disable Part remains powered up but outputs disabled with OE pulled high.
Write
Enable sector protect Sector unprotect Verify sector protect
Temporary sector unprotect RESET Deep power down
READ codes
Mode MFG code (Alliance Semiconductor) Part code Sector protection
A17-A13 X Top boot Bottom boot X X sector address
Code 52h B0h 34h 01h protected 00h unprotected
AS29F002
Write operation status
Status In progress Exceeded time limits Auto programming Program / erase in auto erase Auto programming Program erase in auto erase DQ7 DQ7 0 DQ7 0 DQ6 Toggle Toggle Toggle Toggle DQ5 0 0 1 1 DQ3 0 1 1 1
Command definitions
Item Description Initiate read or reset operations by writing the Read / Reset command sequence into the command register. This allows the microprocessor to retrieve data from the memory. Device remains in read mode until command register contents are altered. Device automatically powers up in read / reset state. This feature allows only reads, therefore ensuring no spurious memory content alterations during power up. AS29F002 provides manufacturer and device codes in two ways. External PROM programmers typically access the device codes by driving +12V on A9. AS29F002 also contains an ID read command to read the device code with only +5V, since multiplexing +12V on address lines is generally undesirable. ID Read Initiate device ID read by writing the ID Read command sequence into the command register. Follow with a read sequence from address XX00h to return MFG code. Follow ID read command sequence with a read sequence from address XX01h to return device code. To verify write protect status on sectors, read address XX02. Sector addresses A17-A13 produce a 1 on DQ0 for protected sector and a 0 for unprotected sector. Exit from ID read mode with Read / Reset command sequence. Holding RESET low for 500 ns resets the device, terminating any operation in progress data handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is driven low. After RESET is set high, there is a delay of 1.5 µs for the device to permit read operations.
Reset / Read
Hardware reset
AS29F002
Byte programming
Chip Erase
Sector Erase
AS29F002
Erase Suspend
AS29F002 takes 0.1-15 µs to suspend erase operations after receiving Erase Suspend command. Check completion of erase suspend by polling DQ7 and / or DQ6. AS29F002 ignores redundant writes of erase suspend. AS29F002 defaults to erase-suspend-read mode while an erase operation has been suspended. While in erase-suspend-read mode AS29F002 allows reading data in any sector not undergoing sector erase, treated as standard read mode. Write the Resume command 30h to continue operation of sector erase. AS29F002 ignores redundant writes of the Resume command. AS29F002 permits multiple suspend / resume operations during sector erase.
Sector Protect Status operations
Data polling (DQ7)
Toggle bit (DQ6)
Exceeding time limit (DQ5)
AS29F002
Command format
Required 1st bus write cycle 2nd bus write cycle 3rd bus write cycle Command sequence bus cycles Address Data Address Data Address Data
4th bus write cycle Address Data
5th bus write cycle Address Data
6th bus write cycle Address Data
AS29F002
Automated on-chip programming algorithm
Write program command sequence (see below)
Automated on-chip erase algorithm
Write erase command sequence (see below)
Data polling or toggle bit successfully completed Data poll device Erase complete Chip erase command sequence (address / command): 5555h / AAh YES Programming completed 2AAAh / 55h 2AAAh / 55h Sector erase command sequence (address / command): 5555h / AAh
Program command sequence (address / command): 5555h / AAh
5555h / 80h
5555h / AAh
2AAAh / 55h 2AAAh / 55h 2AAAh / 55h
5555h / A0h
5555h / 10h
Sector address / 30h
Program address / program data Optional multiple sector erase commands
Sector address / 30h
The system software should check the status of DQ3 prior to and following each subsequent sector erase command to ensure command completion. The device may not have accepted the command if DQ3 is high on second status check.
AS29F002
Data polling algorithm
Toggle bit algorithm
YES DONE
AS29F002
DC electrical characteristics
Parameter Input load current A9 Input load current Output leakage current Output short circuit current
Active current, read @ 6MHz Standby current Deep power down Input low voltage Input high voltage Output low voltage Output high level Low VCC lock out voltage Input HV select voltage
Active current, program / erase
Maximum negative overshoot waveform
+0.8V -0.5V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
-2.0V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Maximum positive overshoot waveform
VCC+2.0V VCC+0.5V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +2.0V 20 ns 20 ns
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AS29F002
AC parameters: read cycle
JEDEC Symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tPHQV -70 Std Symbol tRC tACC tCE tOE tDF tDF tOH tPWH Parameter Read cycle time Address to output delay Chip enable to output Output enable to output Chip enable to output HI-Z Output enable to output HI-Z Output hold time from addresses, first occurrence of CE or OE RESET high to output delay Min 70 Max 70 70 30 20 20 0 1.5 Min 90 -90 Max 90 90 35 20 20 0 1.5 Min 120 -120 Max 120 120 50 30 30 0 1.5 Unit ns ns ns ns ns ns ns µs
Key to switching waveforms
AAAAAAA AAAAAAA AAAAAAA
Rising input
AAAAAAA AAAAAAA AAAAAAA
Falling input
AAAAAAA AAAAAAA AAAAAAA
Read waveform
tRC Addresses
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
Addresses stable tACC
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
CE tDF tOE OE tOEH
WE tCE Outputs HI-Z
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Output valid AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tPWH RESET
AS29F002
AC parameters - write cycle
JEDEC Symbol tAVAV tAVWL tWLAX tDVWH tWHDX Std Symbol tWC tAS tAH tDS tDH tOES tOEH tREADY tRP tGHWL tELWL tWHEH tWLWH tWHWL tGHWL tCS tCH tWP tWPH -70 Parameter Write cycle time Address setup time Address hold time Data setup time Data hold time Output enable setup time Output enable hold time: Read Output enable hold time: Toggle and data polling RESET pin low to read mode RESET Read recover time before write CE setup time CE hold time Write pulse width Write pulse width high Byte Min 70 0 45 30 0 0 0 10 20 500 0 0 0 35 20 50
WE controlled -90 Max -
-120 Max -
Unit ns ns ns ns ns ns ns ns µs ns ns ns ns ns ns µs
tWHWH1 tWHWH1 Programming pulse time tWHWH2 tWHWH2 Erase pulse time
Write waveform
3rd bus cycle tWC Addresses 5555H tCH CE tGHWL OE tWP WE tCS tWPH tDH PD tDS DQ7 DOUT tWHWH1 or 2 tAS PA tAH
AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA
WE controlled
AS29F002
AC parameters-write cycle 2
JEDEC Symbol tAVAV tAVEL tELAX tDVEH tEHDX Std Symbol tWC tAS tAH tDS tDH tOES tOEH tGHEL tWLEL tEHWH tELEH tEHEL tGHEL tWS tWH tCP tCPH -70 Parameter Write cycle time Address setup time Address hold time Data setup time Data hold time Output enable setup time Output enable hold time: Read Output enable hold time: Toggle and data polling Read recover time before write WE setup time WE hold time CE pulse width CE pulse width high Min 70 0 45 30 0 0 0 10 0 0 0 35 20 50 0.3 Max Min 90 0 45 45 0 0 0 10 0 0 0 45 20 50 0.3 -90 Max Min 120 0 50 50 0 0 0 10 0 0 0 50 20 50 0.3 -120
CE controlled Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns µs
tWHWH1 tWHWH1 Programming pulse time tWHWH2 tWHWH2 Erase pulse time
Write waveform 2
Addresses 5555H tWC WE tGHEL OE tCP CE tCPH tDH DATA A0H tDS Data DQ7 DOUT tWHWH1 or 2 PA tAS tAH
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
CE controlled
Data polling PA
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
AS29F002
Erase waveform
tWC Addresses
5555H
2AAAH 5555H 5555H 2AAAH Sector address
tAH CE tGHWL OE tWP WE tCS Data tDS
tWC tWPH tDH
55H 80H AAH 55H 10H for Chip Erase 30H
RESET waveform
RESET tRP tReady CE
DATA polling waveform
CE tCH tOE OE tOEH WE tCE Input DQ7
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tOH Output DQ7 Output
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tWHWH1 or 2
AS29F002
Toggle bit waveform
CE tOEH WE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Erase and programming performance
Limits Parameter Sector erase and verify-1 time (excludes 00h programming prior to erase) Byte program time Chip programming time Erase program cycles Min
Typ 1.6 120 120 -
Max 15 5200 240 10, 000
Unit sec µs sec cycles
AS29F002
AC test conditions
+3.3V 1N3064 or equivalent Device under Test 100 pF 6.2K 1N3064 or equivalent VSS VSS 2.7K
VSS including scope and jig capacitance
Recommended operating conditions
Parameter Supply voltage Input voltage Symbol VCC VSS VIH VIL Min +4.5 0 2.0 -0.5 Typ 5.0 0 -
Absolute maximum ratings
Parameter Input voltage (Input or DQ pin) Input voltage (A9 pin), OE, RESET Power supply voltage Operating temperature Storage temperature (plastic) Short circuit output current Symbol VIN VIN VCC TOPR TSTG IOUT Min -2.0 -2.0 -0.5 -55 -65 Max +7.0 +13.0 +5.5 +125 +150 200 Unit V V V °C °C mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
AS29F002
Latchup characteristics
Parameter Input voltage with respect to VSS on A9, OE, and RESET pin Input voltage with respect to VSS on all DQ, address and control pins Current
Min -1.0 -1.0 -100
Max +13.0 VCC+1.0 +100
TSOP pin capacitance
SO pin capacitance
Data retention
Parameter Minimum pattern data retention time Temp. 150° 125° Min 10 20 Unit years years
AS29F002
Package dimensions
40-pin TSOP min (mm) max (mm) a h f b c d e f g i a h i .05 0.120 0.30 18.20 19.80 9.8 0.96 0.134 0.35
40-pin TSOP
44-pin SO
44-pin SO min (mm) max (mm) 28.00 28.40 0.35 0.50 0.10 0.35 2.17 2.45 2.80 1.27 13.10 13.50 15.70 16.30 0.06 1.00 0.10 0.21
AS29F002
Ordering codes
Part numbering system
Representatives, distributors and sales offices
DOMESTIC REPS
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