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AS29F002 Megabit CMOS Flash EEPROM Preliminary information Featur


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High Performance CMOS Flash EEPROM
AS29F002
Megabit CMOS Flash EEPROM Preliminary information Features
Organization: Sector architecture
16K; 32K; three byte sectors Boot code sector architecture-T (top) (bottom) Erase combination sectors full chip
power consumption
maximum read current maximum program current maximum standby current standby current (RESET
Single 5.0±0.5V power supply read/write operations Sector protection High speed 70/90/120 address access time Automated on-chip programming algorithm
Automatically programs/verifies data specified address
JEDEC standard software, packages pinouts
40-pin TSOP 44-pin
Detection program/erase cycle completion
DATA polling toggle
Automated on-chip erase algorithm
Automatically preprograms/erases chip specified sectors
Erase suspend/resume
Supports reading data from sector being erased
10,000 write/erase cycle endurance Hardware RESET
Resets internal state machine read mode
write lock-out below 3.2V
Logic block diagram
RESET Program/erase control Command register Program voltage generator Chip enable Output enable Logic Data latch Sector protect switches Erase voltage generator DQ0-DQ7
arrangement
40-pin TSOP
RESET RY/BY RESET
44-pin
Input/output buffers
Address latch
detector Timer
decoder
gating
decoder
Cell matrix
A0-A17
Selection guide
29F002-70 Maximum access time Maximum chip enable access time Maximum output enable access time 29F002-90 29F002-120 Unit
ALLIANCE SEMICONDUCTOR
AS29F002
Functional description
AS29F002 megabit, volt only Flash memory organized 256K bytes bits each. flexible erase program capability, megabits data divided into sectors: byte, byte, byte, three bytes. data appears DQ0- DQ7. AS29F002 offered JEDEC standard 40-pin TSOP 44-pin packages. This device designed programmed erased in-sytem with single 5.0V supply. device also reprogrammed standard EPROM programmers. AS29F002 offers access times 70/90/120 allowing 0-wait state operation high speed microprocessors. eliminate contention device separate chip enable (CE), write enable (WE), output enable (OE) controls. AS29F002 fully compatible with JEDEC single power supply Flash standard. Write commands command register using standard microprocessor write timings. internal state-machine uses register contents control erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Read data from device same manner other Flash EPROM devices. program command sequence invoke automated on-chip programming algorithm that automatically times program pulse widths verifies proper cell margin. erase command sequence invoke automated on-chip erase algorithm that preprograms sector already programmed before executing erase operation, times erase pulse widths, verifies proper cell margin. Boot sector architecture enables device boot from either (AS29F002T) bottom (AS29F002B) sector. Sector erase architecture allows specified sectors memory erased reprogrammed without altering data other sectors. sector typically erases verifies within seconds. Hardware sector protection disables both program erase operations combination seven sectors. device provides background erase with Erase Suspend, which puts erase operations hold read data from sector that being erased. chip erase command will automatically erase unprotected sectors. factory shipped AS29F002 fully erased (all bits programming operation sets bits Data programmed into array byte time sequence across sector boundaries. sector must erased change bits from Erase returns bytes sector erased state (all bits Each sector erased individually with effect other sectors. device features single 5.0V power supply operation both read write functions. Internally generated regulated voltages provided program erase operations. detector automatically inhibits write operations during power transtitions. DATA polling toggle (DQ6) used detect program erase operations. device automatically resets read mode after program/erase operations completed. AS29F002 resists accidental erasure spurious programming signals resulting from power transitions. Control register architecture permits alteration memory contents only after successful completion specific command sequences. During power device read mode with program/erase commands disabled when less than VLKO (lockout voltage). command registers affected noise pulses less than must logical zero logical initiate write commands. When device's hardware RESET driven low, program/erase operation progress will terminated internal state machine will reset read mode. RESET tied system reset circuitry system reset occurs during automated onchip program/erase algorithm, data address locations being operated will become corrupted require rewriting. Resetting device enables system's microprocessor read boot-up firmware from Flash memory. AS29F002 uses Fowler-Nordheim tunnelling electrically erase bits within sector simultaneously. Bytes programmed time using EPROM programming mechanism electron injection.
AS29F002
Flexible sector architecture
Bottom boot sector architecture (AS29F002B) Sector 00000h-03FFFh 04000h-05FFFh 06000h-07FFFh 08000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh Size (Kbytes) 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-37FFFh 38000h-39FFFh 3A000h-3BFFFh 3C000h-3FFFFh boot sector architecture (AS29F002T) Size (Kbytes)
Sector address table
Bottom boot sector address (AS29F002B) Sector boot sector address (AS29F002T)
Operating modes
Mode read code read part code Read Standby Output disable Write Enable sector protect Sector unprotect Verify sector protect Temporary sector unprotect Hardware reset Pulse/L Pulse/L RESET Code Code DOUT HI-Z HI-Z Code HI-Z
(<VIL); High (>VIH 12.0 0.5V; Don't care.
AS29F002
Mode definitions
Item code, part code Read mode Standby Description Selected VID(11.5-12.5V), enabling outputs. When (VIL) output data 52h, unique Mfr. code Alliance Semiconductor Flash products. When high (VIH), DOUT represents part code 29F002. Selected with Data valid tACC time after addresses stable, after after low. Selected with Part powered down, reduced <1.0 input levels. activated during automated on-chip algorithm, device completes operation before entering standby. Selected with Accomplish Flash erasure programming through command register. Contents command register serve inputs internal state machine. Address latching occurs falling edge whichever occurs later; data latching occurs rising edge that occurs first. Filters line prevent spurious noise events from appearing write commands. Hardware protection circuitry implemented with external programming equipment causes device disable program erase operations specified sectors. Erases sector protection using external programming equipment. Verifies write protection sector. Sectors protected from program/erase operations commercial programming equipment. Determine sector protection exists system writing read command sequence location xx02h, where address bits A13-17 select defined sector addresses. logical indicates protected sector; logical indicates unprotected sector. Temporarily disables sector protection in-system data changes protected sectors. Apply +12V RESET activate sector unprotect mode. During sector unprotect mode, program protected sectors selecting appropriate sector address. protected sectors revert protected state removal +12V from RESET. Resets write erase state machine read mode. device programming erasing when RESET data corrupted. Hold RESET enter deep power down mode (<10 CMOS). Recovery time active mode
Output disable Part remains powered outputs disabled with pulled high.
Write
Enable sector protect Sector unprotect Verify sector protect
Temporary sector unprotect RESET Deep power down
READ codes
Mode code (Alliance Semiconductor) Part code Sector protection
Key: =Low High (>VIH); =Don't care.
A17-A13 boot Bottom boot sector address
Code protected unprotected
AS29F002
Write operation status
Status progress Exceeded time limits Auto programming Program/erase auto erase Auto programming Program erase auto erase Toggle Toggle Toggle Toggle
Command definitions
Item Description Initiate read reset operations writing Read/Reset command sequence into command register. This allows microprocessor retrieve data from memory. Device remains read mode until command register contents altered. Device automatically powers read/reset state. This feature allows only reads, therefore ensuring spurious memory content alterations during power AS29F002 provides manufacturer device codes ways. External PROM programmers typically access device codes driving +12V AS29F002 also contains read command read device code with only +5V, since multiplexing +12V address lines generally undesirable. Read Initiate device read writing Read command sequence into command register. Follow with read sequence from address XX00h return code. Follow read command sequence with read sequence from address XX01h return device code. verify write protect status sectors, read address XX02. Sector addresses A17-A13 produce protected sector unprotected sector. Exit from read mode with Read/Reset command sequence. Holding RESET resets device, terminating operation progress; data handled operation corrupted. internal state machine resets after RESET driven low. After RESET high, there delay device permit read operations.
Reset/Read
Hardware reset
AS29F002
Item
Description Programming AS29F002 four cycle operation performed byte-by-byte basis. unlock write cycles precede Program Setup command program data write cycle. Upon execution program command, additional controls timings necessary. Addresses latched falling edge (whichever last); data latched rising edge (whichever first). AS29F002's automated on-chip program algorithm provides adequate internally-generated programming pulses verifies programmed cell margin. Check programming status sampling data DATA polling (DQ7) toggle (DQ6). AS29F002 returns equivalent data that written opposed complemented data), complete programming operation. AS29F002 ignores commands written during programming. hardware reset occurring during programming corrupt data programmed location. AS29F002 allows programming sequence across sector boundary. Changing data from requires erase operation. Attempting program data results either (exceeded programming time limits) success according data polling; reading this data after Read/reset operation returns When programming time limit exceeded, reads high, continues toggle. this state, reset command returns device read mode. Chip erase requires cycles: unlock write cycles; setup command, additional unlock write cycles; finally Chip Erase command.
Byte programming
Chip Erase
Chip erase does require logical written prior erasure. When automated on-chip erase algorithm invoked with Chip Erase command sequence, AS29F002 automatically programs verifies entire memory array all-zero pattern prior erase. AS29F002 returns read mode upon completion chip erase unless high result exceeding time limit. Sector erase requires cycles: unlock write cycles, setup command, additional unlock write cycles, finally Sector Erase command. Determine sector erased addressing location sector. This address latched falling edge command, latched rising edge sector erase operation begins after time-out. erase multiple sectors, write sector erase command each addresses sectors erase after following cycle operation above. Timing between writes additional sectors must AS29F002 ignores command erasure begins. During time-out period falling edge resets time-out. command (other than Sector Erase Erase Suspend) during time-out resets AS29F002 read mode, device ignores sector erase command string. Erase such ignored sectors restarting Sector Erase command ignored sectors. entire array need written with prior erasure. AS29F002 writes entire sector prior electrical erase; writing affects only selected sectors, leaving non-selected sectors unaffected. AS29F002 requires control timing signals during sector erase operations. Automatic sector erase begins after time-out from last rising edge from sector erase command stream ends when DATA polling (DQ7) logical DATA polling address must performed addresses that fall within sectors being erased. AS29F002 returns read mode after sector erase unless high exceeding time limit.
Sector Erase
AS29F002
Item
Description Erase suspend allows interruption sector erase operations perform data reads from sector being erased. Erase suspend applies only during sector erase operations, including timeout period. Writing Erase Suspend command during sector erase time-out results immediate termination time-out period suspension erase operation. AS29F002 ignores commands during erase suspend other than Erase Resume command. Writing erase resume continues erase operations. Addresses DON'T CARE when writing Erase Suspend Erase Resume commands.
Erase Suspend
AS29F002 takes 0.1-15 suspend erase operations after receiving Erase Suspend command. Check completion erase suspend polling and/or DQ6. AS29F002 ignores redundant writes erase suspend. AS29F002 defaults erase-suspend-read mode while erase operation been suspended. While erase-suspend-read mode AS29F002 allows reading data sector undergoing sector erase, treated standard read mode. Write Resume command continue operation sector erase. AS29F002 ignores redundant writes Resume command. AS29F002 permits multiple suspend/resume operations during sector erase.
Sector Protect Status operations
When attempting write protected sector, DATA polling activated When attempting erase protected sector, Toggle activated about both cases, device returns read mode without altering specified sectors. Only active during automated on-chip algorithms sector erase time outs. reflects complement data last written when read during automated on-chip algorithm during erase algorithm); reflects true data when read after completion automated on-chip algorithm after completion erase agorithm). Active during automated on-chip algorithms sector time outs. toggles when toggles, Erase Resume command invoked. valid after rising edge fourth pulse during programming; after rising edge sixth pulse during chip erase; after last rising edge sector erase pulse sector erase. protected sectors, toggles only during writes, during erase selected sectors protected); both cases, data unaffected. Indicates unsuccessful completion program/erase operation (DQ5 Data polling remains active; powers device down during chip erase, some sectors defective; during byte programming, entire sector defective; during sector erase, sector defective this case, reset device execute program erase command sequence continue working with functional sectors). Attempting program will
Data polling (DQ7)
Toggle (DQ6)
Exceeding time limit (DQ5)
Checks whether sector erase timer window open. erase progress; Sector erase timer (DQ3) commands will accepted. device will accept sector erase commands. Check before after each sector erase command verify that command accepted.
AS29F002
Command format
Required write cycle write cycle write cycle Command sequence cycles Address Data Address Data Address Data
Reset/read Reset/read Autoselect read boot bottom boot 5555h 2AAAh 5555h XXX02h Program Chip erase Sector erase Sector erase suspend Sector erase resume 5555h 5555h 5555h XXXXh XXXh 2AAAh 2AAAh 2AAAh 5555h 5555h 5555h Program address 5555h 5555h protected unprotected Program data 2AAAh 2AAAh 5555h Sector address XXXXh 5555h 2AAAh 5555h Read address Read data
write cycle Address Data
write cycle Address Data
write cycle Address Data
operations defined "Mode definitions," page Reading from non-erasing sectors allowed Erase Suspend mode. Address A12-A17 Don't care address commands except Program Address Sector Address. System should generate address patterns: 5555h 2AAAh address A0-A11. sector protect verify sector selected A17-A13.
AS29F002
Automated on-chip programming algorithm
Write program command sequence (see below)
Automated on-chip erase algorithm
Write erase command sequence (see below)
Data polling toggle successfully completed Data poll device Erase complete Chip erase command sequence (address/command): 5555h/AAh Programming completed 2AAAh/55h 2AAAh/55h Sector erase command sequence (address/command): 5555h/AAh
Verify byte?
Program command sequence (address/command): 5555h/AAh
5555h/80h
5555h/80h
5555h/AAh
5555h/AAh
2AAAh/55h 2AAAh/55h 2AAAh/55h
5555h/A0h
5555h/10h
Sector address/30h
Program address/program data Optional multiple sector erase commands
Sector address/30h
Sector address/30h
system software should check status prior following each subsequent sector erase command ensure command completion. device have accepted command high second status check.
AS29F002
Data polling algorithm
Read byte (DQ0-DQ7) Address
Toggle algorithm
Read byte (DQ0-DQ7) Address don't care
data
DONE
toggle
DONE
Read byte (DQ0-DQ7) Address
Read byte (DQ0-DQ7) Address don't care
data FAIL
DONE
toggle FAIL
DONE
Byte address programming. sector addresses within sector being erased during Sector Erase. valid address equals non-protected sector group address during Chip Erase. rechecked even because change simultaneously.
rechecked even because stop toggling when changes
AS29F002
electrical characteristics
Parameter Input load current Input load current Output leakage current Output short circuit current
5.0±0.5V, +70°C Symbol ICC2 ISB1 ISB2 VOH1 VOH2 VLKO 5.8mA, -2.5 -100 Test Conditions VCC, VCCMAX VCCMAX, 12.5V VOUT VCC, VCCMAX VOUT 0.5V VIL, VIL, VIH, VCCMAX -0.5 11.5 0.45 12.5 Unit
Active current, read 6MHz Standby current Deep power down Input voltage Input high voltage Output voltage Output high level lock voltage Input select voltage
Active current, program/erase
more than output tested simultaneously. Duration short circuit must second. VOUT 0.5V selected avoid test problems caused tester ground degradation. (This parameter sampled 100% tested, guaranteed characterization.) current listed includes both operating current frequency dependent component MHz). frequency component typically less than mA/MHz with active while program erase operations progress.
Maximum negative overshoot waveform
+0.8V -0.5V
-2.0V
Maximum positive overshoot waveform
VCC+2.0V VCC+0.5V +2.0V
AS29F002
parameters: read cycle
JEDEC Symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tPHQV Symbol tACC tPWH Parameter Read cycle time Address output delay Chip enable output Output enable output Chip enable output HI-Z Output enable output HI-Z Output hold time from addresses, first occurrence RESET high output delay -120 Unit
switching waveforms
AAAAAAA AAAAAAA AAAAAAA
Rising input
AAAAAAA AAAAAAA AAAAAAA
Falling input
AAAAAAA AAAAAAA AAAAAAA
Undefined output/don't care
Read waveform
Addresses
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
Addresses stable tACC
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tOEH
Outputs HI-Z
Output valid
HI-Z
tPWH RESET
AS29F002
parameters write cycle
JEDEC Symbol tAVAV tAVWL tWLAX tDVWH tWHDX Symbol tOES tOEH tREADY tGHWL tELWL tWHEH tWLWH tWHWL tGHWL tWPH Parameter Write cycle time Address setup time Address hold time Data setup time Data hold time Output enable setup time Output enable hold time: Read Output enable hold time: Toggle data polling RESET read mode RESET Read recover time before write setup time hold time Write pulse width Write pulse width high Byte
controlled
-120
Unit
tWHWH1 tWHWH1 Programming pulse time tWHWH2 tWHWH2 Erase pulse time
Write waveform
cycle Addresses 5555H tGHWL tWPH DOUT tWHWH1
AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA
controlled
DATA
AS29F002
parameters-write cycle
JEDEC Symbol tAVAV tAVEL tELAX tDVEH tEHDX Symbol tOES tOEH tGHEL tWLEL tEHWH tELEH tEHEL tGHEL tCPH Parameter Write cycle time Address setup time Address hold time Data setup time Data hold time Output enable setup time Output enable hold time: Read Output enable hold time: Toggle data polling Read recover time before write setup time hold time pulse width pulse width high -120
controlled Unit
tWHWH1 tWHWH1 Programming pulse time tWHWH2 tWHWH2 Erase pulse time
Write waveform
Addresses 5555H tGHEL tCPH DATA Data DOUT tWHWH1
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
controlled
Data polling
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
AS29F002
Erase waveform
Addresses
5555H
mode only
2AAAH 5555H 5555H 2AAAH Sector address
tGHWL Data
tWPH
Chip Erase
RESET waveform
RESET tReady
DATA polling waveform
tOEH Input
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
Output Output
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
HI-Z
tWHWH1
AS29F002
Toggle waveform
tOEH
AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Erase programming performance
Limits Parameter Sector erase verify-1 time (excludes programming prior erase) Byte program time Chip programming time Erase program cycles
5200 10,000
Unit cycles
AS29F002
test conditions
+3.3V 1N3064 equivalent Device under Test 6.2K 1N3064 equivalent 2.7K
*including scope capacitance
Recommended operating conditions
Parameter Supply voltage Input voltage Symbol +4.5 -0.5
+70°C +5.5 Unit
Absolute maximum ratings
Parameter Input voltage (Input pin) Input voltage pin), RESET Power supply voltage Operating temperature Storage temperature (plastic) Short circuit output current Symbol TOPR TSTG IOUT -2.0 -2.0 -0.5 +7.0 +13.0 +5.5 +125 +150 Unit
Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
AS29F002
Latchup characteristics
Parameter Input voltage with respect RESET Input voltage with respect address control pins Current
Includes pins except VCC. Test conditions: 5.0V, time.
-1.0 -1.0 -100
+13.0 VCC+1.0 +100
Unit
TSOP capacitance
Symbol COUT CIN2 Parameter Input capacitance Output capacitance Control capacitance Test Setup VOUT Unit
capacitance
Symbol COUT CIN2 Parameter Input capacitance Output capacitance Control capacitance Test Setup VOUT Unit
Data retention
Parameter Minimum pattern data retention time Temp. 150° 125° Unit years years
AS29F002
Package dimensions
40-pin TSOP (mm) (mm) 0.120 0.30 18.20 19.80 0.96 0.134 0.35
40-pin TSOP
18.60
20.20 10.2 1.02 0.05
0-5°
0-8°
44-pin
44-pin (mm) (mm) 28.00 28.40 0.35 0.50 0.10 0.35 2.17 2.45 2.80 1.27 13.10 13.50 15.70 16.30 0.06 1.00 0.10 0.21
AS29F002
Ordering codes
Package Access Time TSOP, 40-pin AS29F002T-70TC AS29F002B-70SC package available (44-pin) AS29F002T-70SC AS29F002T-90SC AS29F002T-120SC AS29F002T-90TC AS29F002B-90SC AS29F002T-120TC AS29F002B-120SC AS29F002B-70TC AS29F002B-90TC AS29F002B-120TC
Part numbering system
AS29F Flash EEPROM prefix Device number (bottom) (top) boot block -XXX Address access time Package: TSOP Commercial temperature range,
Representatives, distributors sales offices
DOMESTIC REPS
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DISTRIBUTORS
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SALES OFFICES
HEADQUARTERS Alliance Semiconductor Jose, (408) 383-4900 NORTHEAST AREA Alliance Semiconductor Boston, (617) 239-8127
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INTERNATIONAL REPS
AUSTRALIA
TOKYO
Bussan Micro Electronics +81-3-5421-1730
WEST
(816) 358-8100 MISSISSIPPI Concord Component (205) 772-8883 MONTANA ES/Chase (503) 684-8500 NEBRASKA CenTech (816) 358-8100 NEVADA Brooks Technical (415) 960-3880 HAMPSHIRE Kitchen Kutchin (617) 229-2660
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KYOTO
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Alliance Semiconductor reserves right make changes this data sheet time improve design supply best product possible. Publication advance information does constitute committment produce supply product described. company cannot assume responsibility circuits shown represent that they free from patent infringement. Alliance products authorized critical components life support devices systems without express written approval president Alliance. ProMotion® Alliance logo registered trademarks Alliance Semiconductor Corporation. other trademarks property their respective holders.
3099 North First Street Printed U.S.A.
ALLIANCE SEMICONDUCTOR
Jose, 95134 (408) 383-4900 Copyright 1996 rights reserved.
(408) 383-4999 June 1996

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