High Temperature, Volt, Byte Alterable E2PROM 128K FEATURES
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X28ST010
High Temperature, Volt, Byte Alterable E2PROM
128K
FEATURES 185°C Full Functionality Simple Byte Page Write -Single Supply -Self-Timed Erase Before Write Complex Programming Algorithms Overerase Problem Highly Reliable Direct WriteCell -Endurance: 10,000 Write Cycles -Data Retention: Years -Higher Temperature Functionality Possible Operating Byte Mode.
Xicor X28ST010 128K E2PROM, fabricated with Xicor's proprietary, high performance, floating gate CMOS technology which provides Xicor products superior high temperature performance characteristics. Like Xicor programmable non-volatile memories X28ST010 only device. X28ST010 features JEDEC approved pinout byte-wide memories, compatible with industry standard EPROMs. X28ST010 supports 256-byte page write operation, effectively providing 19µs/byte write cycle enabling entire memory typically written less than seconds. Xicor E2PROMs designed tested applications requiring extended endurance. Data retention specified greater than years.
CONFIGURATIONS
FLAT PACK CERDIP SOIC X28ST010
I/O0 I/O2 I/O3 I/O5 I/O6 I/O1 I/O4 I/O7
X28ST010
TTOMVIEW)
6613-1.4 04-01-98 T1/C2/D2
Characteristics subject change without notice
X28ST010
DESCRIPTIONS Addresses (A0-A16) Address inputs select 8-bit memory location during read write operation. Chip Enable (CE) Chip Enable input must enable read/ write operations. When HIGH, power consumption reduced. Output Enable (OE) Output Enable input controls data output buffers used initiate read operations. Data In/Data (I/O0-I/O7) Data written read from X28ST010 through pins. Write Enable (WE) Write Enable input controls writing data X28ST010. Back Bias Voltage (VBB) required provide pin. This negative voltage improves higher temperature functionality. FUNCTIONAL DIAGRAM NAMES Symbol
A0-A16 I/O0-I/O7
Description
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable Ground Connect
-A16
BUFFERS LATCHES DECODER
1M-BIT 2PROM ARRAY
0-A7
BUFFERS LATCHES DECODER
BUFFERS LATCHES
0-I/O7 DATA INPUTS/OUTPUTS CONTROL LOGIC TIMING
X28ST010
DEVICE OPERATION Read Read operations initiated both LOW. read operation terminated either returning HIGH. This line control architecture eliminates contention system environment. data will high impedance state when either HIGH. Write Write operations initiated when both HIGH. X28ST010 supports both controlled write cycle. That address latched falling edge either whichever occurs last. Similarly, data latched internally rising edge either whichever occurs first. byte write operation, once initiated, will automatically continue completion, typically within 5ms. Page Write Operation page write feature X28ST010 allows entire memory written seconds. Page write allows hundred fifty-six bytes data consecutively written X28ST010 prior commencement internal programming cycle. host fetch data from another device within system during page write operation (change source address), page address through A16) each subsequent valid write cycle part during this operation must same initial page address. page write mode initiated during write operation. Following initial byte write cycle, host write additional hundred fifty-six bytes same manner first byte written. Each successive byte load cycle, started HIGH transition, must begin within 100µs falling edge preceding subsequent HIGH transition detected within 100µs, internal automatic programming cycle will commence. There page write window limitation. Effectively page write window infinitely wide, long host continues access device within byte load cycle time 100µs. HARDWARE DATA PROTECTION X28ST010 provides three hardware features that protect nonvolatile data from inadvertent writes. Noise Protection-A pulse less than 10ns will initiate write cycle. Default Sense-All functions inhibited when 3.4V. Write inhibit-Holding either LOW, HIGH, HIGH will prevent inadvertent write cycle during power-up power-down, maintaining data integrity. SYSTEM CONSIDERATIONS Because X28ST010 frequently used large memory arrays provided with line control architecture both read write operations. Proper usage provide lowest possible power dissipation eliminate possibility contention where multiple pins share same bus. been demonstrated that markedly higher temperature performance obtained from this device left enabled throughout read write operation. gain most benefit recommended that decoded from address used primary device selection input. Both would then common among devices array. read operation this assures that deselected devices their standby mode that only selected device(s) outputting data bus. Because X28ST010 power modes, standby active, proper decoupling memory array prime concern. Enabling will cause transient current spikes. magnitude these spikes dependent output capacitive loading I/Os. Therefore, larger array sharing common bus, larger transient spikes. voltage peaks associated with current transients suppressed proper selection placement decoupling capacitors. minimum, recommended that 0.1µF high frequency ceramic capacitor used between each device. Depending size array, value capacitor have larger. addition, recommended that 4.7µF electrolytic bulk capacitor placed between each eight devices employed array. This bulk capacitor employed overcome voltage droop caused inductive effects board traces.
X28ST010
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias X28ST010 .-55°C +185°C Voltage with Respect D.C. Output Current .5mA Lead Temperature (Soldering, seconds) 300°C *COMMENT Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMEND OPERATING CONDITIONS Temperature
High Temp.
Min.
Max.
+185°C
Supply Voltages
X28ST010 Back Bias Voltage:
Limits
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.) Limits Symbol
Parameter
Current (Active) (TTL Inputs) Current (Standby) (TTL Inputs) Input Leakage Current Output Leakage Current Input Voltage Input HIGH Voltage Output Voltage Output HIGH Voltage Back Bias Current
Min.
Max.
Units
Test Conditions
VIL, VIH, I/O's Open, Address Inputs .4V/2.4V Levels 5MHz VIH, I/O's Open, Other Inputs VOUT VCC,
ISB1 VlL(1) VIH(1)
-400µA ±10%
Notes: min. max. reference only tested.
X28ST010
POWER-UP TIMING Symbol
tPUR(2) tPUW(2)
Parameter
Power-up Read Operation Power-up Write Operation
Max.
Units
CAPACITANCE +25°C, 1MHz, Symbol
CI/O(2) CIN(2)
Parameter
Input/Output Capacitance Input Capacitance
Max.
Units
Test Conditions
VI/O
ENDURANCE DATA RETENTION Parameter
Endurance Data Retention
Min.
10,000
Max.
Units
Cycles Byte Years
A.C. CONDITIONS TEST
Input Pulse Levels Input Rise Fall Times Input Output Timing Levels 10ns 1.5V
MODE SELECTION
Mode
Read Write Standby Write Inhibit Write Inhibit Write Inhibit
DOUT High
Power
Active Active Standby
EQUIVALENT A.C. LOAD CIRCUIT
SYMBOL TABLE
WAVEFORM INPUTS Must steady OUTPUTS Will steady Will change from HIGH Will change from HIGH Changing: State Known Center Line High Impedance
1.92K OUTPUT 1.37K 100pF
change from HIGH change from HIGH Don't Care: Changes Allowed
Notes: This parameter periodically sampled 100% tested.
X28ST010
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.) Read Cycle Limits X28ST010-20 Symbol
X28ST010-25 Min.
Parameter
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output HIGH High Output HIGH High Output Output Hold from Address Change
Min.
Max.
Max.
Units
tOLZ
tOHZ(3)
Read Cycle
ADDRESS DATA HIGH DATA VALID DATA VALID tOHZ
Notes: min.,tHZ, tOLZ min., tOHZ periodically sampled 100% tested. max. tOHZ max. measured, with 5pF, from point when return HIGH (whichever occurs first) time when outputs longer driven.
X28ST010
Write Cycle Limits Symbol
tOES tOEH tWPH tBLC
Parameter
Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time Pulse Width HIGH Setup Time HIGH Hold Time Pulse Width HIGH Recovery Data Valid Data Setup Data Hold Delay Next Write Byte Load Cycle
Min.
Max.
Units
Controlled Write Cycle
ADDRESS
DATA DATA VALID DATA HIGH tWPH tOEH
Notes: minimum cycle time allowed from system perspective unless polling techniques used. maximum time device requires complete internal write operation.
X28ST010
Controlled Write Cycle
ADDRESS tOES tOEH DATA DATA VALID DATA HIGH tWPH
Page Write Cycle
*ADDRESS(6) tBLC
BYTE BYTE BYTE BYTE BYTE
LAST BYTE BYTE
*For each successive write within page write operation, A8-A should same writes unknown address could occur.
Notes: Between successive byte writes within page write operation, strobed LOW: e.g. this done with HIGH fetch data from another memory device within system next write; with HIGH effectively performing polling operation. timings shown above unique page write operations. Individual byte load operations within page write must conform either controlled write cycle timing.
X28ST010
PACKAGING INFORMATION
32-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE
1.690 (42.95) MAX.
0.610 (15.49) 0.500 (12.70)
0.005 (0.13) MIN. 0.100 (2.54) MAX.
SEATING PLANE 0.232 (5.90) MAX.
0.150 (3.81) MIN.
0.060 (1.52) 0.015 (0.38)
0.200 (5.08) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.100 (2.54)
0.065 (1.65) 0.033 (0.84) TYP. 0.055 (1.40)
0.023 (0.58) 0.014 (0.36) TYP. 0.018 (0.46)
0.620 (15.75) 0.590 (14.99) TYP. 0.614 (15.60)
0.015 (0.38) 0.008 (0.20)
NOTE: DIMENSIONS INCHES PARENTHESES MILLIMETERS)
3926
X28ST010
PACKAGING INFORMATION
32-LEAD CERAMIC FLAT PACK TYPE
1.228 (31.19) 1.000 (25.40) INDEX
0.019 (0.48) 0.015 (0.38)
0.050 (1.27)
0.830 (21.08) MAX.
0.045 (1.14) MAX. 0.005 (0.13) MIN.
0.007 (0.18) 0.004 (0.10)
0.488 0.430 (10.93)
0.120 (3.05) 0.090 (2.29)
0.370 (9.40) 0.270 (6.86) 0.347 (8.82) 0.330 (8.38) 0.030 (0.76) 0.045 (1.14) 0.026 (0.66)
NOTE: DIMENSIONS INCHES PARENTHESES MILLIMETERS)
3926
X28ST010
PACKAGING INFORMATION
36-LEAD CERAMIC GRID ARRAY PACKAGE TYPE
0.008 (0.20)
0.050 (1.27)
NOTE: LEADS
TYP. 0.100 (2.54) LEADS
TYP. 0.180 (.010) (4.57 .25) CORNERS
TYP. 0.180 (.010) (4.57 .25) CORNERS INDEX
0.120 (3.05) 0.100 (2.54) 0.072 (1.83) 0.062 (1.57)
0.770 (19.56) 0.750 (19.05) 0.020 (0.51) 0.016 (0.41)
0.185 (4.70) 0.175 (4.45)
NOTE: DIMENSIONS INCHES PARENTHESES MILLIMETERS)
3926
X28ST010
PACKAGING INFORMATION
32-LEAD CERAMIC SMALL OUTLINE GULL WING PACKAGE TYPE
0.060 NOM.
DETAIL LEAD INFORMATION 0.020 MIN. 0.340 ±0.007 0.165 TYP. 0.015 TYP.
0.035
0.015
0.035 MIN.
DETAIL
0.0192 0.0138
0.050" TYPICAL
0.050" TYPICAL 0.840 MAX. 0.750 ±0.005 0.560" TYPICAL
0.050
FOOTPRINT
0.030" TYPICAL PLACES
0.440 MAX. 0.560 NOM.
NOTES: DIMENSIONS INCHES FORMED LEAD SHALL PLANAR WITH RESPECT ANOTHER WITHIN 0.004 INCHES
3926
X28ST010
ORDERING INFORMATION
X28ST010 Device
Access Time 200ns 250ns Temperature Range Blank Commercial 185°C Package 32-Lead Cerdip 32-Lead Flat Pack 36-Lead Grid Array 32-Lead Ceramic SOIC
LIMITED WARRANTY Devices sold Xicor, Inc. covered warranty patent indemnification provisions appearing Terms Sale only. Xicor, Inc. makes warranty, express, statutory, implied, description regarding information forth herein regarding freedom described devices from patent infringement. Xicor, Inc. makes warranty merchantability fitness purpose. Xicor, Inc. reserves right discontinue production change specifications prices time without notice. Xicor, Inc. assumes responsibility circuitry other than circuitry embodied Xicor, Inc. product. other circuits, patents, licenses implied. U.S. PATENTS Xicor products covered more following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents additional patents pending. LIFE RELATED POLICY situations where semiconductor component failure endanger life, system designers using this product should design system with appropriate error detection correction, redundancy back-up features prevent such occurence. Xicor's products authorized critical components life support devices systems. Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
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