July 2003 Quartus version This document provides late-breaking informa
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Quartus Software Release Notes
July 2003 Quartus version This document provides late-breaking information about following areas this version Altera® Quartus® software. information about memory, disk space, system requirements, refer readme.txt file your quartus directory. Features Enhancements Device Support Pin-Out Status Full Device Support. Advance Device Support. Initial Information Support. Timing Models Preliminary Timing Models Final Timing Models Interface Information Known Issues Workarounds.7 General Quartus Software Issues. Platform-Specific Issues. Device Family Issues. Design Flow Issues. SOPC Builder Issues Integration Issues Simulation Model Changes Latest Known Quartus Software Issues
Altera Corporation
RN-QIIV3.0-1.0
Quartus Software Release Notes
Version
Features Enhancements
Quartus software version includes following features enhancements: assignment analysis allows validate your assignments before compiling design Chip Editor feature make incremental design changes easily Incremental fitting feature small design changes reduces compilation time while maintaining timing closure Updated Assignment Editor supports device families provides increased functionality usability design space explorer script provides automated method increase design performance performing compilations using varying optimization settings Enhanced LogicLockmethodology lock down routing well placement Support HardCopy Stratixmask-programmed devices Support MAX® 7000S, 3000A, FLEX® 10K, FLEX 10KA device families Enhanced command-line operation with simplified scripting makefile support Support Linux Timing-driven Compilation includes enhancements following areas: Automatically optimizes hold times adding delays paths order satisfy hold time requirements those paths Optimizes user-specified timing constraints (for example; clock period, tSU, tCO, tPD). Clocks paths without user-specified constraints will optimized. absence user-specified timing constraints, timing-driven compilation only focuses maximizing slowest clock design does optimize timing paths. Quartus software displays information messages communicate what timing-driven compilation focusing Physical Synthesis Tools, including register duplication register retiming, extend existing Fitter Netlist Optimizations.
Altera Corporation
Quartus Software Release Notes
Version
Device Support Pin-Out Status
Full Device Support
Full compilation, simulation, timing analysis, programming support available following devices device packages:
Devices with Full Support
Device Family 7000S EPM7032S EPM7128S EPM7192S EPM3128A FC256 EPF10K10 EPF10K30 EPF10K50 EPF10K10A EPF10K50V EP1S10 EP1S40 EP1S80 F1020 EP1SGX25ES EP1C3 EP1C12 HC1S25 HC1S40 HC1S80 Devices EPM7064S EPM7160S EPM7256S EPM3256A FC256 EPF10K20 EPF10K40 EPF10K70 EPF10K30A EPF10K100A EP1S20 F484 EP1S60 EP1SGX40ES EP1C6 EP1C20 HC1S30 HC1S60
3000A FLEX
FLEX 10KA Stratix
StratixGX CycloneHardCopy Stratix
Advance Device Support
Compilation, simulation, timing analysis support provided following devices that will released near future. Although Compiler generates pin-out information these devices, does generate programming files them this release.
Devices with Advance Support
Device Family Cyclone EP1C4F324 Devices EP1C4F400
Altera Corporation
Quartus Software Release Notes
Version
Initial Information Support
Compilation, simulation, timing analysis support provided following devices that will released near future. Programming files pin-out information, however, generated these devices this release.
Devices with Initial Information Support
Device Family None Devices
Timing Models
This section contains summary timing model status current version Quartus software.
Preliminary Timing Models
following table shows devices with preliminary timing models current version Quartus software:
Devices with Preliminary Timing Models
Device Family Stratix Device EP1SGX10 EP1SGX25 EP1SGX40 EP1C3 EP1C4 EP1C12 Notes
Cyclone
changes have been made preliminary timing models this version Quartus software.
Final Timing Models
following table lists devices with final timing models that available current version Quartus software:
Altera Corporation
Quartus Software Release Notes
Version
Devices with Final Timing Models
Device Family APEXII Device EP2A15 EP2A25 EP2A40 EP2A70 EP20K200C EP20K1000C EP1C6 EP1C20 EPXA1 EPXA4 EPXA10 EP1M120 EPM3512A EPM7512B EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 Timing Models Final Quartus Version Number
APEX20KC(1) Cyclone Excalibur
FLEX FLEX 10KA MercuryTM(1) 3000(1) 7000(1) 7000S Stratix
Timing models devices this device family listed here became final versions earlier.
current version Quartus software also includes final timing models ACEX® APEX 20KE, FLEX 6000, FLEX 10KE device families. Final timing models these device families became final versions earlier than version 2.0.
Altera Corporation
Quartus Software Release Notes
Version
Interface Information
Quartus software version supports following tools.
Supported Tools
Synthesis Tools Mentor Graphics® LeonardoSpectrumTM-Altera Mentor Graphics® LeonardoSpectrumSynopsys Design Compiler Synopsys FPGA Compiler Mentor Graphics Precision Synthesis Synplicity Synplify Synplify Aplus Design Technologies (ADT) PALACEVerification Tools Cadence NC-Verilog Cadence NC-VHDL Cadence Verilog-XL Model TechnologyModelSim® Model Technology ModelSim-Altera Mentor Graphics BLAST Synopsys PrimeTime Synopsys Scirocco Synopsys Synopsys Mentor Graphics Verplex Conformal Version 2002f 2003b 2002.02 2003a Version 5.7c 5.7c 1.2.2 2003.03 2002.06 2000.05 3.4.0.a NativeLink® support NativeLink support
Altera Corporation
Quartus Software Release Notes
Version
Known Issues Workarounds
General Quartus Software Issues
Issue Quartus software longer uses registry store non-user interface-related settings. Non-user interface-related settings stored automatically quartus2.ini file when open Quartus software user interface first time. Versions Quartus software earlier than version cannot open Block Design Files (.bdf) created with Quartus software version later. Workaround must open Quartus software user interface least once before using command-line version software.
Changes made Assignment Editor saved only when choose Save (File menu). have turned Save changes files before starting compilation, simulation, software build option Processing page Options dialog (Tools menu), changes made Assignment Editor reflected latest compilation. speed grades given device share same features. default setting Power-Up Don't Care logic option been changed Quartus software version Service Pack later.
alter that opened earlier versions, location information will lost. Open text editor (vi, emacs, notepad). Change version from header section. Remove lines with string "location," example: (annotation_block (location)(rect -336 -248 -8)). Save file. Turn Save changes files before starting compilation, simulation, software build option Processing page Options dialog (Tools menu). Chose Save (File menu) after making changes Assignment Editor Refer Altera data sheet device family further information.
Altera Corporation
Quartus Software Release Notes
Version
Issue There distinction between output ports bidirectional ports AHDL Function Prototypes; instead, ports listed after RETURNS keyword treated output ports. result, specify bidirectional port logic function's Function Prototype Statement connect port top-level bidirectional other logic design where instantiate logic function, error occur. EP20K400GC655 device your design, please contact Altera Customer Applications Department. have version Quartus® software earlier than Quartus software version installed your computer addition Quartus software, start previous version program only running runq.exe program from \quartus\bin directory that contains earlier version wish use. should create multiple Compiler settings that have same design entity "compilation focus." Context-sensitive Help available some items Quartus software.
Workaround Connect port top-level bidirectional other logic design.
locate Help those items, choose Index from Help menu type name item.
Altera Corporation
Quartus Software Release Notes
Version
Issue APEX 20KE devices, Quartus software provides limited support following standards that available with Standard logic option: LVPECL differential standard that similar LVDS standard. APEX 20KE devices support LVPECL pins using pins LVDS mode with external resistor network.
Workaround
LVPECL standard APEX 20KE devices Quartus software, Standard logic option pins LVDS connect pins appropriate external resistor network.
PCI-X enhanced version standard that support higher average bandwidth. This standard more stringent requirements than PCI. cannot locate source error design file compilation unsuccessful syntax error. open project that created using earlier version Quartus software, receive message that indicates that database incompatible that results last compilation will lost.
APEX 20KE drivers meet requirements PCI-X. Turn logic option support PCI-X requirements, including overshoot clamp.
Timing Analyzer does recognize non-PLL clock signals when using megafunction. Waveform Editor does allow create with nodes that nonconsecutive members bus. using altcam, altclklock, altlvds_rx, altlvds_tx megafunctions, equations shown Equations Section Compilation Report complete. Quartus software does support file names with more than extension. example, cannot file name file.eda.edif.
Altera Corporation
maintain existing placement information optionally routing information, backannotate project assignments earlier version. also need generate Quartus Verilog Mapping file (.vqm) netlist preserve result Physical Synthesis. Make clock settings assignments nonPLL clocks. Create buses only with nodes that consecutive members bus. Group command (Edit menu) create groups arbitrary nodes. view complete equations these megafunctions, Equations window Last Compilation floorplan.
file names with only extension.
Quartus Software Release Notes
Version
Issue install Quartus software UNIX server that exports shares with Samba software version 1.9.18p10, experience problems accessing project files also network. make assignments reserve pins group with group notation (debug[7.0]), Quartus software does correctly generate simulation output files, receive warning message saying "Unsupported data type top-level module." Quartus software versions later supports only version later Altera PowerKitsoftware. Previous versions PowerKit software supported with these versions Quartus software. using HSTL Class standard with APEX device, additional information required. change file permissions (such changing "read-only" "read write") Quartus settings configurations files (.csf, .esf, while Quartus project open. order ports ARM®-based Excalibur MegaWizard® Plug In-generated symbol stripe changed version Quartus software. re-run MegaWizard Plug-In Manager (Tools menu) design created version Quartus software earlier than version 2.0, will receive port connection errors when compile design. Node names containing numbers greater than 2^31-1 (2147483647) will cause Internal Error Quartus software.
Workaround Altera recommends using version 1.9.16p11 Samba software.
Reserve pins using single name notation (for example, debug7, debug6, on).
Contact Altera Customer Applications department apexii@altera.com information about Service Packs device pin-outs. Close Quartus project before making changes file permissions.
avoid receiving these errors, adjust port connections after updating symbol.
node names containing large numbers.
Altera Corporation
Quartus Software Release Notes
Version
Issue Occasionally Programmer does allow 7000AE Programmer Output File (.pof) with 7000AE device. This error sometimes occurs after compatible 7000B device used with 7000AE POF. Quartus software versions later longer support Compiler Settings File (.csf) MIGRATION_DEVICES variable.
Workaround switch between compatible 7000B 7000AE devices when 7000AE loaded, reload 7000AE POF. order specify migration device names CSF, DEVICE_MIGRATION_LIST variable. example:
DEVICE_MIGRATION_LIST "DEVICE_A,DEVICE_B,DEVICE_C";
Routing back-annotation fail backannotated locations match location assignments location assignments missing. This problem occur change devices, remove some location assignments using Assignment Editor (Assignments menu) manually editing CSF. After register duplication occurred, duplicated register unique name form <original name>~<suffix>. register name properly inherit timing assignments made with wild cards. receive "invalid command name" error when existing script that uses toolkit user interface. Beginning with Quartus software version 2.2, Quartus software longer initializes toolkit automatically when starting process. lpm_fifo MegaWizard Plug-In been removed from Quartus software version 2.2. lpm_fifo megafunction still included backward compatibility with older designs.
experience fit" Internal Error while using routing back-annotation, delete Routing Constraints File (.rcf) back-annotate design again after successful compilation.
Make sure that duplicated register names included your wild card match when making timing assignments.
command "init_tk" beginning script that uses
Altera recommends that lpm_fifo+ MegaWizard Plug-In designs requiring single-clock FIFO functions.
Altera Corporation
Quartus Software Release Notes
Version
Issue receive error message saying "System resources low." user interface slow responding there disk activity when compiling design, your system running free memory.
Workaround recover system memory clearing messages from Messages window. clear messages from Messages window, right-click anywhere Messages window choose Clear Messages from Window (right button pop-up menu). Additional memory recovered closing Floorplan Editor. Delete Quartus Workspace File (.qws) <project name>.qws from project directory. problem persists, delete <project directory>\db directory. should first select values parameter (phase shift duty cycle) that most important your design.
Occasionally, Quartus software crash hang with error message immediately upon opening project. When setting phase shift duty cycle values clock signals using altpll megafunction, some combinations settings result values that cannot synthesized exactly. Under certain circumstances, Quartus software attempts synthesize phase shift parameter before duty cycle parameter. Fitter Timing Information setting been removed from Netlist Optimizations page Settings dialog (Assignments menu) Quartus software version 3.0.
Quartus software version supports this netlist optimization setting only form flow. This flow called twopass optimization flow. this with following command-line command: quartus_sh -flow two_pass_optimization <project> <csf/ssf>] <Enter> also embedded script using following command: quartus_sh your_script.tcl <Enter> script named your_script.tcl should then contain following commands: package require ::quartus::flow project_open <project> execute_flow -two_pass_optimization project_close
Altera Corporation
Quartus Software Release Notes
Version
Issue During compilation simulation, Quartus software "hang" proceed next module menu modal dialog open time current module finishes execution. global Preserve Hierarchical Boundary logic option assignment been removed from user interface Quartus software version 3.0.
Workaround Close open menus modal dialog boxes before compilation simulation reaches next stage.
need Preserve Hierarchical Boundary logic option Firm, entity-by-entity basis with Assignment Editor, following command make assignment: set_global_assignment -entity <entity_name> -name
PRESERVE_HIERARCHICAL_BOUNDARY FIRM
Running individual Quartus software executables (quartus_map, quartus_fit, from within Quartus Console cause Quartus software crash. have chosen migration devices Compatible Migration Devices dialog box, which available from Device page Settings dialog (Assignments menu), Timing Closure Floorplan Last Compilation Floorplan will display only pins PLLs that common selected devices. However, Chip Editor will display pins PLLs available device specified compilation. Under certain circumstances, remove LogicLock assignments with Remove Assignments dialog (Assignments menu), assignments will removed from your project. When specifying entity name Look Node Finder, case entity name must match case Compilation focus entity name actual design file entity name.
should individual executables either from within Quartus scripting shell (quartus_sh) directly command prompt.
LogicLock Regions window (Assignments menu) remove LogicLock assignments.
Altera Corporation
Quartus Software Release Notes
Version
Issue online Help Minimum Timing Analysis does describe device families that support this feature.
Workaround
Minimum Timing Analysis supported following device families: APEX 20KE, APEX 20KC, APEX Mercury, Stratix, Stratix Stratix HardCopy. Changing devices while critical path(s) Turn Routing Show Critical Paths shown Timing Closure Floorplan option (View menu) before changing devices cause Quartus software crash. compilation. licenses that were issued earlier than June, Licenses that will work contain "SIGN 2002 will work Quartus version portion feature line. Feature line software. your does contain "SIGN portion, then must obtain license from Altera logging onto import LogicLock regions after Import LogicLock regions other running HardCopy Files wizard (Project entity settings) before running HardCopy menu), Quartus software crash. Files wizard. Close, then reopen your project Quartus software before importing LogicLock regions other settings. Under certain circumstances, Quartus sure change back last device software crash change device after specified compilation before opening compiling your design before opening Resource Property Editor. Resource Property Editor. Turning Physical Synthesis Netlist compilation time excessive with Physical Optimizations page Settings dialog Synthesis turned either remove convert LogicLock Regions "soft" before average will cause compilation time recompiling, turn Physical double peak memory usage increase approximately 20%. large designs, Synthesis. Progress Fitter appear stuck 50-70% range while elapsed time continues increase. Provided that compilation time increased over 10X, this normal compilation should allowed finish. rare cases, compilation time increase more than 10X. these cases, appropriate apply workaround cannot tolerate such long compilation time.
Altera Corporation
Quartus Software Release Notes
Version
Issue following Altera megafunctions have simulation models altera_mf library: altmemmult altpll_reconfig altremote_update altdqs altclkbuf
Workaround corresponding <device>_atoms.v .vhd file your design compilation. These files located \quartus\eda\sim_lib directory.
Platform-Specific Issues
Only Issue Under certain circumstances, Quartus installation program crash receive error message immediately upon launching installation program. Workaround Reinstall stdole32.tlb file from original Windows distribution disks. reinstall file, type appropriate command command prompt. (Note: command must typed line.) Windows <CD-ROM drive letter>:\i386\expand.exe stdole32.tl_ %SystemRoot%\System32\stdole32. <Enter> Windows 2000: <CD-ROM drive letter>:\i386\expand.exe stdole32.tl_ %SystemRoot%\System32\stdole32. <Enter> Windows <CD-ROM drive letter>:\i386\expand.exe stdole32.tl_ %SystemRoot%\System32\stdole32. <Enter> Windows Task Manager process before running Quartus software again.
possible that Quartus executable files (quartus.exe, quartus_cmd.exe, quartus_swb.exe, quartus_dbc.exe, quartus_old_sim.exe) terminate properly after error.
Altera Corporation
Quartus Software Release Notes
Version
Issue full, hierarchical name instance exceeds characters, displayed properly Quartus user interface. This problem occurs most often with EDIF netlist files generated other synthesis tools. Japanese-language version online Help file Quartus software version included Quartus software CD-ROM. Japanese online Help with current version Quartus software, Help information will up-to-date. running Quartus software from network server, Quartus software will properly client computer share \quartus\bin directory. running ZoneAlarm personal firewall software, receive message saying, "Can't start continue database creator" when launch Quartus Simulator.
Workaround Limit full, hierarchical instance name fewer than characters possible.
Japanese online Help, copy quartus.chm file from jhelp directory CD-ROM your \quartus\bin directory.
must share quartus directory, \quartus\bin directory.
Quartus software compatible with ZoneAlarm software. ZoneAlarm software mistakenly determines that Quartus Simulator accessing Internet when uses TCP/IP interprocess communication. must disable ZoneAlarm software Quartus Simulator. Under some circumstances, Quartus Close button close Print software crashes when using button Preview window have project open. close Print Preview window project open. Close Quartus software before disconnect your network connection disconnecting network connection while Quartus software open, receive error message saying "Can't wait "LAN disconnected" start continue message Windows Taskbar before restarting Quartus software. creator." Quartus software compatible Turn MATLAB server with MATLAB server. Services Control Panel (Start menu) before running Quartus software. Under some circumstances, Quartus registry settings controlling position splash screen appears Quartus icon Quartus windows have become appears Taskbar, graphical user corrupted. Type following command interface does appear. command prompt: quartus -reset_desktop <Enter>
Altera Corporation
Quartus Software Release Notes
Version
Issue Path names longer than characters cause internal error Quartus software. Under some circumstances, Quartus software correctly first time started after installation, then fail with "License Found" error thereafter.
Workaround Make sure that path names exceed characters. have specified multiple license servers either your LM_LICENSE_FILE environment variable License Setup page Options dialog (Tools menu), must make license server that serves Quartus software license first server specified line. Start Quartus software before opening Quartus project file file.
Opening Quartus software dropping Quartus project file (.quartus) Quartus Archive file (.qar) onto shortcut Quartus software will cause Quartus software crash when project compiled. install stand-alone Quartus Programmer Quartus software, then uninstall either one, Programmer report "JTAG Server internal error code occurred" when click Hardware button Hardware Setup dialog (Edit menu). This error occurs because uninstalling software disabled JTAG Server service. Solaris, HP-UX Linux Issue Quartus Help available have either MWNO_RIT MWDONT_XINITTHREAD environment variables before running Quartus software. using Exceed server software Windows while running Quartus software, font size larger than line height. This problem occurs most often installed Exceed software while running screen resolution greater than 1024 768.
Altera Corporation
Manually restart JTAG Server service locating jtagserver.exe program command prompt that directory, type jtagserver -install <Enter>
Workaround Remove variables from your environment allow Quartus software these variables automatically, needed.
Reinstall Exceed software while running screen resolution 1024 768. then switch back your normal, higher resolution setting.
Quartus Software Release Notes
Version
Issue Under some circumstances, there editor windows listed Window menu that cannot see. cannot launch Debugger software from within Quartus software. Under some circumstances, Internet connectivity features Quartus software functional.
Workaround display hidden windows, choose Cascade (Window menu). Launch Debugger software from outside Quartus software. Specify full path your browser software Internet Connectivity page Options dialog (Tools menu). access Internet through proxy server, must also specify address proxy server port number. Select color close Color list box.
Colors list Block Symbol Editor Color Options page Options dialog (Tools menu) Format Properties dialog (Edit menu) object Block Symbol Editors remain open, cause internal error click anywhere else Quartus software before closing Colors list box. cannot Innoveda BLAST software automatically from within Quartus software, even this tool automatically after compilation option turned cannot Mentor Graphics LeonardoSpectrum software from within Quartus software even this tool automatically after compilation option turned cannot Model Technology ModelSim software from Tool PostCompilations Options Simulation Tool command (Processing menu) from within Quartus software. access Quartus online Help typing quartus.chm <Return> command prompt. attempt exit from Quartus software while Tutorial window open, Tutorial window remain open respond your commands.
Innoveda BLAST software manually outside Quartus software.
LeonardoSpectrum software manually outside Quartus software.
ModelSim software outside Quartus software.
Close Tutorial window before exiting from Quartus software.
Altera Corporation
Quartus Software Release Notes
Version
Issue When LogicLock Regions window floating, cannot drag drop node names from Node Finder. accessing Quartus software through following versions Hummingbird Exceed software (6.2, 7.0, 8.0) have Microsoft Office application Internet Explorer open, Quartus user interface start very slowly. Spaces directory paths file names used Quartus command-line executables will cause error. Semicolons command-line arguments, such following example: quartus_map path1;path2;path3, will cause error because software interprets arguments separate commands.
Workaround Dock LogicLock Regions window before dragging node names from Node Finder. Contact Hummingbird Software www.hummingbird.com patch Exceed software.
Rename file directory such that does contain spaces. Enclose command-line arguments that require) semicolons (for example, quartus_map quartus_pgm quotes. example, "quartus_map path1;path2;path3" intentionally perform multiple commands single line, enclose semicolons quotation marks. example: quartus_sh -tcl_eval puts Hello puts World recommended usage this example -family=APEXII. escaped quotation marks (\") enclose strings Tcl, whitespace characters within string will reduced single space. Example: quartus_sh -tcl_eval puts \"Hello World\"
Spaces command-line arguments, even when enclosed quotes, such following example -family="APEX will seen separate arguments will cause error. Additionally, command quartus_sh -tcl_eval puts "Hello World" will work UNIX Linux.
Altera Corporation
Quartus Software Release Notes
Version
Issue Portions SOPC Builder function correctly perform crossplatform installation (for example, from Solaris workstation Linux workstation).
Workaround Install software from same platform that which will Type following command command prompt either platform (note command must line): <path perl>/perl <path Quartus II>/sopc_builder/bin/regs opc.pl -quartus_root_dir=<path Quartus <Enter>
Solaris Only Issue Workaround
Check site ARM-based Excalibur MegaWizard which available from solaris-patches.html MegaWizard Plug-In Manager requires Java Runtime Environment (JRE) version 1.3, information about patches that might needed. which already been installed your computer. Solaris workstations, however, need install extra patches operating system order function properly. Japanese online Help, copy Japanese-language version online quartus.chm file from jhelp directory Help file Quartus software version CD-ROM your /quartus/solaris included Quartus software directory. CD-ROM. Japanese online Help with current version Quartus software, Help information will up-to-date. attempt exit from Quartus Close Tutorial window before exiting software while Tutorial window open, from Quartus software. Tutorial window remain open respond your commands. attempt Excalibur Stripe following setting your Simulator (ESS) with ModelSim software, environment: QESS_PLATFORM solaris. receive error message saying that addition, your designs Verilog ModelSim software cannot locate HDL, must your veriuser path follows: libraries. veriuser $QESS_ROOTDIR/ $QESS_PLATFORM/libess_sspli.so
Altera Corporation
Quartus Software Release Notes
Version
Issue running FLEXlm license server software Solaris server, alterad daemon fail start receive following message: "Vendor daemon can't talk lmgrd" Launching SOPC Builder without certain run-time patches operating system cause receive message indicating that "Could create Java virtual machine." double-click click hold dropdown list boxes Property Resource Editor Quartus software crash. HP-UX Only Issue receive error messages indicating that have required permissions perform requested operation while using Network Information Services (NIS). Attempting convert your device SRAM Object Files (.sof) Programmer Output Files (.pof) with configuration device, such EPC2 device, causes Quartus software "hang" when open Conversion Setup File (.cof). Japanese-language version online Help file Quartus software version included Quartus software CDROM. Japanese online Help with current version Quartus software, Help information will up-to-date. Programming EPC16 configuration devices causes Quartus software crash.
Workaround following script start lmgrd daemon: #!/bin/sh ulimit 1024 ulimit 1024 lmgrd Visit site following determine download appropriate patches your system: sunsolve.sun.com/pub-cgi
Workaround plus-sign followed carriage return line itself last line both following files: /etc/passwd /etc/group. Create usual your project with Files Project command (Project menu).
Japanese online Help, copy quartus.chm file from jhelp directory CD-ROM your /quartus/hp11 directory.
Altera Corporation
Quartus Software Release Notes
Version
Issue
Workaround
maximize Utility windows after float Utility window (Change restricting them main window. Manager, Node Finder, Project Navigator, Status Window, etc.) main window with Restrict Main Window command (right-button popup menu), then maximize that window after Report window been opened, Quartus software crash. Linux Only Issue Japanese-language version online Help file Quartus software version included Quartus software CDROM. Japanese online Help with current version Quartus software, Help information will up-to-date. MasterBlasterdownload cable listed Available hardware items list Hardware Settings Hardware Setup dialog box, connected properly, have read/write permission serial (dev/ttySx) port which MasterBlaster cable connected. This release Quartus software supports ByteBlaster ByteBlasterMV download cables using either Passive Serial JTAG modes. Although generate Files (.jam) ByteCode Files (.jbc), these file types supported device configuration Linux version 7.1. Additionally, EPC4, EPC8, EPC16 configuration devices supported this time, programming times EPC2 devices extremely slow. Workaround Japanese online Help, copy quartus.chm file from jhelp directory CD-ROM your /quartus/linux directory.
Have system administrator assign read/write permission appropriate port. This change accomplished adding "uucp" group, giving read/write permission serial port everyone, using following command: chmod o+rw /dev/ttySx where serial port affected. information about using ByteBlaster ByteBlasterMV download cable with Quartus software Linux operating system, refer Quartus Installation Licensing Manual UNIX Linux Workstations, contact Altera Customer Applications.
Altera Corporation
Quartus Software Release Notes
Version
Issue using ReflectionX X-server software your display Linux workstation, Quartus software hang white appear.
Workaround QUARTUS_MWWM environment variable allwm then start Quartus software without splash screen typing following commands command prompt: setenv QUARTUS_MWWM allwm <Enter> quartus -no_splash <Return> scripts only when compilation, simulation, software build processes running.
Running script with Scripts command from within Console while process (compilation, simulation, software build) running background cause Quartus software crash with internal error. double-click click hold dropdown list boxes Resource Property Editor Quartus software crash. When running Quartus software under Linux operating system, LogicLock Regions Properties dialog shown completely. When running Quartus software under Linux operating system, Insert Symbol dialog MegaWizard Plug-In Manager window cannot closed using Window Close button right corner. float Utility window (Change Manager, Node Finder, Project Navigator, Status Window, etc.) main window with Restrict Main Window command (right-button popup menu), then maximize that window after Report window been opened, Quartus software crash. Under certain circumstances, Quartus software start properly.
Right-click title dialog window choose Close (right-button menu).
maximize Utility windows after restricting them main window.
Ensure that /etc/hosts file entry hostname machine which running. example, workstation named "orange", there should entry /etc/hosts with address "orange" workstation shown below: address orange> orange
Altera Corporation
Quartus Software Release Notes
Version
Issue Quartus software crash have Graphic Editor open Block Design File (.bdf) Programmer open type range values Number Words Word Size Number Words Word Size dialog Memory Editor.
Workaround Enter positive integers only negative numbers alphabetic characters) Number Words Word Size boxes.
Device Family Issues
Mercury Issue your Quartus version design Mercury device uses altlvds_tx altlvds_rx megafunction, archived design, have functional problems your design, including inverted signals. Excalibur Issue receive message "System Build Descriptor File missing parameter programming_clock_frequency" System Build Descriptor Files (.sbd) generated Quartus software version earlier, after selecting Boot from Serial option ARM-based Excalibur MegaWizard Plug-In. Workaround Rerun ARM-based Excalibur MegaWizard Plug-In current version Quartus software regenerate File correct error. Workaround Delete altlvds_tx altlvds_rx megafunction from design replace with version included with current version Quartus software before compiling your design Quartus software version later.
Altera Corporation
Quartus Software Release Notes
Version
Issue using Stripe-to-PLD Bridge Excalibur EPXA10 Devices, your design function Stripe-to-PLD Bridge lockup errata either following options turned Quartus software: Remove Redundant Logic Cells Perform WYSIWYG Primitive Resynthesis Please refer EPXA10 Device Errata Sheet details device errata.
Workaround avoid bridge lock-up, ensure that Remove Redundant Logic Cells option turned project. Perform WYSIWYG Primitive Resynthesis option turned your project, receive warnings that stripe signals were routed correctly. eliminate warnings, re-run MegaWizard Plug-In Manager Quartus version software. This procedure will create additional settings file (alt_exc_stripe.esf) ensure that required logic elements implemented.
Cyclone, Stratix Stratix Issue Inverting clock signal logic cell that clock enable signal with Resource Property Editor when other logic cells same share both clock clock enable signals will pass netlist checks choosing Check Save Netlist Changes command (Edit menu) cause Quartus software crash with internal error Assembler. Under certain circumstances, LogicLock region design appears after compilation block lower-left corner device floorplan. Workaround Invert clock signal logic cells with common clock clock enable signals. Inverting only clock signal requires that change your source.
This problem occur when both Automatically route signal probe signals option Smart Compilation/More disk space option Mode page Settings dialog (Assignments menu) turned prevent this problem from occurring future, perform following steps: Turn Smart Compilation/More disk space option Turn Preserve fewer node names option. Turn Automatically route signal probe signals option. Recompile your design. Create desired LogicLock regions.
Altera Corporation
Quartus Software Release Notes
Version
Issue Quartus software perform register duplication into cells even though have Netlist Optimizations option Never Allow that register. When Routing Constraints File (.rcf) control fitting after performing Routing Back-Annotation, your timing analysis results change slightly parasitic other effects. change will very small. SignalProbe feature observe signals output pin, routing them another output pin, SignalProbe output signal will shown Unknown Quartus Simulator. SignalProbe Source Output Delays table Timing Analyzer Report, following right-button menu commands available that available other similar Timing Analyzer Report tables: List Paths Locate Chip Editor Locate Timing Closure Floorplan Locate Last Compilation Floorplan Under certain circumstances, Quartus software crash with internal error about complete Fitter module.
Workaround Turn Auto Packed Registers option affected register.
signal will correct actual operation, error only appears Quartus Simulator.
other Timing Analyzer Report tables list locate affected paths.
automatic hold time optimization algorithm increase your compilation times significantly. When compiling Stratix, Stratix Cyclone designs with tight requirements, Quartus software choose delay chain settings meet constraint such that guaranteed I/Os, user constraint these I/Os.
Open LogicLock Regions window (Assignments menu) right-click each LogicLock region that highlighted red. Choose Repair Branch right-button pop-up menu corrupted LogicLock region. After corrupted regions fixed, recompile your design. Fitting page Settings dialog (Assignments menu), turn Optimize Hold Timing. your design requires some I/Os, should make appropriate assignments that Quartus software will optimize analyze them.
Altera Corporation
Quartus Software Release Notes
Version
Stratix Stratix Issue Designs that make DQS, Fast Clock, corner LVDS PLLs Stratix Stratix devices have back-annotated routing Quartus software version earlier generate warnings version 3.0. warning will indicate that backannotated routing will ignored these connections. result, routing these resources different from routing when compiled with Quartus software version SP2. Stratix Issue Versions Quartus software earlier than version correctly implement following functions blocks Stratix devices: Mixed sign multiplications bits greater Dynamic sign multiplications bits greater Signed multiplications greater than bits Designs compiled Stratix EP1S40ES devices must recompiled EP1S40 device before programming. Stratix simulation models have been enhanced handle jitter input clock. This enhancement unintended side effect that functional simulations LVDS designs using cascaded PLLs incorrect clock cycle. Workaround Designs that implement functions must recompiled Quartus software version later. Quartus software version will implement design correctly, will more resources have reduced performance from earlier versions. Workaround These warnings ignored safely. should back-annotate routing achieved using Quartus software version create Routing Constraints file (.rcf). Only routing constraints DQS, corner LVDS PLL, fast clocks should change.
Altera recommends that perform Timing Simulation display correct behavior Quartus Simulator other Simulators.
Altera Corporation
Quartus Software Release Notes
Version
Changes Stratix Timing: Enhanced Maximum Clock Frequency (MHz) Speed Grade Quartus Ver. Stratix Datasheet Ver. Quartus Ver. 1000 1000 1000
Fast Maximum Clock Frequency (MHz) Speed Grade Quartus Ver. Stratix Datasheet Ver. Quartus Ver. Enhanced PLLs (EPLLs): Quartus software version later will enforce 300-800 clock frequency range specified Stratix device family data sheet speed grades. clock frequency range speed grade 300- MHz. Fast PLLs (FPLLs): Quartus software version later will continue support 300-1000 clock frequency range when FPLL used general purpose PLL. higher clock frequency range enables more flexibility choosing multiplication division factors Quartus software. When FPLL used Source Synchronous mode, clock frequency range unchanged from data sheet specification 300-840 MHz. Stratix Issue Currently simulation models provided altgxb megafunction model power-up condition correctly simulation other simulation tools. Workaround must manually pll_areset signal power high your test bench simulation vector file. Refer "Perform Functional Simulation." topics "Using Other Simulation Tools" section Quartus Help more information. 1000 1000 1000 1000 1000
Altera Corporation
Quartus Software Release Notes
Version
Issue Quartus software version also supports PowerGaugesimulation-based power estimation Stratix device family. power estimation includes approximately each Stratix transceiver block design. Cyclone Issue Altera recommends that frequency external clock output PLLs limited MHz. Cyclone EP1C3T100 device does support LVDS standard pins. APEX Issue altddio_in altddio_bidir megafunction connect dataout_h dataout_l ports, will receive error message design will fail compile.
Workaround
Workaround
Cyclone EP1C3T144 device instead. supports LVDS standard.
Workaround Connect dataout_h dataout_l ports.
Design Flow Issues
Verification Issue Node names module outputs that directly connected inferred objects (counters, forth) cannot added SignalTap File (.stp). select SignalTap pre-synthesis SignalTap post-fitting Filter list Node Finder select File, Quartus software expand into individual nodes that removed during synthesis, resulting error. Workaround such node names File, should first assign those names signal then File. Delete nodes recompile project. select individual nodes Node Finder group them SignalTap window using Group command (Edit menu).
Altera Corporation
Quartus Software Release Notes
Version
Simulation Issue PLLs designs targeted Stratix devices sometimes simulate correctly other simulation tools. PLLs lock when driving altlvds_tx megafunction with altlvds_rx clock, driving altlvds_rx megafunction with altlvds_tx clock. Workaround Make following changes VHDL Verilog files generated MegaWizard Plug-In Manager altlvds_tx altlvds_rx megafunctions. When using altlvds_tx clock output drive altlvds_rx PLL, make following changes: VHDL COMPONENT altlvds_rx GENERIC (clk_src_is_pll STRING altlvds_rx_component altlvds_rx GENERIC (clk_src_is_pll "on" Verilog HDL: altlvds_rx_component.clk_src_is _pll "on"; when using altlvds_rx clock output drive altlvds_tx PLL, make following changes: VHDL COMPONENT altlvds_tx GENERIC (clk_src_is_pll STRING altlvds_tx_component altlvds_tx GENERIC (clk_src_is_pll "on" Verilog HDL: altlvds_tx_component.clk_src_is _pll "on";
Altera Corporation
Quartus Software Release Notes
Version
Integrated Synthesis (VHDL Verilog HDL) Issue Verilog VHDL extractors support translate_off translate_on pragmas. This change support cause problems some designs that relied behavior Quartus software versions earlier than version 2.1, which ignore pragmas. common case where have MegaWizard-generated VHDL Verilog megafunction have added translate_off translate_on pragmas hide internal details from your synthesis tool. those pragmas, details will also hidden from Quartus software, result, megafunctions will implemented when compile using Quartus software version later. Some designs that compiled successfully using Quartus software version compile successfully using Quartus software version later. Common issues are: Assigning single register multiple Always Constructs Process Constructs. Quartus software version later will give multiply-driven signal error. Width mismatches VHDL that were caught Quartus software version 2.0. Referring another generic within generic list VHDL, example having generic WIDTH generic DATA(WIDTH downto This feature officially supported VHDL, supported many tools including Quartus software version 2.0. supported Quartus software version later. Workaround
Altera Corporation
Quartus Software Release Notes
Version
Issue have core VHDL Verilog your license correctly, will "Can't open design file" error. Quartus software version later connect nets driven together, nets driven together. This cause confusing error messages, electrical conflict reported net, necessarily that actually causing problem. Quartus software version gives message "Error: Duplicate entity <name> found file <filename1> colliding with found file <filename2>," project that compiled successfully with Quartus earlier.
Workaround Refer Application Note 205: Altera Licensing Application Note 229: Troubleshooting Altera Software Licensing more information setting your license.
Quartus software version gives message "Error: illegal Procedural Assignment nonregister data type <name>," "Error: illegal continuous assignment non-net data type <name>," project that compiled successfully with Quartus software version earlier. Quartus software version gives message "Error: unsupported choice with meta-value `X'" `-`) project that compiled successfully with Quartus software version earlier. This occurs case statement which uses meta-values `-`.
Quartus software version earlier versions gave Warning when they encountered duplicate definition VHDL Verilog entity ignored duplicate. Quartus software version will give error message when finds more definitions VHDL Verilog entity same project. avoid this error future, remove duplicate entity entities. Quartus software version enforces distinction between data types wire data types, required Verilog standard. Quartus software version earlier enforce this distinction. avoid receiving this error future, declare variable wire when continuous assignment, when procedural assignment. Previous versions Quartus software ignored case item with meta-value printed Warning message. However, this cause simulation-synthesis mismatches this design style also synthesized differently with other synthesis tools. match behavior Quartus software version 2.2, delete case item with meta-value. this behavior want, re-code your design avoid case statement.
Altera Corporation
Quartus Software Release Notes
Version
Verilog Integrated Synthesis Issue Verilog-2001 mode enabled default. This mode cause some issues with Verilog-1995 designs, most commonly reserved words Verilog-2001 such config. Quartus software version later looks files `include compiler directive project root directory user library directories. there path specified, interpreted being relative project root directory user library directory. function call vector range specification causes Internal Error. Verilog escaped names that look like vectors cause problems Quartus software. example, have singlebit component port named \my_vector_port[3:0], Quartus software versions later will treat array port. Quartus software version later does allow parameter value overrides (Defparam Statements) parameter. This behavior different from IEEE Std. 13642001 IEEE Standard Verilog Hardware Description Language manual, which last Defparam Statement used there multiple Defparam Statements. Recursive Verilog functions modules, such module that instantiates itself, supported Quartus software. VHDL Integrated Synthesis Issue Quartus software version later does synthesize user-defined enums. Workaround Workaround Verilog-2001 reserved words identifiers select Verilog-1995 Verilog input page under Input Settings Settings dialog (Assignments menu).
should avoid using escaped port names Quartus software version later.
Altera Corporation
Quartus Software Release Notes
Version
SOPC Builder Issues
Issue Quartus software installed directory having space characters name, SOPC Builder software will run. When adding Excalibur Stripe component conjunction with Avalon peripherals, encounter SOPC Builder errors indicating many masters present. Workaround Install Quartus software directory that does have space characters path. master-connection patch-panel visible, choose Show Master Connections (View menu). Then click master/slave intersection indicated error message. This will remove connection. Click again restore connection error will reappear. problem occurs only when base address specified SREC file implied binary file does explicitly match base address targeted memory. avoid this problem, following techniques: binary file, base target memory address SREC file input, base same address target memory Initialize memory run-time Choose SOPC Builder Setup (File menu) SOPC Builder Installation box, type path your existing Nios installation. Click Exit restart SOPC Builder. Your components should accessible.
After specifying Motorola S-Record file (.srec) binary file (.bin) containing onchip memory contents, resulting generated files contain memory data.
installed Nios don't your Nios-related components SOPC Builder 3.0, them inaccessible white dots (unlicensed components). This includes Nios core itself well Timer, PIO, UART, SPI, other items.
Altera Corporation
Quartus Software Release Notes
Version
Issue Only 'bash' 'sh' supported SOPC Builder Shell. 'csh' support previously available Nios kits present SOPC Builder version 3.0. This does affect SOPC Builder from within Quartus software.
Workaround Contact Altera Applications updates status 'csh' support. Users their environment operate SOPC Builder under 'csh', setting PATH other variables using script: example.
SOPC Builder Compatibility
Nios version 3.0x SOPC Builder 2.8x
your existing Nios components they will recognized automatically SOPC Builder integrated into Quartus version software.
Nios version SOPC Builder
Your Nios components compatible with SOPC Builder integrated with Quartus version software. will receive upgraded Nios components part Nios Development Kit. your earlier version SOPC Builder following these steps: Altera SOPC Builder shown MegaWizard Plug-In Manager, reinstall SOPC Builder version software, copy sopc_builder_2_7_wizard.lst file into your quartus\libraries\megafunctions directory. When open system that uses Nios version embedded processor, will given choice using Altera SOPC Builder Altera SOPC Builder 2.7. Choose version. choose version without number (version 3.0) your components will disabled.
SOPC Builder Project Files
When open project created version SOPC Builder earlier than version SOPC Builder included Quartus version software, will given choice update your project cancel operation. choose update your project, software will make backup copy your SOPC Builder Project file (.ptf) will modify your make compatible with current version software.
Altera Corporation
Quartus Software Release Notes
Version
choose cancel operation, open your project with earlier version SOPC Builder software following steps shown above.
Integration Issues
Issue current version Quartus software allows select Synplicity Amplify software physical optimization tool. However, this setting ATOPS mode, which currently supported Amplify software. directory containing ARM-based Excalibur stripe models changed Quartus software version 2.0. This change cause compilation scripts that were created earlier versions Quartus software fail. There option installation program install tool interface Cadence Concept software, even though software supported Quartus software version 2.2. Cadence NC-VHDL version software requires s013 patch, which contains more stable version NC-VHDL software. Wildcard timing assignments made Quartus software included Quartus II-generated Script File performing timing analysis Synopsys PrimeTime software. Workaround Contact Synplicity support schedule Amplify software ATOPS mode.
Edit your compilation scripts that models simulation wrapper files located following directory: \quartus\eda\sim_lib\ excalibur\ stripe_model_<operating system> \ModelGen\models\epxa<1 10>\r0\<simulator_language> Select Cadence Verilog-XL installation install cadence.tcl interface script your <Quartus installation>/eda/cadence directory. Install s013 patch, available from Cadence, NC-VHDL software before simulating designs. wildcard timing assignments directly PrimeTime software, assignments Synopsys Design Constraints (SDC) File project, modify Quartus II-generated Script File include assignments before performing timing analysis PrimeTime software.
Altera Corporation
Quartus Software Release Notes
Version
Issue Quartus software duplicate some registers during fitting, which cause unmapped points between golden revised netlists when performing formal verification with Verplex Conformal software.
Workaround flatten revised netlist software merge duplicated registers, following command Quartus IIgenerated <design name>.vlc script file. flatten model -all_seq_merge performing formal verification manually software, type command prompt.
altdqs files generated MegaWizard Plug-In Manager will simulate with other simulation tools correctly.
must edit each instantiation altdqs megafunction your design. Inside stratix_dll section, locate phase_shift parameter. Convert value that parameter integer removing quotation marks from around Locate input_frequency parameter. Convert value picoseconds type without quotation marks. Comment lines that contain following code: lpm_type. Inside each stratix_io sections, locate sim_dll_phase_shift parameter. Convert value that parameter integer removing quotation marks from around Locate sim_dqs_input_frequency parameter. Convert value picoseconds type without quotation marks. Comment lines that contain following code: lpm_type. addition, VHDL instantiations, must locate corresponding Component Declarations change them shown example below: (continued next page)
Altera Corporation
Quartus Software Release Notes
Version
Issue Continued from previous page
Workaround
COMPONENT stratix_dll GENERIC INPUT_FREQUENCY STRING; PHASE_SHIFT STRING "90";
should modified
INPUT_FREQUENCY INTEGER; PHASE_SHIFT INTEGER
SIM_DLL_PHASE_SHIFT STRING "unused"; SIM_DQS_INPUT_FREQUENCY STRING;
should modified
SIM_DLL_PHASE_SHIFT INTEGER SIM_DQS_INPUT_FREQUENCY INTEGER;
Simulation Model Changes
altera_mf Models
Models Model altqpram Change Improved checking 'write enabled' under BIDIR mode. (VHDL Verilog HDL) Enabled simultaneous write different address rectify port write operation under BIDIR mode. (VHDL Verilog HDL) Fixed inconsistent read from with simulator. (Verilog HDL) Added width_byteena support Clearbox flow. (VHDL) Fixed shifting operation avoid race condition reported VCS. (Verilog HDL) Added ADD_RAM_OUTPUT_REGISTER parameter support registered output. (VHDL Verilog HDL) Fixed almost_full almost_empty ports when ALMOST_FULL(EMPTY)_VALUE=0/1. (VHDL Verilog HDL) Standardized unconnected port inaclr value avoid inconsistent result from different simulators. (Verilog HDL)
altdpram altsyncram dcfifo
scfifo altcam
Altera Corporation
Quartus Software Release Notes
Version
Models Model altmult_add Change Added parameters (dedicated_multiplier_circuitry intended_device_family) support wizard flow. (VHDL Verilog HDL)
Models Model altpll altcdr altlvds_tx Change Corrected external feedback mode. (VHDL Verilog HDL) Fixed counter initial value match post place route dynamic value. (VHDL Verilog HDL) Fixed output instead when areset high. (VHDL Verilog HDL) Fixed type mismatch error that's only observed SCIROCCO. (VHDL) Synchronous changes with gate-level model. (VHDL Verilog HDL) Fixed reset connection HSSI_TX. (VHDL) Used time variable (64bits) store simulation time instead using integer bits). (Verilog HDL) Status ports ZERO, DENORMAL, INDEFINITE will used. (VHDL Verilog HDL) Fixed incorrect output Stratix device LVDS receiver when input clock slipped bit. (VHDL Verilog HDL) Added support mode APEX devices. (VHDL Verilog HDL) Stratix devices, registered with Global clock instead being connected reset port. (Verilog HDL) Added support mode APEX devices. (VHDL Verilog HDL)
altclklk altfp_mult altlvds_rx
Models
Model lpm_clshift lpm_divide Change Fixed overflow output "arithmetic shift" operation. (Verilog HDL) Modified model support division. (Verilog HDL) Changed quotient remainder output undefined denominator zero. (Verilog HDL)
Altera Corporation
Quartus Software Release Notes
Version
Latest Known Quartus Software Issues
known software issues after publication this version Quartus Software Release Notes, please look information Quartus Latest Known Issues section Altera Support Knowledge Database following URL:
Copyright 2003 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, mask work rights, copyrights.
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