AD6650 diversity, baseband receiver GSM/EDGE. This narrow band receive

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

AD6650 diversity, baseband receiver GSM/EDGE. This narrow band receive

Datasheet Thumbnail

Top Searches for this datasheet

Diversity Baseband GSM/EDGE Narrowband Receiver Preliminary Technical Data AD6650
AD6650 diversity, baseband receiver GSM/EDGE. This narrow band receiver consists integrated DVGA, IF-to-baseband demodulators, lowpass filtering, dual wideband ADC. chip accommodate input frequencies from MHz. This receiver architecture designed such that only external filter(one main diversity) required entire signal path meet GSM/EDGE blocking requirements. Digital decimation filtering circuitry embedded chip generate serial output data streams. decimating filters remove unwanted signals noise outside channel interest. addition, programmable Coefficient filters allow anti-aliasing, matched filtering, static equalization functions combined single, costeffective filter. AD6650 part complete GSM/EDGE receive transmit chipset. Other components this chipset are: amplifier/mixers, receive transmit frequency hopping synthesizers, baseband transmit modulator ramping chip.
Digital Demodulators Active Pass Filters Dual Wideband Programmable Decimation Channel Filters Phase Locked Loop Circuitry Serial Data Output Ports Frequencies 70-300MHz Noise Figure Input Input Volt CMOS Core Microprocessor Interface JTAG Boundary Scan
APPLICATIONS
GSM/EDGE Single Carrier Diversity Receivers Micro Pico Cell Systems Wireless Local Loop Smart Antenna Systems Software Radios Building Wireless Telephony
Figure AD6650 Functional Block Diagram
02/27/03
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 2003 Analog Devices, Inc. rights reserved.
Preliminary Technical DatTABLE CONTENTS
AD6650
0x07: 0x08: 0x09: Control.xx 0x0A: Dither Control.xx 0x0B: Correction BW.xx 0x0C: Correction Control.xx 0x0D-0x14: Control[7:0].xx 0x15: Start Hold-Off Counter.xx 0x16: CIC4 Decimation.xx 0x17: CIC4 Scale.xx 0x18: Control Register.xx 0x19: Decimation Register.xx 0x1A: Decimation Phase.xx 0x1B: Coefficient Offset.xx 0x1C: Taps.xx 0x1D: Scale Register.xx 0x1E-0x1F: BIST A-I/Q.xx 0x20-0x21: BIST B-I/Q.xx 0x22: Serial Control Register.xx 0x23-0x29: Reserved.xx 0x30-0x5F: Coefficient Memory.xx 0x60-0xFF: Reserved.xx MICROPORT CONTROL External Memory Access Control Register (ACR) External Memory Channel Address Register (CAR) SOFT_SYNC Control Register PIN_SYNC Control Register SLEEP Control Register Data Address Registers Write Sequencing Read Sequencing Read/Write Chaining Intel Nonmultiplexed Mode (INM) Motorola Nonmultiplexed Mode (MNM) PORT CONTROL JTAG BOUNDARY SCAN INTERNAL WRITE ACCESS Write Pseudocode INTERNAL READ ACCESS Read Pseudocode OUTLINE DIMENSIONS
FEATURES PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS/CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS FUNCTION DESCRIPTIONS ARCHITECTURE EXAMPLE FILTER RESPONSE LOOP.xx CORRECTION.xx FOURTH ORDER CASCADED INTEGRATOR COMB FILTER CIC4 Rejection INFINITE IMPULSE RESPONSE COEFFICIENT FILTER Decimation Register Decimation Phase Filter Length Output Scale Factor Control Register
USER-CONFIGURABLE BUILT-IN SELF-TEST
CHANNEL BIST.xx CHIP SYNCHRONIZATION Start SERIAL OUTPUT DATA PORT Serial Output Data Format Serial Data Frame (Serial Master) Serial Data Frame (Serial Cascade) Configuring Serial Ports Serial Port Data Rate Serial Slave Operation Serial Ports Cascaded Serial Output Frame Timing (Master Slave) Serial Port Timing Specifications SCLK SDO0 SDO1 SDFS Serial Word Length SDFS Mode Mapping Data BIST Registers 0x00: Clock Divider Control 0x01-0x05: Register[4:0] 0x06: Clamp Control.xx
REV. 02/27/2003
Preliminary Technical DatAC Specifications
Parameter Overall Function Frequency Range Gain Control Gain Step Size Gain Step Accuracy Baseband Filters Group Delay Bandwidth Phase Noise: 200KHz Offset 400KHz Offset 600KHz Offset 800KHz Offset 1600KHz Offset 3000KHz Offset Temp Test Level AD6650BBC
AD6650
Units
.094
Step
3.36
-108 -120
3.64
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Gain Gain Noise Figure1 Input Input Image Rejection FullScale Input Power Input Impedance Gain Gain Noise Figure1 Input Input Image Rejection FullScale Input Power Input Impedance Gain Gain Noise Figure1 Input Input Image Rejection FullScale Input Power Input Impedance Gain Gain Noise Figure1 Input REV. 02/27/2003
10.25 200+jx
10.25 200+jx
10.25 200+jx
10.25
Preliminary Technical DatInput Image Rejection FullScale Input Power Input Impedance Gain Gain Noise Figure1 Input Input Image Rejection FullScale Input Power Input Impedance 200+jx
AD6650
10.25 200+jx
This Measurement applies Maximum Gain (+36
REV. 02/27/2003
Preliminary Technical DatDIGITAL SPECIFICATIONS
(TMIN TMAX, AVDD, CLKVDD, DVDD +3.3v, unless otherwise noted) Test Parameter Temp Level VDDIO AVDD TAMBIENT AD6650BBC
AD6650
Units
ELECTRICAL CHARACTERISTICS
Parameter (Conditions) LOGIC INPUTS Logic Compatibility Logic Voltage Logic Voltage Logic Current Logic Current Input Capacitance LOGIC OUTPUTS Logic Compatibility Logic Voltage (IOH=0.25mA) Logic Voltage (IOL=0.25mA) SUPPLY CURRENT CLK=104 (GSM Example) IVDD IVDDIO IAVDD POWER DISSIPATION CLK=104 GSM/EDGE Example Temp Full VDD-0.9 Full Full Full +25°C 3.3VCMOS/TTL VDD-0.2 Test Level AD6650BBC 3.3V CMOS Units
REV. 02/27/2003
Preliminary Technical DatGENERAL TIMING CHARACTERISTICS
Parameter (Conditions) Timing Requirements: tCLK Period tCLKL Width tCLKH Width High /RESET Timing Requirements: tRESL /RESET Width SYNC Timing Requirements: SYNC Setup Time SYNC Hold Time Master Mode Serial Port Timing Requirements (SBM=1): Switching Characteristics2 tDSCLK1 SCLK Delay (divide tDSCLKH SCLK Delay (for other divisor) tDSCLKL SCLK Delay (divide even tDSCLKLL SCLK Delay (divide tDSDFS SCLK SDFS Delay tDSDO SCLK Delay tDSD1 SCLK Delay tDSDR SCLK Delay Slave Mode Serial Port Timing Requirements (SBM=0): Switching Characteristics2 tSCLK SCLK Period tSCLKL SCLK time (when SDIV=1, divide tSCLKH SCLK high time (when SDIV=1, divide tDSDO SCLK Delay tDSD1 SCLK Delay DSDR SCLK Delay Input Characteristics tSSF SDFS SCLK Setup Time tHSF SDFS SCLK Hold Time Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Test Level
AD6650
tCLK tCLK AD6650 Units
13.4
3.25 3.02 16.0 -1.15
14.0
Timing Specifications valid over range 3.0V 3.6V VDDIO range 3.0V 3.6V. timing parameters SCLK, SDFS, SDO0, SDO1, apply both channels Slave serial port's (SCLK) operating frequency limited MHz. Specification pertains control signals: (/WR), /DS, (/RD), (CLOAD=40pF outputs unless otherwise specified)
REV. 02/27/2003
Preliminary Technical DatMICROPROCESSOR PORT TIMING CHARACTERISTICS
Temp MICROPROCESSOR PORT, MODE (MODE=0) MODE Write Timing: Control3 Setup Time Control3 Hold Time tHWR /WR(RW) RDY(/DTACK) Hold Time tSAM Address/Data /WR(RW) Setup Time tHAM Address/Data RDY(/DTACK) Hold Time tDRDY /WR(RW) RDY(/DTACK) Delay tACC /WR(RW) RDY(/DTACK) High Delay MODE Read Timing: Control3 Setup Time Control3 Hold Time tSAM Address /RD(/DS) Setup Time tHAM Address Data Hold Time Data Tri-state Delay RDY(/DTACK) Data Delay tDRDY /RD(/DS) RDY(/DTACK) Delay tACC /RD(/DS) RDY(/DTACK) High Delay MICROPROCESSOR PORT, MODE (MODE=1) Test Level AD6650
AD6650
Units
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Temp
Test Level
-0.5 4*tCLK 4*tCLK AD6650
5*tCLK
Units
7*tCLK
MODE Write Timing: Full Control3 Setup Time Full Control Hold Time tHDS Full /DS(/RD) /DTACK(RDY) Hold Time tHRW RW(/WR) /DTACK(RDY) Hold Time Full tSAM Address/Data RW(/WR) Setup Time Full -0.5 tHAM Address/Data RW(/WR) Hold Time Full tDDTACK /DS(/RD) /DTACK(RDY) Delay Full tACC RW(/WR) /DTACK(RDY) Delay Full 4*tCLK MODE Read Timing: Full Control3 Setup Time Full Control3 Hold Time tHDS Full /DS(/RD) /DTACK(RDY) Hold Time tSAM Address /DS(/RD) Setup Time Full tHAM Address Data Hold Time Full Data Tri-State Delay Full /DTACK(RDY) Data Delay Full tDDTACK /DS(/RD) /DTACK(RDY) Delay Full tACC /DS(/RD) /DTACK(RDY) Delay Full 4*tCLK MODE Timing: tDSCL Full Delay tDSDA Full Delay tSSCL5 Full Delay Timing Specifications valid over range 3.0V 3.6V VDDIO range 3.0V 3.6V. timing parameters SCLK, SDFS, SDO0, SDO1, apply both channels Specification pertains control signals: (/WR), /DS, (/RD), (CLOAD=40pF outputs unless otherwise specified) There hold time because this waits negative transition transition.
5*tCLK
7*tCLK
REV. 02/27/2003
Preliminary Technical DatTIMING DIAGRAMS
RESET
AD6650
Figure Reset Timing Requirements
tDSCLKH SCLKH SCLK tSCLKL
Figure SCLK Switching Characteristics (Divide
tDSCLKH
tDSCLKL
SCLK
Figure SCLK Switching Characteristics (Divide EVEN integer)
tDSCLKH
tDSCLKLL
SCLK
Figure SCLK Switching Characteristics (Divide integer)
REV. 02/27/2003
Preliminary Technical DatTIMING DIAGRAMS
SCLK tDSDFS SDFS tSSI tHSI DATAn
AD6650
Figure Serial Port Switching Characteristics
tDDR
Figure CLK, Switching Characteristics
SCLK
DSDR
Figure SCLK, Switching Characteristics
SCLK
SDFS
Figure SDFS Timing Requirements (SBM=0)
REV. 02/27/2003
Preliminary Technical DatTIMING DIAGRAMS
AD6650
SYNC
Figure SYNC Timing Inputs
TIMING DIAGRAMS Microport Mode
(/DS)
tSAM
A[2:0]
tSAM
Valid Address
D[7:0]
Valid
(/DTACK)
Notes: Access depends Address accessed. Access easured from requires axim periods
Figure Microport Write Timing Requirements.
(/DS)
tSAM
A[2:0]
Valid
Valid Address
D[7:0]
(/DTACK)
Notes: Access depends Address accessed. Access time easured from RDY. requires axim periods applies A[2:0]=7,6,5,3,2,1
Figure Microport Read Timing Requirements.
REV. 02/27/2003
Preliminary Technical DatTIMING DIAGRAMS Microport Mode
AD6650
(/RD)
tSAM A[2:0] tSAM D[7:0] Valid Data Valid Address
DTAC /DTACK (RDY)
Notes: Access depends Address accessed. Access measured from /DTACK. requires maximum periods
Figure Microport Write Timing Requirements.
(/RD)
A[2:0] Valid Data Valid Address
D[7:0]
/DTACK (RDY)
Notes: Access depends Address accessed. Access easured from /DTACK. requires aximum periods
Figure Microport Read Timing Requirements.
REV. 02/27/2003
Preliminary Technical DatABSOLUTE MAXIMUM RATINGS1
Supply Voltage.-0.3V 3.3v Input Voltage.-0.3 3.6V Output Voltage Swing.-0.3V VDDIO +0.3V Load Capacitance.200pF Junction Temperature Under Bias.+125°C Storage Temperature Range.-65°C +150°C Lead Temperature sec).+280°C Notes
AD6650
Stresses greater than those listed above cause permanent damage device These stress ratings only; functional operation devices these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Thermal Characteristics
121-Pin Ball Grid Array: JA=28.1°C /Watt, airflow JA=XX°C/Watt, 200-lfpm airflow Thermal measurements made horizontal position 4-layer board.
EXPLANATION TEST LEVELS
100% Production Tested. 100% Production Tested 25°C, Sampled Tested Specified Temperatures. Sample Tested Only Parameter Guaranteed Design Analysis Parameter Typical Value Only 100% Production Tested 25°C, Sampled Tested Temperature Extremes
ORDERING GUIDE
Package Model Temperature Range Package Description Option AD6650BBC1 121- Ball Grid Array -40°C +85°C (Ambient) AD6650/PCB Evaluation Board with AD6650 Software Notes X-Grade Material Pre-Production material, normally shipped during product characterization qualification.
SENSITIVITY
AD6650 (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD6650 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
REV. 02/27/2003
Preliminary Technical DatPin Configuration
DVDD DVDD DVDD DVDD DVDD DVDD
AD6650
AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD VREF
/TRST TCLK DVDD DGND DGND DGND DGND DGND DVDD
/RESET SYNC DVDD DGND DGND DGND DGND DGND DVDD
/CLK
/BIN
DGND SDFS SCLK
AVDD AVDD DVDD AVDD DGND AVDD DGND AVDD DGND AVDD DGND AVDD DGND AVDD DVDD AVDD
AGND AGND
AGND AGND AGND AGND AGND AGND AGND AGND AGND XVCOB AGND AGND AGND AGND AGND AGND
/DTACK DVDD
AGND XVCO AGND
/AIN
DGND
MODE1 CHIP_ID1 AVDD REFGND REFT AGND
MODE2 MODE0 CHIP_ID0 AVDD
Function
REFB AGND AGND
Pins
Function Descriptions Name Type POWER SUPPLY DVDD AVDD DGND AGND INPUTS /RESET SYNC CHIP_ID[1:0] SERIAL DATA PORT SCLK SDFS MICROPORT/SERIAL CONTROL
3.3V Digital Core/IO Supply 3.3V Analog Supply Digital Ground Analog Ground Active Reset Synchronizes Digital Filters loop
Chip
Bi-directional Serial Clock Bi-directional Serial Data Frame Sync Serial Data Output Serial Data Output Output Data Ready Indicator Bi-directional Microport Data Microport Address Bits Microport Adress Chip Select Active Data Strobe (Active Read) Active Data Acknowledge (Microport Status Bit) Read Write (Active Write) Selects Control Port Mode Test Reset Test Clock Input Test Mode Select Input
D[7:0]
I/O/T I/O/T I/O/T I/O/T I/O/T
A[2:1] /DS(/RD) /DTACK(RDY) RW(/WR) MODE[2:0] JTAG /TRST TCLK REV. 02/27/2003
Preliminary Technical DatTDO Analog Inputs Ain/ Bin/ Inputs CPOut XVCO XVCOB REFT; REFB; VREF REFGND Clock Inputs CLK/ Test Data Output Test Data input Main Analog Input Complement AIN, differential analog input Diversity Analog Input Complement BIN, differential analog input Charge Pump Loop Filter External Input Connection required internal used] External Input Complement connection required internal used] Internal Voltage Reference; bypass ground with capacitor[3]; Schematic Proper hook-up Ground Reference; Schematic Proper hook-up Encode Input, conversion initiated rising edge Complement Encode Connect
AD6650
REV. 02/27/2003
Preliminary Technical DatARCHITECTURE
AD6650 mixed-signal received signal processor intended direct sampling radios requiring high symbol rate. been optimized demanding filtering requirements EDGE. AD6650 five signal processing stages: digital VGA, Demodulators, Order Pass Filters, dual wideband ADC, Digital Filtering Control Stage. Programming control accomplished serial microprocessor interfaces. DVGA gain ranging digital used extend dynamic range input signal prevent signal clipping input. Demodulators Frequency translation accomplished with demodulators. Real data entering this stage separated into in-phase quadrature components. This stage translates input signal from intermediate frequency (IF) baseband frequency. Pass Filters Following frequency translation Order Pass Active Filter with Bandwidth calibration. Dual ADCs implemented providing dual track holds front AD9238 core. front each operating MSPS. VCO/PLL voltage controlled oscillator phase locked loop circuit generates appropriate frequency demodulators. DIGITAL FILTERS Following analog frequency translation fourth order Cascaded Integrator Comb (CIC4) filter whose response defined decimation rate. Stage Next final stage sum-of-products filter with programmable 20-bit coefficients, decimation rates programmable from Coefficient filter (RCF Functional Block Diagram) handle maximum taps. overall filter response AD6650 composite decimating. Each successive filter stage capable REV. 02/27/2003
AD6650
narrower transition bandwidths requires greater number cycles calculate output. More decimation first filter stage will minimize overall power consumption. Data from chip interfaced high-speed synchronous serial port.
Theory Operation
LOOP consists three gain control loops; slow loop following ADC, Fast Attack (FA) loop following base band filter, Fast Decay (FD) loop following decimation filters.
Slow Loop slow loop main loop `Loop gain' parameter (p41) associated with This parameter controls rate change gain should always less than default loop gain used 1/256. slow loop attempts maintain signal entering given level, which referred `Requested level' (p5). This level specified loop dBFS. This level between 0dBFS -24dBFS converter .094dB resolution. default value -6.02 dBFS. slow loop `peak detect' function, period which user (p1). This `peak detect' period symbol period greater prevent loop from gaining envelope EDGE signal. This works since Peak Detector works function dB(max(|I|,|Q|)) which reflects samples back into quadrant plane. 26MHz sampling frequency, symbol period turns clock cycles; therefore, obtain peak detect period symbol, period should samples. Fast Attack Loop loop based analog threshold detector that prevents overdrive analog signal path. situation that could potentially overdrive converter, loop takes over from slow loop decreases gain front end. step size used loop programmable between 1.504dB .094 steps(p0). loop also counter, which programmable between When initialized `Count+1', loop decreases gain `Count+1' clock cycles when threshold crossed.
Preliminary Technical
AD6650
scale factor, SCIC4 programmable unsigned integer between serves control attenuation data into CIC4 stage increments. best dynamic range, SCIC4 should smallest value possible (lowest attenuation) without creating overflow condition.
ceil
output rate this stage given equation
SAMP
Fast Decay Loop Fast Decay (FD) loop fast loop that increases gain when signal falls below threshold during deep channel fade Ramp Down. fast loop accomplishes this task looking outputs. first peak signal plus blocker level output (which includes signal blockers that passed through filter). second peak signal level after decimation filters Blocker Reject Filter have attenuated blockers. There programmable levels that determine when this loop activated: Signal Plus Blocker level (SPB_level) Signal level (SIG_level). Both these levels defined dBFS. Default values stand -40dBFS SPB_level 60dBFS SIG_level. When `wideband' signal below level (p12) `narrowband' information below Signal level (p13), loop activated. This loop overrides slow loop programmable step size (p7) (currently 0.094dB) programmable peak detect period (p6) currently samples 1.08MHz.
ADCOUTPUT
CIC4 Rejection Table illustrates amount bandwidth percentage clock rate that protected with various decimation rates alias rejection specifications. maximum input rate into CIC4 MHz, mentioned above. Table these bandwidth characteristics CIC4. Table CIC4 Alias Rejection Table
FOURTH ORDER CASCADED INTEGRATOR COMB FILTER
CIC4 processing stage implements sharp fixedcoefficient decimating filter, which driven Analog Digital converter. maximum input rate into this filter ADCOUTPUT, which cannot exceed MHz. decimation ratio, MCIC4, programmed from (all integer values). frequency response filter given Equation gain passband droop CIC4 should calculated these equations. Both parameters compensated stage.
REV. 02/27/2003
2.602 2.311 2.078 1.889 1.731 1.597 1.483 1.384 1.297 1.221 1.153 1.092 1.037 0.988 0.943 0.902 2.602 0.830 0.798 0.768 0.741
2.751 2.444 2.199 1.998 1.831 1.690 1.569 1.464 1.373 1.292 1.220 1.156 1.098 1.045 0.998 0.954 2.751 0.878 0.844 0.813 0.784
2.867 2.547 2.291 2.083 1.909 1.761 1.635 1.526 1.431 1.346 1.272 1.205 1.144 1.090 1.040 0.995 2.867 0.915 0.880 0.847 0.817
2.957 2.627 2.364 2.148 1.969 1.817 1.687 1.575 1.476 1.389 1.312 1.243 1.181 1.124 1.073 1.027 2.957 0.944 0.908 0.874 0.843
3.027 2.690 2.420 2.200 2.016 1.861 1.728 1.613 1.512 1.423 1.344 1.273 1.209 1.152 1.099 1.051 3.027 0.967 0.930 0.896 0.864
-100 3.080 2.737 2.463 2.239 2.052 1.894 1.759 1.641 1.539 1.448 1.368 1.296 1.231 1.172 1.119 1.070 3.080 0.985 0.947 0.912 0.879
Preliminary Technical Dat29 0.715 0.691 0.669 0.648 0.757 0.732 0.708 0.686 0.789 0.763 0.738 0.715 0.814 0.787 0.762 0.738 0.834 0.806 0.780 0.756 0.849 0.820 0.794 0.769
AD6650
required processing delay. This data stored 0x19 2-bit number. Filter Length maximum number taps this filter calculate, Ntaps, given equation below. value Ntaps-1 written channel register within AD6650 address 0x1B.
This table helps calculate upper bound decimation, MCIC4, given desired filter characteristics.
INFINITE IMPULSE RESPONSE FILTER
filter AD6650 order low-pass filter with Infinite Impulse response. Z-Transform coefficients this filter shown below.
taps SAMPIIR
coefficients located addresses 0x40 0x6F interpreted 20-bit complement numbers. When writing coefficient RAM, lower addresses will multiplied relatively older data from higher coefficient addresses will multiplied relatively newer data from IIR. coefficients need symmetric coefficient length, Ntaps, even odd. coefficients symmetric, then both sides impulse response must written into coefficient RAM. stores data from into 46x24 RAM. 23x24 assigned data 23x24 assigned data. uses circular buffer, that difficult know which address particular data element stored. avoid start-up transients undefined data values, data should cleared upon initialization. When triggered calculate filter output, starts multiplying oldest value data first coefficient, which pointed Coefficient Offset Register (0x1A). This value accumulated with products newer data words multiplied subsequent locations coefficient until coefficient address RCFOFF +Ntaps-1 reached. Coefficient Address =(Ntaps Impulse Data Response h(0) N(0) oldest h(1) N(1) h(2) N(2) newest Table Three-tap Filter
xx_trunc)
0.012895 0.254698 1.026276
0.046227 0.278961 0.76021 1.208472
COEFFICIENT FILTER
final signal processing stage sum-of-products decimating filter with programmable coefficients, Figure data memories I-RAM Q-RAM store most recent complex samples from previous filter stage with 23bit resolution. coefficient memory, CMEM, stores coefficients with 20-bit resolution. every cycle, calculated using same coefficients. output consists 24-bit data bits. Decimation Register Each channel used decimate data rate. decimation register register decimate from decimation stored 0x18 form MRCF-1. input rate fSAMPIIR. Decimation Phase Register AD6650 filter channel uses value stored this register pre-load counter. Therefore instead starting from counter loaded with this value, thus creating offset processing that should equivalent
Coefficient Offset register used purposes. main purpose this register allow multiple filters loaded into memory selected simply changing offset pointer rapid filter changes. other this register form part symbol timing adjustment. desired filter length padded with zeros ends, then starting point adjusted form slight delays when filter computed with reference high-speed clock. This allows vernier adjustment symbol timing. Course adjustments made with Decimation Phase.
REV. 02/27/2003
Preliminary Technical DatThe output rate this filter determined output rate stage MRCF.
AD6650
Output Scale Factor Control Register Register 0x1C used configure scale factor filter. This register used scale output data increments. possible output scales range from
SAMPR
SAMPIIR
Rejection,
CIC4 Response, Mcic4
9.75
3.25
3.25
9.75
Offset from Channel Center,
1.98 1.46 0.94
Composite Digital Response with Rate
Gemini Digital Composite Response CIC4 Response Filter Response
0.43 Frequency
0.61
1.13
1.65
2.17
REV. 02/27/2003
Preliminary Technical DatSERIAL OUTPUT DATA PORT
AD6650 configurable serial output ports (SDO0, SDO1). Both ports must configured same programmed using same control register. ports also share common SFDS, SCLK, connection external ASIC DSP. such, outputs configured either serial master serial slave, cannot programmed independently. Serial Output Data Format AD6650 utilizes normal linear binary data format with serial data frame word lengths 24-bit precision. this mode, data shifted device Endian format (MSB first). Serial Data Frame Sync (Serial Master) serial data frame initiated with Serial Data Frame Sync (SDFS). each channel within AD6650 completes filter cycle, data transferred into serial data buffer. Serial Master (SBM) mode, internal serial controller initiates SDFS next rising edge serial clock. AD6650, there modes which frame sync generated Serial Master. case where both input channels processed through SDO0 only, there four modes, when input channels output through SDO0 SDO1 respectively, there three modes operation (mode same). These modes described section SDFS Modes. Serial Data Frame (Serial Cascade) AD6650 serial outputs operated serial cascade mode (serial slave). this mode, selected AD6650 channel requires that external device such issue serial clock SDFS. operate successfully serial cascade mode, must have some indication that AD6650 channel's serial buffer ready send data. This indicated assertion This should tied interrupt flag DSP. this manner, will know when service serial port. When begins handling serial service, serial port should configured such that SDFS asserted clock cycle prior shifting data. such, AD6650 channel samples SFDS rising edge serial clock. next rising edge serial clock AD6650 serial port begins shifting data until specified number bits have been shifted. Configuring Serial Ports Both Serial Output Ports either function Master Slave, they cannot independently. Serial Master will provide SCLK SDFS outputs. Serial Ports will always default serial slaves when RESET taken low, REV. 02/27/2003
AD6650
Serial Ports programmed become master setting serial control register high. Serial Port Data Rate Serial Ports defined master, SCLK frequency defined Equation fCLK frequency master clock AD6650 channel SDIV Serial Division word channel. SDIV Serial Port programmed internal control register 0x22.
Serial Slave Operation AD6650 also operated serial slave. this configuration, shown Figure serial clock provided asynchronous with AD6650 clock input data this mode clock maximum frequency must fast enough read entire serial frame prior next frame coming available. AD6650 output derived (via Decimation/Interpolation Rates) from input sample rate, user determine output rate. output rate AD6650 given below. Serial Ports Cascaded Serial output ports cascaded AD6650. This allows data shifted master slave channel parallel. accomplish this, SDFS signal master channel drives SDFS input slave channel Using AD6650 master/slave mode permits shift data from master AD6650 serial port, parallel with frame data words) from AD6650 slave port. shown Figure Master Port Serial Port Slave Port Serial Port from another AD6650. only limit number ports that cascaded comes from serial bandwidth fan-out considerations. There must enough Serial Clock cycles available shift necessary data into DSP, SCLK (common channels DSP) must closely monitored ensure that clean signal. Serial Output Frame Timing (Master Slave) SDFS signal transitions accordingly depending whether part Master (SBM Figure Slave (SBM Figure mode. next rising edge SCLK after this occurs will drive first serial data pin. falling edge SCLK subsequent rising edge then used sample data until required number bits received (determined serial output port word length). ability count bits, will know when complete frame received.
Preliminary Technical DatSerial Port Timing Specifications Whether AD6650 serial channel operated Serial Master Serial Slave, serial port timing identical. Figures indicate required timing each specification.
tSCLK tSCLKH SCLK tSCLKL
SCLK
AD6650
SDFS
SDFS minimum width SCLK
First data available first rising SCLK after SDFS goes high
Figure Timing Serial Output Port (SBM=1)
Figure SCLK Timing Requirements
tDSCLKH
tSCLKH
SCLK SCLK output when high; SCLK input when serial slave mode. outputs switched rising edge SCLK. SDFS sampled falling edge SCLK. This allows AD6650 recognize SDFS time initiate frame very next SCLK rising edge. maximum speed this port MHz. Serial Data Output. Serial output data shifted rising edge SCLK. very next SCLK rising edge after SDFS, data from channel shifted. every subsequent SCLK edge piece data shifted until last data shifted out. last data shifted Channels data. three-stated when serial port outside time-slot. This allows AD6650 share SDIN with other AD6650s other devices.
SCLK
tSCLKL
Figure SCLK Switching Characteristics (Divide
tDSDO
SCLK
Figure Serial Output Data Switching Characteristics
SCLK
SDFS
SDFS SDFS Serial Data Frame Sync signal. SDFS output when high master mode. SDFS input when slave mode. SDFS sampled falling edge SCLK. When sampled low, AD6650 serial port will function serial slave. this mode, port silent until issues frame sync. When AD6650 detects SDFS falling edge DSP-generated serial clock, next rising edge serial clock, AD6650 enables output driver shifts word. Data shifted until word been sent. When sampled high, chip functions serial master. this mode, AD6650 responsible generating serial control data. Four modes that operation channel address 0x22 Bits 6-5. Serial Word Length register 0x22 determine length serial word this `0,' each word bits bits bits this `1,' serial words bits wide.
Figure SDFS Timing Requirements (SBM=0)
REV. 02/27/2003
Preliminary Technical DatSDFS Modes mentioned section above, Serial Data Frame Sync, there either modes operation depending output AD6650 configured. Setting register 0x22 high indicates that input channel data output SDO0 input channel output SDO1. this condition there modes operation (There technically modes, mode same): Mode (0x22 Bits 6-5:00; 7:1): SDFS valid complete clock cycle prior data shift. This single pulse valid output channel SDO0 SDO1. next clock cycle, AD6650 begins shifting digitally processed data stream. Depending precision serial configuration, either bits data shifted out, followed bits data. Mode (0x22 Bits 6-5:10; 7:1): Since both SDO0 SDO1 used, SDFS pulses high clock cycle prior data also pulses high clock cycle prior data each corresponding input channel. this mode, there will SFDS pulses each output channel. Mode (0x22 Bits 6-5:11; 7:1): SDFS high entire time that valid bits being shifted. SDO0 this will either bits data, followed bits data corresponding input channel SDO1, SDFS remains high bits data, followed bits data corresponding input channel SDFS goes high complete clock cycle before first shifted AD6650. Setting register 0x22 indicates that input channel data will output SDO0 only. this condition there modes operation: Mode (0x22 Bits 6-5:00; 7:0): SDFS valid complete clock cycle prior data shift. There only single pulse both input channels. next clock cycle, AD6650 begins shifting digitally processed data stream onto SDO0. Depending precision serial configuration, either bits data, followed bits data shifted corresponding input channel then either bits data, followed bits data corresponding input channel shifted out. Mode (0x22 Bits 6-5:01; 7:0): SDFS goes high clock cycle prior actual data associated with analog input channel When data stream complete, second SDFS inserted clock cycle prior shift data associated with analog input channel Mode (0x22 Bits 6-5:10; 7:0): SFDS will high complete clock cycle prior data second SDFS inserted clock cycle prior shift first bit, both corresponding channel input data. third fourth SDFS inserted clock cycle prior shift data REV. 02/27/2003
AD6650
respectively, which corresponds input channel data. this mode there will total SFDS pulses. Mode (0x22 Bits 6-5:11; 7:0): SDFS high entire time that valid bits being shifted, goes high complete clock cycle before first shifted AD6650. SDO0 there will either bits data, followed bits data, then bits data, followed bits data corresponding input channel respectively.
MICROPORT CONTROL
AD6650 8-bit microprocessor port serial input ports. each these ports described separately below. interaction ports then described. Microport interface multi-mode interface that designed give flexibility when dealing with host processor. There modes operation: Intel nonmultiplexed mode (INM), Motorola non-multiplexed mode (MNM). mode selected based host processor which mode best suited that processor. micro-port 8-bit data (D[7:0]), 3-bit address bus(A[2:0]), control pins lines (/CS, /RD, /WR), status (DTACK RDY). functionality control signals status line changes slightly depending upon mode that chosen. Refer timing diagrams following descriptions details operation both modes. External Memory External Memory used gain access Channel Address Space. 8-bit data address buses used registers that seen following table. These registers collectively referred External Interface Registers since they control accesses Channel Address space well global chip functions. each these individual registers described below detail.
Preliminary Technical DatExternal Memory
A[2:0] Name Access Control Register (ACR) Comment Auto Increment Broadcast 5-2: Instruction[3:0] 1-0: A[9:8] 7-0: A[7:0]
AD6650
Microport Instructions
Instruction 0000 0001 0010 0100 1000 Comment: Chips will access. Chips will access. Chips will access. Chips will access. Chips with Chip_ID[0] =xxx will access.1 Chips with Chip_ID[0] xxx1 will access.1 Chips with Chip_ID[1:0] xx00 will access.1 Chips with Chip_ID[1:0] xx01 will access.1 Chips with Chip_ID[1:0] xx10 will access.1 Chips with Chip_ID[1:0] xx11 will access.1
Channel Address Register (CAR) Special Function Register (SF2)
Special Function Register (SF1) Special Function Register (SF0)
Data Register (DR2) Data Register (DR1) Data Register (DR0)
sync Enable correction sync enable sync enable 3-1: Reserved Issue soft sync First Sync only Enable edge-sensitivity 3-1: Reserved 7-4: Reserved Status Channel Enable Channel Status Channel Enable Channel 7-4: Reserved 3-0: D[19:16] 15-8: D[15:8] 7-0: D[7:0]
1001 1100 1101 1110 1111
A[9:8] bits control which channel decoded access. Table Microport Instructions
Table External Memory Access Control Register (ACR) Access Control Register serves define channel channels that receive access from micro-port port. this register Auto-Increment bit. this then register described below will increment value after every access channel. This allows blocks address space such Coefficient Memory initialized more efficiently. register Broadcast determines bits interpreted. Broadcast should high that bits 5-2, which referred Instruction bits (Instruction [3:0]), allows single multiple AD6650 chip(s) configured simultaneously There possible instructions that defined table below. table represent don't cares digital decoding.
When broadcast enabled (bit high) read back valid because potential internal contention. Therefore, read back subsequently desired, broadcast should low. Bits this register address bits that decode which channels being accessed. Because channels AD6650 cannot programmed independently, these bits should Channel Address Register (CAR) This register represents 8-bit internal address each channel. Auto-Increment then this value will incremented after every access register, which will turn access location pointed this address. Channel Address register cannot read back while Broadcast high. Special Function Registers AD6650 three special function registers, SF0, SF1, that control synchronizing enabling channels. channel enable register, pinsync register, soft-sync register. SF0, bits allow channels respectively come sleep based method selected SF1.Bits read-only indicate whether channels respectively active. indicates channel active indicates active. Bits through unused. SF1, 1,then both channels will wait pulse appear SYNC before coming sleep; otherwise, channels will assume soft start desired wait start hold-off counter issue sync. When set, both channels ignore subsequent attempts resync once they awake. SF2, tells startup block start hold-off counter from value programmed into start hold-off counter control register issue sync when done. Bits
REV. 02/27/2003
Preliminary Technical Dat6 used enable syncs individual blocks channels. Data Address Registers External Address [2-0] form data registers DR2, respectively. internal data words have widths that less than equal bits. Accesses External Address trigger internal access AD6650 based address indicated CAR. Thus during writes internal registers, External Address must written last. this point data transferred internal memory indicated A[9:0]. Reads performed opposite direction. Once address set, External Address DR0must first data register read initiate internal access. only bits wide. Data written upper bits this register will ignored. Likewise reading from this register will produce only LSBs. Write Sequencing Writing internal location achieved first writing upper bits address bits through ACR. Bits select channel indicated above. then written with lower eight bits internal address doesn't matter written before long both written before internal access). Data register (DR2) register (DR1) must written first because write data register triggers internal access. Data register must always last register written initiate internal write. Read Sequencing Reading from micro port accomplished same manner. internal address same write. read from data register activates internal read, thus register must always read first initiate internal read followed DR1and DR2. This provides LSBs internal read through micro port (D[7:0]). Additional data registers read read balance internal memory. Read/Write Chaining micro port AD6650 allows multiple accesses while held (/CS tied permanently micro port shared with additional devices). user access multiple locations pulsing line changing contents external three address bus. External access external registers Table accomplished modes using /CS, /RD, /WR, MODE inputs. access modes Intel Non-Multiplexed mode Motorola Non-Multiplexed mode. These modes controlled MODE input (MODE=0 INM, MODE=1 MNM). /CS, /RD, control access type each mode. REV. 02/27/2003
AD6650
Programming Modes
AD6650 programmed using several different modes. These modes include micro-port modes, Intel Non-Multiplexed mode Motorola Non-Multiplexed Mode, serial port mode, I2C. programming mode selected writing appropriate 3-bit word mode pins. following table identifies which word selects desired mode. Mode [2:0] Comment: Micro-Port Intel Non-Multiplexed Mode Micro-Port Motorola Non-Multiplexed Mode Reserved Reserved Reserved Reserved Reserved
Intel Non-Multiplexed Mode (INM)
Setting mode word bits will enable AD6650 microprocessor mode. access type controlled user with /CS, (/DS), (RW) inputs. (/DTACK) signal produced micro port communicate user that access been completed. (/DTACK) goes start access released when internal cycle complete. timing diagrams both read write modes Specifications.
Motorola Non-Multiplexed Mode (MNM)
Setting mode word bits will enable AD6650 microprocessor mode. access type controlled user with /CS, (/RD), (/WR) inputs. /DTACK (RDY) signal produced micro port communicate user that access been completed. /DTACK (RDY) goes when internal access complete then will return high after (/RD) de-asserted. timing diagrams both read write modes Specifications.
programming selected setting MODE =100. two-line bi-directional serial interface specification developed Phillips that AD6650 uses program control registers/ coefficient memory address space. uses data line (SDA) clock line (SCL) transfer data between master device slave device. AD6650 only slave, master device always needed program mode. data transfers AD6650 comply with Standard-mode transfer, kHz. multi-master and/or multislave relying wired-and function devices connected indicate that free. comply with this, pins AD6650 open-drain
Control
Preliminary Technical Datoutputs, meaning that they drive logic low, logic high. pins tri-state indicate logic-high this pulled high external pull-up resistors provide logic high other devices bus. single-master, single-slave configuration, k-ohm resistor should sufficient each lines. Stable data transferred when high, meaning that only changed when low. transitions while high, this indicates AD6650 that transfer being initiated bus. start condition from master initiates transfer between devices stop condition ends one. START condition signaled transitioning line from high while high transition from high while high indicates STOP condition. Read/Write Acknowledge (ACK) obligatory receiver must send acknowledge back transmitter after each byte transferred. master generates acknowledgerelated clock pulse after given byte transmitted releases line. receiver must pull line stable before high period extra clock pulse signal receipt transmitted byte. Access Once start condition been generated, master must transmit AD6650 1-byte device read/write indicate that rest access follow intended (the read/write together create byte). device AD6650 0010 0000 (hex). Next, master must transmit instruction byte AD6650 indicating type access EIR. Comment: Read/Write SI[2] SI[1] SI[0] A[2] A[1] A[0] Table Instruction Byte
AD6650
being accessed. serial instruction decoded according following table. Function Write byte: A[2:0] determines address Write bytes: Write bytes: Write bytes: ACR, Write bytes: ACR, CAR, Write bytes: ACR, CAR, DR2, DR1, Write bytes: addresses, Write bytes: DR2, DR1, Read byte: A[2:0] determines address Write bytes: Write byte: CAR; then read byte: Write bytes: then CAR; then read byte: Write bytes: then CAR; then read bytes: then Write bytes: then CAR; then read bytes: DR0, DR1, then Read bytes: addresses Read bytes: DR0, DR1, then Table Instructions SI[2:0]
After instruction byte, appropriate data must written read from EIR. Finally, STOP condition sent transfer. Multiplexing Since programming modes AD6650 mutually exclusive, pins used each mode multiplexed together named after their microport function. I2Cmode, microport mode DTACKn microport mode.
Each instruction byte indicates whether being written read (R/Wn), which serial instruction [2:0 being executed which register [2:0 appropriate, REV. 02/27/2003
Preliminary Technical DatAD6650 Memory
Address (Hex) Register Clock Divider Control Register Register Register Register Clamp Control Control Width Definitions Clock_DIV Divide Divide
AD6650
Disable Disable Aux_DACA Aux_DACB 7-5: Current Adjust Enable 3-1: Current Adjust Enable High Dither Power Enable Dither 15-0: Correction Multiply 5-2: Scalar PN_EN Enable Force Gain FD_Enable FA_Enable Slow Loop Enable 8-0: VGA_Gain 15-8 Hysterisis 7-0: Requested Level 10-8: Loop Gain-Exp 7-0: Loop Gain-Mant 12-10: FD_Step-1 9-8: FA_Thresh 7-4: FA_count 3-0: FA_Step-1 15-8: Peak Detect Period 7-0: Peak Detect Period 11-0: FD_S Threshold 11-0: FD_SpB Threshold Start Hold-Off Counter MCIC4-1 CIC4_scale SYNC_MASK MRCF-1 PRCF CORCF NTaps-1 1-0: Scale BIST-I/DATA_I BIST-Q/DATA_Q BIST-I/DATA_I
Dither Control Correction Correction Control
Control
Control Control Control Control
Control Control Control Start Hold-Off Counter CIC4 Decimation CIC4 Scale Control Register Decimation Register Decimation Phase Coefficient Offset Taps Scale Register BIST BIST BIST
REV. 02/27/2003
Preliminary Technical Dat20 BIST Serial Control Register BIST-Q/DATA_Q Data BIST SDO1 data 6-5: I_SDFS Control High SDO0 valid AI,AQ,BI,BQ pulses AI,BI pulses pulse SOWL 24-bit words 16-bit words 2-0: SDIV[2:0]
AD6650
23-3F 40-6F 70-FF
Reserved Coefficient Memory Reserved
48x20
REV. 02/27/2003
Preliminary Technical DatRecommended Applications circuit
AD6650
REV. 02/27/2003
Preliminary Technical DatOutline Dimensions
AD6650
Dimensions shown 121-Pin PBGA
REV. 02/27/2003

AD6650 diversity, baseband receiver GSM/EDGE. This narrow band receive

Top Searches for this datasheet

Other recent searches