1.3GHz 4-Address Synthesiser Supersedes version April 1994 Consum

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SP5502
1.3GHz 4-Address Synthesiser
Supersedes version April 1994 Consumer Handbook, HB3120 DS3031 January 1997
SP5502 single-chip frequency synthesiser designed tuning systems. Control data entered standard format. SP5502 four programmable addresses, which allows more synthesisers used system. device available variants: SP5502F 14lead miniature plastic package (MP14) SP5502S 16lead miniature plastic package (MP16). Features below functional differences between devices.
FEATURES Complete Single Chip System
Programmable Power Consumption (240mW Typ.) Radiation Phase Lock Detector Varactor Drive Disable 20mA Controllable Outputs (SP5502S) 20mA Controllable Outputs (SP5502F) Variable Address Multi-Tuner Applications Protection Normal handling precautions should observed.
APPLICATIONS Cable Tuning Systems VCRs
Fig. connections view
ORDERING INFORMATION
SP5502F MPAS (14-lead miniature plastic package) SP5502S MPAS (16-lead miniature plastic package)
Fig. Block diagram SP5502S. (Ports present SP5502F)
SP5502
ELECTRICAL CHARACTERISTICS
TAMB 10°C 80°C, references SP5502S (MP16 package). These Characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated. Value Characteristic Supply current Prescaler input voltage Prescaler input voltage Prescaler input impedance Prescaler input capacitance SDA, Input high voltage Input voltage Input high current Input current Leakage current Output voltage Charge pump current Charge pump current high Charge pump output leakage current Charge pump drive output current Charge pump amplifier gain Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator negative resistance Output Ports Sink current Leakage current Input Port input current high input current Min. 13,14 13,14 Typ. 6400 6,7,9-11 6,7,9-11 Parallel resonant crystal (note VOUT (see note VOUT Max. mVrms 80MHz 1GHz mVrms Fig. Units Conditions
Input voltage Input voltage When Sink current Byte Byte Byte
NOTES Source impedance between output ports ground approximately This should taken into account when calculating output port saturation voltages. maximum resistance quoted refers conditions, including start-up.
FUNCTIONAL DESCRIPTION (Except where otherwise indicated, `SP5502' refers both variants)
WRITE MODE (FREQUENCY SYNTHESIS)
When device write mode Bytes select synthesised frequency while Bytes select output port states charge pump information. Once correct address received acknowledged, first next Byte determines whether that Byte interpreted Byte logic frequency information logic charge pump output port information. Additional data Bytes entered without need readdress device until stop condition recognised. This allows smooth frequency sweep fine tuning purposes. transmission data stopped mid-byte (i.e., another device bus) then previously programmed byte maintained. Frequency data from Bytes stored 15-bit shift register used control division ratio 15-bit programmable divider which preceded divide-by-8 prescaler amplifier give excellent sensitivity local oscillator input; input impedance shown
SP5502 programmed from BUS. Data Clock lines respectively defined format. synthesiser either accept data (write mode) send data (read mode). Tables Fig. illustrate format data. device programmed respond several addresses, which enables more than synthesiser system. Table shows address selected applying voltage address input shown Fig. address Byte (R/W) sets device into read mode high write mode low. When SP5502 receives correct address Byte pulls line during acknowledge period during following acknowledge periods after further data Bytes programmed. When SP5502 programmed into read mode controlling device accepting data must pull down line during following acknowledge period read another status Byte.
SP5502
programmed frequency calculated multiplying programmed division ratio times comparison frequency FCOMP When frequency data entered, phase comparator, charge pump varactor drive amplifier, adjusts local oscillator control voltage until output programmable divider frequency phase locked comparison frequency. reference frequency generated external source capacitively coupled into provided onchip 4MHz crystal controlled oscillator. Note that comparison frequency when 4MHz reference used. Byte programming data (CP) controls current charge pump circuit, logic 170µA logic 50µA, allowing compensation variable tuning slope tuner also enable fast channel changes over full band. Byte (T0) disables charge pump logic Byte (OS) switches charge pump drive amplifier's output when logic Byte (T1) selects test mode where phase comparator inputs available logic connects FCOMP FDIV Byte programs output ports P0-P2, SP5502S (P1, only SP5502F), logic high impedance output, logic impedance (on).
READ MODE
When device read mode status data read from device line takes form shown Table (POR) power supply device dropped below nominal programmed information lost (e.g., when device initially turned on). when read sequence terminated stop command. outputs high impedance when device initially powered (FL) indicates whether device phase locked, logic present device locked logic device unlocked.
Address Programmable divider Programmable divider Charge pump test bits port control bits
Byte Byte Byte Byte Byte
Table Write data format (MSB transmitted first) Address Status byte Byte Byte
Table Read data format Voltage input Open circuit
Table Address selection MA1, P4*, Acknowledge Variable address bits (see Table Charge Pump current select Test mode selection Charge pump disable Varactor drive Output disable Switch Control output port states Power Reset indicator Phase lock detect flag Don't care valid
NOTES Programmed connecting resistor between Address Select Port VCC. Don't care condition SP5502F. Fig. Data formats
SP5502
APPLICATION
typical application shown Fig. input/output interface circuits shown Fig.
Fig. Typical application
Fig. Typical input sensitivity
SP5502
Fig. SP5502 input/output interface circuits
SP5502
Fig. Typical input impedance
ABSOLUTE MAXIMUM RATINGS
voltages referred Parameter Supply voltage input voltage Port voltage 13,14 6,7, 9-11 6,7, 9-11 6,7, 9-11 13,14 SP5502S SP5502F 11,12 6,8, 6,8, 6,8, 11,12 Storage temperature Junction temperature MP16 thermal resistance, chip-to-ambient MP16 thermal resistance, chip-to-case MP14 thermal resistance, chip-to-ambient MP14 thermal resistance, chip-to-case Power consumption Min. Value Max. °C/W °C/W °C/W °C/W With applied applied Port state Port state Units Conditions
Total port output current input offset Charge pump offset Drive output offset Crystal oscillator offset SDA, input voltage
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1.3GHz 4-Address Synthesiser Supersedes version April 1994 Consum

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