State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Diss

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Diss

Datasheet Thumbnail

Top Searches for this datasheet

SN54ABT126, SN74ABT126 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS
State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation Typical VOLP (Output Ground Bounce) 25°C High-Impedance State During Power Power Down High-Drive Outputs (-32-mA IOH, 64-mA IOL) Latch-Up Performance Exceeds JESD Protection Exceeds 2000 MIL-STD-883, Method 3015; Exceeds Using Machine Model Package Options Include Plastic Small-Outline Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Plastic Ceramic DIPs
SN54ABT126 PACKAGE SN74ABT126 PACKAGE (TOP VIEW)
SN54ABT126 PACKAGE (TOP VIEW)
description
'ABT126 buffer gates feature independent line drivers with 3-state outputs. Each output disabled when associated output-enable (OE) input low. When between device high-impedance state during power power down. However, ensure high-impedance state above should tied through pulldown resistor; minimum value resistor determined current-sourcing capability driver.
internal connection OUTPUT
Copyright 1999, Texas Instruments Incorporated
SN54ABT126 characterized operation over full military temperature range -55°C 125°C. SN74ABT126 characterized operation from -40°C 85°C.
FUNCTION TABLE (each buffer) INPUTS
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC-B trademark Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT126, SN74ABT126 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS
logic symbol
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12. numbers shown packages.
logic diagram (positive logic)
numbers shown packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Voltage range applied output high power-off state, -0.5 Current into output state, SN54ABT126 SN74ABT126 Input clamp current, Output clamp current, Package thermal impedance, (see Note package 127°C/W package 158°C/W package 78°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stressratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output clamp-current ratings observed. package thermal impedance calculated accordance with JESD except through-hole packages, which trace length zero.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT126, SN74ABT126 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
SN54ABT126 t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise fall rate Power-up ramp rate Operating free-air temperature SN74ABT126 UNIT ns/V µs/V
NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER Vhys IOZPU IOZPD IOZH IOZL Ioff ICEX TEST CONDITIONS input Other inputs Outputs high Outputs high Outputs Outputs disabled Outputs enabled Outputs disabled -100 ±100 -200 -200 ±100 -200 0.55 0.55* 0.55 0.55 25°C -1.2 SN54ABT126 -1.2 SN74ABT126 -1.2 UNIT
products compliant MIL-PRF-38535, this parameter does apply. typical values between should less than equal ensure state. more than output should tested time, duration test should exceed second. This increase supply current each input that specified voltage level rather than GND.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT126, SN74ABT126 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS
switching characteristics over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Note Figure
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) 25°C SN54ABT126 SN74ABT126 UNIT
NOTE Limits vary among suppliers.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT126, SN74ABT126 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
From Output Under Test (see Note
LOAD CIRCUIT Input VOLTAGE WAVEFORMS PULSE DURATION
Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES Output Control tPZL Output Waveform (see Note Output Waveform Open (see Note tPZH VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING tPLZ tPHZ
Input tPLH Output tPHL tPHL tPLH Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated

State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Diss

Top Searches for this datasheet

Other recent searches