SYNCHRONOUS DRAM MODULE PC100- PC133-compliant 168-pin, dual in-l
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128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
SYNCHRONOUS DRAM MODULE
PC100- PC133-compliant 168-pin, dual in-line memory module (DIMM) Unbuffered, ECC-optimized pinout 128MB 256MB Single +3.3V power supply Fully synchronous; signals registered positive edge system clock Internal pipelined operation; column address changed every clock cycle Internal SDRAM banks hiding access/precharge Programmable burst lengths: full page Auto Precharge, includes Concurrent Auto Precharge, Auto Refresh Modes Self Refresh Mode 64ms, 4,096-cycle refresh LVTTL-compatible inputs outputs Serial Presence-Detect (SPD) Gold edge contacts
MT9LSDT1672A(I) 128MB MT18LSDT3272A(I) 256MB
latest data sheet, please refer Micron site: www.micron.com/products/modules
Figure 168-Pin DIMM (MO-161)
Standard 1.375in./34.93mm
Profile 1.125in./28.58mm
Options
Marking
Table
Timing Parameters
SETUP TIME HOLD TIME
ACCESS TIME MODULE CLOCK MARKING FREQUENCY -13E -133 -10E 5.4ns 5.4ns 7.5ns
Self-Refresh Standard None Power Package 168-pin DIMM (Standard) 168-pin DIMM (Lead-free) Frequency/CAS Latency 7.5ns (133 MHz)/CL -13E 7.5ns (133 MHz)/CL -133 10ns (100 MHz)/CL -10E Standard (1.375in./34.93mm) note page Low-Profile (1.125in./28.58mm) note page
NOTE: Consult Micron product availability.
Table
Address Table
128MB 256MB (BA0, BA1) 128Mb (A0-A11) (A0-A9) (S0, (BA0, BA1) 128Mb (A0-A11) (A0-A9) (S0,
Refresh Count Device Banks Device Configuration Addressing Column Addressing Module Ranks
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
©2004 Micron Technology, Inc.
PRODUCTS SPECIFICATIONS DISCUSSED HEREIN SUBJECT CHANGE MICRON WITHOUT NOTICE.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Table Part Numbers
MODULE DENSITY 128MB 128MB 128MB 128MB 128MB 128MB 256MB 256MB 256MB 256MB 256MB 256MB CONFIGURATION SYSTEM SPEED
PART NUMBER MT9LSDT1672AG-13E_ MT9LSDT1672AY-13E_ MT9LSDT1672AG-133_ MT9LSDT1672AY-133_ MT9LSDT1672AG-10E_ MT9LSDT1672AY-10E_ MT18LSDT3272AG-13E_ MT18LSDT3272AY-13E_ MT18LSDT3272(L)AG-133_ MT18LSDT3272(L)AY-133_ MT18LSDT3272AG-10E_ MT18LSDT3272AY-10E_
NOTE:
Designators component revision last characters each part number Consult factory current revision codes. Example: MT9LSDT1672G-133B1.
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Table Assignment (168-Pin DIMM Front)
DQMB0 DQMB1 DQMB2 DQMB3 DQ16 DQ17 DQ18 DQ19 DQ20 CKE1 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Table
Assignment (168-Pin DIMM Back)
CKE0 DQMB6 DQMB7 CAS# DQMB4 DQMB5 RAS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SYMBOL SYMBOL SYMBOL SYMBOL DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
SYMBOL SYMBOL SYMBOL SYMBOL DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
Figure 168-Pin DIMM Locations
Front View
Back View (Populated only 256MB module)
Indicates
Indicates
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Table Descriptions
SYMBOL RAS#, CAS#, CK0-CK3 TYPE Input Input DESCRIPTION Command Inputs: RAS#, CAS#, (along with define command being entered. Clock: driven system clock. SDRAM input signals sampled positive edge also increments internal burst counter controls output registers. Clock Enable: activates (HIGH) deactivates (LOW) signal. Deactivating clock provides PRECHARGE POWER-DOWN SELF REFRESH operation (all device banks idle) CLOCK SUSPEND OPERATION (burst access progress). synchronous except after device enters powerdown self refresh modes, where becomes asynchronous until after exiting same mode. input buffers, including disabled during power-down self refresh modes, providing standby power. Chip Select: enables (registered LOW) disables (registered HIGH) command decoder. commands masked when registered HIGH. considered part command code. Input/Output Mask: DQMB input mask signal write accesses output enable signal read accesses. Input data masked when DQMB sampled HIGH during WRITE cycle. output buffers placed High-Z state (twoclock latency) when DQMB sampled HIGH during READ cycle. Bank Address: define which device bank ACTIVE, READ, WRITE, PRECHARGE command being applied. Address Inputs: Provide address ACTIVE commands, column address auto prcharge (A10) READ/WRITE commands, select location memory arrary respective device bank. sampled during PRECHARGE command determines whether PRECHARGE applies device bank (A10 LOW, device bank selected BA0, BA1) device banks (A10 HIGH). address inputs also provide op-code during MODE REGISTER command. Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module. Presence-Detect Address Inputs: These pins used configure presence-detect device. Check Bits. ECC, 1-bit error detection correction. numbers correlate with symbols. Refer Assignment tables page more information NUMBERS 111, 125,
CKE0, CKE1
Input
45,114,
S0#-S3#
Input
112, 113, 130,
DQMB0-DQMB7
Input
BA0,
Input
33-38, 117-121,
A0-A11
Input
165-167 105, 106, 136, 2-5, 7-11, 13-17, 55-58, 65-67, 69-72, 86-89, 91-95, 97-101, 103, 104, 139-142, 144, 149-151, 153-156,158-161
SA0-SA2 CB0-CB7 DQ0-DQ63
Input Input
Input/ Output Input/ Data I/O: Data bus. Output
Input/ Serial Presence-Detect Data: bidirectional used Output transfer addresses data into presencedetect portion module.
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Table Descriptions
SYMBOL TYPE DESCRIPTION numbers correlate with symbols. Refer Assignment tables page more information NUMBERS 102, 110, 124, 133, 143, 157, 107, 116, 127, 138, 148, 152, 108, 109, 126, 132, 134, 135, 145,146,
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
Connected: These pins connected these module.
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Figure Functional Block Diagram Single Rank
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQMB6
2.2µF
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
RAS# CAS# CKE0 A0-A11
RAS#: SDRAMs CAS#: SDRAMs CKE0: SDRAMs WE#: SDRAMs A0-A11: SDRAMs BA0: SDRAMs BA1: SDRAMs
SDRAMs
2.2µF
SDRAMs
3.3pF
CK1,
10pF
Note: resistor values unless otherwise specified. industry standard, Micron modules various component speed grades referenced module part numbering guide www.micron.com/
Standard modules following SDRAM devices: MT48LC16M8A2TG Lead-free modules following SDRAM devices: MT48LC16M8A2TG
support/numbering.html.
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Figure Functional Block Diagram Dual Rank
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
CKE1: SDRAMs CKE0: SDRAMs CAS#: SDRAMs RAS#: SDRAMs WE#: SDRAMs A0-A11: SDRAMs BA0: SDRAMs BA1: SDRAMs
CKE1 CKE0 CAS# RAS# A0-A11
SDRAMs SDRAMs
3.3pF
3.3pF
NOTE: resistor values unless othersise specified.
industry standard, Micron modules various component speed grades referenced module part numbering guide www.micron.com/
Standard modules following SDRAM devices: MT48LC16M8A2TG Lead-free modules following SDRAM devices: MT48LC16M8A2TG
support/numbering.html.
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
General Description
MT9LSDT1672 MT18LSDT3272A modules high-speed CMOS, dynamic random-access, 128MB 256MB DIMMs organized (ECC) configuration. SDRAM modules internally configured quad-bank SDRAM devices with synchronous interface (all signals registered positive edge clock signals). Read write accesses SDRAM modules burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed (BA0, select device bank, A0-A11 select device row). address bits registered coincident with READ WRITE command used select starting column location burst access. SDRAM modules provide programmable READ WRITE burst lengths locations, full page, with burst terminate option. AUTO PRECHARGE function enabled provide selftimed precharge that initiated burst sequence. SDRAM modules internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows column address changed every clock cycle achieve highspeed, fully random access. Precharging device bank while accessing other three device banks will hide precharge cycles provide seamless, high-speed, random-access operation. SDRAM modules designed operate 3.3V, low-power memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs outputs LVTTL-compatible. SDRAM modules offer substantial advances DRAM operating performance, including ability syn-chronously burst data high data rate with automatic column-address generation, ability interleave between internal device banks order hide precharge time capability randomly change column addresses each clock cycle during burst access. more information regarding SDRAM operation, refer 128Mb SDRAM component data sheet. 2,048-bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters. remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals, together with (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) tied ground module, permanently disabling hardware write protect.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. Once power applied VDDQ (simultaneously) clock stable (stable clock defined signal cycling within timing constraints specified clock pin), SDRAM requires 100µs delay prior issuing command other than COMMAND INHIBIT Starting some point during this 100µs period continuing least through this period, COMMAND INHIBIT commands should applied. Once 100µs delay been satisfied with least COMMAND INHIBIT command having been applied, PRECHARGE command should applied. device banks must then precharged, thereby placing device banks idle state. Once idle state, AUTO REFRESH cycles must performed. After AUTO REFRESH cycles complete, SDRAM ready mode register programming. Because mode register will power unknown state, should loaded prior applying operational command.
Mode Register Definition
mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode write burst mode, shown Figure Mode Register Definition Diagram, page mode register programmed LOAD MODE REGISTER command will retain stored information until programmed again device loses power. Mode register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), M4-M6 specify latency, specify operating mode, specifies write
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
Serial Presence-Detect Operation
These modules incorporate serial presence-detect (SPD). function implemented using
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
burst mode, reserved future use. Address (M12) undefined should driven during loading mode register. mode register must loaded when device banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation. ordering accesses within burst determined burst length, burst type starting column address, shown Table Burst Definition Table, page
Figure Mode Register Definition Diagram
Address
Burst Length
Read write accesses SDRAM burst oriented, with burst length being programmable, shown Figure Mode Register Definition Diagram, page burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. full-page burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached, shown Table Burst Definition Table, page block uniquely selected A1-A9 when burst length two; A2-A9 when burst length four; A3-A9 when burst length eight. remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached, shown Table Burst Definition Table, page
Mode Register (Mx) Reserved* Mode Latency Burst Length
*Should program M11, ensure compatibility with future devices.
Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved Reserved
M6-M0 Defined
Operating Mode Standard Operation other states reserved
Burst Type
Accesses within given burst programmed either sequential interleaved; this referred burst type selected
Write Burst Mode Programmed Burst Length Single Location Access
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Table
BURST LENGTH
Burst Definition Table
STARTING COLUMN ADDRESS ORDER ACCESSES WITHIN BURST TYPE SEQUENTIAL TYPE INTERLEAVED 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Supported
Figure Latency Diagram
COMMAND
READ
DOUT
Full Page A0-A9 (location 0-y)
NOTE:
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn+1, Cn+2 Cn+3, Cn+4. .Cn-1,
Latency
COMMAND
READ
DOUT
Latency
DON'T CARE UNDEFINED
Latency
latency delay, clock cycles, between registration READ command availability first piece output data. latency three clocks. READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, READ command registered latency programmed clocks, will start driving after data will valid shown Figure Latency Diagram. Table Latency Table, indicates operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result.
full-page accesses: 1,024 burst length two, A1-A9 select block burst; selects starting column within block. burst length four, A2-A9 select block four burst; A0-A1 select starting column within block. burst length eight, A3-A9 select block eight burst; A0-A2 select starting column within block. full-page burst, full selected A0-A9 select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-A9 select unique column accessed, Mode Register ignored.For full-page burst, full selected A0-A8 select starting column.
Operating Mode
normal operating mode selected setting zero; other combinations values reserved future and/or test modes. programmed burst length applies both READ WRITE bursts.
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Test modes reserved states should used because unknown operation incompatibility with future versions result.
Table
Latency Table
ALLOWABLE OPERATING CLOCK FREQUENCY (MHz)
Write Burst Mode
When burst length programmed M0M2 applies both READ WRITE bursts; when programmed burst length applies READ bursts, write accesses single-location (nonburst) accesses.
SPEED -13E -133 -10E
LATENCY
LATENCY
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Commands
Truth Table, below, provides quick reference available commands. This followed written description each command. more detailed description commands operations, refer 128Mb SDRAM component data sheet.
Table
SDRAM Commands DQMB Operation Truth Table
RAS# CAS# DQMB ADDR Bank/ Bank/Col Bank/Col Code Op-code Valid Active Active High-Z NOTES
HIGH commands shown except SELF REFRESH NAME (FUNCTION) COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z
NOTE:
A0-A11 provide address; BA0-BA1 determine which device bank made active. A0-A9 provide column address; HIGH enables auto-precharge feature (nonpersistent), while disables auto-precharge feature; BA0-BA1 determine which device bank being read from written LOW: BA0-BA1 determine which device bank being precharged. HIGH: device banks precharged BA0, "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. A0-A11 define op-code written mode register. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Absolute Maximum Ratings
Stresses greater than those listed cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operaVoltage VDD, VDDQ Supply Relative +4.6V Voltage Inputs Pins Relative +4.6V tional sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Operating Temperature TOPR (Commercial ambient) +65°C TOPR (Industrial ambient) .-40°C +85°C Storage Temperature (plastic) -55°C +150°C
Table Electrical Characteristics Operating Conditions 128MB
Notes: notes appear page VDD, VDDQ +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input (All other pins under test SYMBOL VDD, VDDQ Command Address Inputs, CKE0 CK0, CK2, DQMB -0.3 UNITS NOTES
OUTPUT LEAKAGE CURRENT: pins disabled; VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA)
Table Electrical Characteristics Operating Conditions 256MB
Notes: notes appear page VDD, VDDQ +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input (All other pins under test SYMBOL VDD, VDDQ Command Address Inputs CKE0, CKE1 CK0, CK1, S0#, CK2, CK3, S2#, DQMB -0.3 UNITS NOTES
OUTPUT LEAKAGE CURRENT: pins disabled; VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA)
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Table Specifications Conditions 128MB
Notes: notes appear page VDD, VDDQ +3.3V ±0.3V; SDRAM component values only PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device banks idle; STANDBY CURRENT: Active Mode;CKE HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active tRFC tRFC (MIN) AUTO REFRESH CURRENT HIGH; HIGH SELF REFRESH CURRENT: 0.2V 15.625µs Standard Power
SYMBOL
IDD1
-13E
-133
-10E
UNITS
NOTES
1,125 1,035
IDD2 IDD3 IDD4 IDD5 IDD6 IDD7
1,350 1,260 1,080 2,070 1,890 1,710
Table Specifications Conditions 256MB
Notes: notes appear page VDD, VDDQ +3.3V ±0.3V; SDRAM component values only PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active tRFC tRFC (MIN) AUTO REFRESH CURRENT HIGH; HIGH SELF REFRESH CURRENT: 0.2V
NOTE:
SYMBOL IDD1a IDD2b IDD3a IDD4a IDD5b IDD6b IDD7b
-13E
-133
-10E
UNITS
NOTES
1,458 1,368 1,278
1,503 1,368 1,278 5,940 5,580 4,860
15.625µs Standard Power
tRFC
Value calculated module rank this condition, other module ranks Power-Down Mode (IDD2). Value calculated reflects module ranks this condition.
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Table Capacitance 128MB
Note notes appear page PARAMETER Input Capacitance: Address Command Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: DQMB0, 2-4, Input Capacitance: DQMB1 Input/Output Capacitance: SYMBOL 22.5 12.5 13.3 12.5 22.5 34.2 17.5 17.3 15.2 34.2 UNITS
Table Capacitance 256MB
Note notes appear page PARAMETER Input Capacitance: Address Command Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: DQMB0, 2-4, Input Capacitance: DQMB1 Input/Output Capacitance: SYMBOL 12.5 13.3 12.5 22.5 68.4 17.5 17.3 15.2 34.2 11.4 UNITS
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Table Electrical Characteristics Recommended Operating Conditions
Notes: notes appear page Module timing parameters comply with PC100 PC133 Design Specs, based component parameters ACCHARACTERISTICS PARAMETER Access timefrom (pos.edge) Address hold time Address setup time high-level width low-level width Clock cycle time holdt setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time (noload) ACTIVE PRECHARGE command ACTIVE ACTIVE command period ACTIVE READ WRITE delay Refresh period (4,096 rows) AUTOREFRESH period PRECHARGE command period ACTIVE bank ACTIVE bank command Transition time WRITE recovery time
-13E SYMBOL
-133 120,000
-10E UNITS 120,000 NOTES
AC(3) AC(2)
tCK(3)
CK(2)
tCKS
tCKH
tCMH tCMS tHZ(3) tHZ(2)
tRAS tRCD tREF tRFC tRRD
120,000
7.5ns
Exit SELF REFRESH ACTIVE command
tXSR
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Table Functional Characteristics
Notes: notes appear page PARAMETER READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVE command Data-in PRECHARGE command Last data-in burst STOP command Last data-in READ/WRITE command Last data-in PRECHARGE command LOAD MODE REGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command SYMBOL
-13E
-133
-10E
UNITS
NOTES
tCKED
tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH(3) tROH(2)
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Notes
voltages referenced VSS. This parameter sampled. VDD, VDDQ +3.3V; MHz; 25°C; under test biased 1.4V. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range ensured (0°C +70°C Commercial, -40°C +85°C Industrial). initial pause 100µs required after powerup, followed AUTO REFRESH commands, before proper device operation ensured. (VDD VDDQ must powered simultaneously. VSSQ must same potential.) AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load:
50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have with timing referenced 1.5V crossover point. input transition time longer than 1ns, then timing referenced (MAX) (MIN) longer crossover point. Other input signals allowed transition more than once every clocks otherwise valid levels. specifications tested after device properly initialized. Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate.
Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate. Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will increase decrease proportionally according amount frequency alteration test condition. Address transitions average transition every clocks. must toggled minimum times during this period. Based 10ns -10E; 7.5ns -133 -13E. overshoot: (MAX) VDDQ pulse width 3ns, pulse width cannot greater than third cycle rate. undershoot: (MIN) pulse width 3ns. clock frequency must remain constant (stable clock defined signal cycling within timing constraints specified clock pin) during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. precharge timing budget (tRP) begins -13E; 7.5ns -133; -10E after first clock delay, after last WRITE executed. exceed limit precharge mode. Precharge mode only. JEDEC PC100 specify three clocks. -133/-13E with load 4.6ns guaranteed design. Parameter guaranteed design. -13E, 7.5ns; -133, 7.5ns; -10E, CL=2 10ns HIGH during refresh command period (MIN) else LOW. IDD6 limit actually nominal value does result fail value. Refer device data sheet timing waveforms. value tRAS used -13E speed grade mod. ules calculated from Leakage number reflects worst case leakage possible through module pin, what each memory device contributes.
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Clock Data Conventions
Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions shown Figure Data Validity, Figure Definition Start Stop).
Acknowledge
Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data shown Figure Acknowledge Response From Receiver). device will always respond with acknowledge after recognition start condition slave address. both device WRITE operation have been selected, device will respond with acknowledge after receipt each subsequent eight word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
Start Condition
commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met.
Stop Condition
communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode.
Figure Data Validity
Figure Definition Start Stop
DATA STABLE DATA CHANGE DATA STABLE
START
STOP
Figure Acknowledge Response From Receiver
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Table EEPROM Device Select Code
most significant (b7) sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code DEVICE TYPE IDENTIFIER CHIP ENABLE
Table EEPROM Operating Modes
MODE Current Address Read RandomAddressRead Sequential Read Byte Write Page Write
BYTES
INITIAL SEQUENCE Start, Device Select, Start, Device Select, Address RESTART, Device Select, Similar Current Random Address Read START, Device Select, START, Device Select,
Figure EEPROM Timing Diagram
HIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
UNDEFINED
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; VDDSPD +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs POWER SUPPLY CURRENT: SYMBOL ICCS Write Read UNITS
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; VDDSPD +3.3V ±0.3V PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time
NOTE:
SYMBOL
tBUF tHD:DAT tHD:STA tHIGH tLOW fSCL tSU:DAT tSU:STA
UNITS
NOTES
SU:STO tWRC
avoid spurious START STOP conditions, minimum delay placed between SCL=1 falling rising edge SDA. This parameter sampled. reSTART condition, following WRITE cycle. EEPROM WRITE cycle time (tWRC) time from valid stop condition write sequence EEPROM internal erase/program cycle. During WRITE cycle, EEPROM interface circuit disabled, remains HIGH pull-up resistor, EEPROM does respond slave address.
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Table Serial Presence-Detect Matrix
"1"/"0": Serial data, "driven HIGH"/"driven LOW"; +3.3V ±0.3V BYTE DESCRIPTION Number Bytes Used Micron Total Number Memory Bytes Memory Type Number Addresses Number Column Addresses Number Module Ranks Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, (CAS Latency SDRAM Access From CLK, (CAS Latency Module Configuration Type Refresh Rate/Type SDRAM Width (Primary SDRAM) Error-checking SDRAM Data Width Minimum Clock Delay from Back-to-Back Random Column Addresses,tCCD Burst Lengths Supported Number Banks SDRAM Device Latencies Supported Latency Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time (CAS Latency SDRAM Access from CLK, (CAS Latency SDRAM Cycle Time, (CAS Latency SDRAM Access from CLK,
ENTRY (VERSION) SDRAM LVTTL (-13E) 7.5ns (-133 (-10E) 5.4ns (-13E/-133) (-10E) 15.625µs/SELF PAGE UNBUFFERED 7.5ns (13E) 10ns (-133/-10E) 5.4ns (-13E) (-133/-10E)
MT9LSDT1672A MT18LSDT3272A
(CAS Latency
Minimum Precharge Time,
Minimum Active Active, tRRD
Minimum RAS# CAS# Delay, tRCD Minimum RAS# Pulse Width, tRAS (See note
Module Rank Density
15ns (-13E) 20ns (-133/-10E) 14ns (-13E) 15ns (-133) 20ns (-10E) 15ns (-13E) 20ns (-133/-10E) 45ns (-13E) 44ns (-133) 50ns (-10E) 128MB
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Table Serial Presence-Detect Matrix (Continued)
"1"/"0": Serial data, "driven HIGH"/"driven LOW"; +3.3V ±0.3V BYTE 36-40 DESCRIPTION Command Address Setup Time, tAS, tCMS Command Address Hold Time, tAH, tCMH Data Signal Input Setup Time, Data Signal Input Hold Time, Reserved Device Minimum Active/Auto-Refresh Time, 60ns (-13E) 66ns (-133) 70ns (10E) REV. (-13E) (-133) (-10E) MICRON 1-12 ENTRY (VERSION) 1.5ns (-13E/-133) (-10E) 0.8ns (-13E/-133) (-10E) 1.5ns (-13E/-133) (-10E) 0.8ns (-13E/-133 (-10E)) MT9LSDT1672A MT18LSDT3272A 01-0C Variable Data 01-09 Variable Data Variable Data Variable Data 01-0C Variable Data 01-09 Variable Data Variable Data Variable Data
42-61
Reserved Revision Checksum Bytes 0-62
65-71 73-90 95-98 99-125
NOTE:
Manufacturer's JEDEC Code Manufacturer's JEDEC Code(Cont.) Manufacturing Location Module Part Number (ASCII) Identification Code Identification Code (Cont.) Year Manufacture Week Manufacture Module Serial Number Manufacturer-Specific Data (RSVD) System Frequency SDRAM Component Clock Detail
(-13E/-133/10E)
value tRAS used -13E modules calculated from tRP. Actual device specification value 37ns.
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Figure 168-Pin DIMM Dimensions Single Rank
STANDARD
FRONT VIEW
5.256 (133.50) 5.244 (133.20) 0.125 (3.18)
0.079 (2.00) (2X)
1.380 (35.05) 1.370 (34.80)
0.118 (3.00) (2X) 0.118 (3.00) 0.250 (6.35) 0.118 (3.00) 1.661 (42.18) 2.625 (66.68) 0.039 (1.00)R (2X) 4.550 (115.57) 1.039 (1.00) 0.050 (1.27)
0.700 (17.78)
0.128 (3.25) (2X) 0.118 (3.00)
0.054 (1.37) 0.046 (1.17)
(PIN BACKSIDE)
(PIN BACKSIDE)
PROFILE
FRONT VIEW
5.256 (133.50) 5.244 (133.20)
0.125 (3.18)
0.079 (2.00) (2X)
1.131 (28.73)
0.700 (17.78) 1.119 (28.42)
0.118 (3.00) (2X) 0.118 (3.00) 0.250 (6.35) 0.118 (3.00) 1.661 (42.18) 2.625 (66.68) 0.039 (1.00)R (2X) 4.550 (115.57) 0.039 (1.00) 0.050 (1.27)
0.128 (3.25) (2X) 0.118 (3.00)
0.054 (1.37) 0.046 (1.17)
(PIN BACKSIDE)
(PIN BACKSIDE)
NOTE:
dimensions inches (millimeters); typical where noted.
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Figure 168-Pin DIMM Dimensions Low-Profile
STANDARD
FRONT VIEW
5.256 (133.50) 5.244 (133.20) 0.157 (3.99)
0.079 (2.00) (2X)
1.380 (35.05) 1.370 (34.80)
0.118 (3.00) (2X) 0.118 (3.00) 0.250 (6.35) 0.118 (3.00) 1.661 (42.18) 2.625 (66.68) 0.039 (1.00)R (2X) 4.550 (115.57) 0.039 (1.00) 0.050 (1.27)
0.700 (17.78)
0.128 (3.25) (2X) 0.118 (3.00)
0.054 (1.37) 0.046 (1.17)
BACK VIEW
PROFILE
FRONT VIEW
5.256 (133.50) 5.244 (133.20)
0.157 (3.99)
0.079 (2.00) (2X)
1.131 (28.73)
0.700 (17.78) 1.119 (28.42)
0.118 (3.00) (2X) 0.118 (3.00) 0.250 (6.35) 0.118 (3.00) 1.661 (42.18) 2.625 (66.68) 0.039 (1.00)R (2X) 4.550 (115.57) 0.039 (1.00) 0.050 (1.27)
0.128 (3.25) (2X) 0.118 (3.00)
0.054 (1.37) 0.046 (1.17)
BACK VIEW
NOTE:
dimensions inches (millimeters); typical where noted.
09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
128MB (x72, ECC, SR), 256MB (x72, ECC, 168-PIN SDRAM UDIMM
Data Sheet Designation
Released Mark): This data sheet contains minimum maximum limits specified over complete power supply temperature range production devices. Although considered final, these specifications subject change, further product development data characterization sometimes occur.
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09005aef807b3709 SD9_18C16_32x72AG.fm Rev. 6/04 Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology,
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