0.6µm Series series ULCs well suited conversion medium- to-large

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0.6µm Series series ULCs well suited conversion medium- to-large

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Series
0.6µm Series
series ULCs well suited conversion medium- to-large sized CPLDs FPGAs. Devices implemented high-performance CMOS technology with 0.6-µm (drawn) channel lengths, capable supporting flip-flop toggle rates MHz, operating clock frequencies input output delays fast architecture series allows efficient conversion many architectures FPGA device types. compact cell, along with large number available gates allows implementation FPGA architectures that support this feature, well JTAG boundary-scan scan-path testing. Conversion series provide significant reduction operating power when compared original FPGA. This especially true when compared many CPLD architecture devices, which typically consume more even when being clocked. series very standby consumption nA/gate typically, which would yield standby current 10,000 gate design. Operating consumption strict function clock frequency, which typically results power reduction depending device being compared. series provides several options output buffers, including variety drive levels Schmitt trigger inputs also option. number techniques used improved noise immunity reduced emissions, including: several independent power supply busses internal decoupling isolation; slew rate limited outputs also available required. series designed allow conversions high performance 3.3V devices well 5.0V devices. Support mixed supply conversions also possible, allowing optimal trade-offs between speed power consumption.
Features
High performance family suitable medium- large-sized CPLDs FPGAs Conversions over 200,000 FPGA gates counts over pins pin-out matched limited number dedicated pads Advanced 0.6-µm (drawn)/0.45-µm (effective) feature size Triple-layer dual-layer metal CMOS technology High speed performance: 250-ps typical cell delay 350-MHz toggle rate Full range packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, PGA/PPGA 3.3V and/or 5.0V operation. quiescent current: nA/gate Available commercial, industrial, automotive, military space grades.
Rev.
May.
Series
Product Outline
Part Number
UG01 UG04 UG09 UG14 UG20 UG33 UG42 UG52 UG70 UG90 UG120 UG140
Full programmables Pads
Equivalent FPGA Gates
3300 7500 15800 24300 34800 46000 58600 63700 85800 108500 145100 156800
Maximum Drive
1210 1740 2880 3660 4550 6130 7750 10360 12250
Architecture
basic element family called cell. cell typically implement between three FPGA gates. Cells located contiguously through core device, with routing resources provided three metal layers above cells. Some cell blockage does occur routing, utilization will significantly greater with three metal routing than two. sizes listed Product Outline estimated usable amounts using three metal layers. cells provided each pad, configured inputs, outputs, I/Os, required match FPGA pinout. Special function cells pins located corners which typically unused. order improve noise immunity within device, separate busses provided internal cells cells.
Slew Rate Controlled Output Buffer this mode, n-output transistor commands delayed, that they never "ON" simultaneously, resulting switching current noise. These buffer dedicated very high load drive.
3.3V Compatibility
series ULCs fully capable supporting high-performance operation 3.3V 5.0V. performance specifications given design however, must explicitly specified 3.3V, 5.0V both.
Power Supply Noise Protection
order improve noise immunity series, several mechanisms have been implemented inside devices. kinds protection have been added: limit buffer switching noise other protect buffers against switching noise coming from core. buffers switching protection Three features implemented limit noise generated switching current: power supplies input output buffer separated. rise fall times output buffers controlled. number buffers that connected same power supply line limited.
Options
Inputs Each input programmed TTL, CMOS, Schmitt Trigger, with without pull pull down resistor. Fast Output Buffer Fast output buffers able source sink according chosen option. 24mA achievable, using pads.
Rev.
May.
Series
Core switching current protection This noise disturbance caused large number gates switching simultaneously. allow this without impacting functionality circuit, three features have been added: Some decoupling capacitors integrated directly silicon reduce power supply drop. power supply network been implemented matrix. This solution lessens parasitic elements such inductance resistance constitutes artificial plane. mesh network supplies approximately cells. low-pass filter been added between core inputs output buffers. This limits transmission noise coming from ground supply core output buffers.
Absolute Maximum Ratings
Supply Voltage (VDD) -0.5 Input Voltage (VIN) -0.5 Storage Temperature 150_C
Recommended Operating Range
Operating Temperature Commercial 70_C Industrial 85_C Military 125_C
Characteristics
Parameter Symbol
Input Leakage Current VSS, with pull-up VDD, with pull-down Output Leakage Current Output Short Circuit Current Standby Current Operating Current Input Capacitance Output Capacitance ICCSB IDDOP COUT VOUT VOUT VOUT VOUT 5.25 -130 -100 nA/Gate
Base Part
Commercial depending buffer -24, -12, depending buffer
Unit
Output Voltage
Input Voltage
µA/Gate/
Notes: 6,3. Selection determined FPGA data sheet requirements.
Rev.
May.
Series
Internal Timing Characteristics
These timing parameters selected macro cells provided information only. Only pin-to-pin timing characteristics guaranteed ULCs, actual specification determined original FPGA data sheet plus specific parameters that agreed separately TEMIC.
Conditions: Typical Process, Statistical Wire Length. delays measured VIN/VOUT
Macro Type
2-Input NAND 4-Input NAND Inverter Inverting State Buffer Tri-State NAND2 NAND4 TRISTAN Propagation Time
Parameter
Symbol
Maxa
0.39 0.68 0.41 0.74
Maxb
0.56 0.88 0.68 0.99 0.97
Units
Enable Time Setup Time Hold Time Pulse Width
tPLH tPHL tPLH 0.40 0.00 0.60 0.60 0.00
0.69
Resetable Latch
LATCHR
Propagation Time Enable Time Reset Time Setup Time Hold Time
0.97 1.22 0.87
1.25 1.49 1.10
Flip-Flop with Reset
FDFFR
Pulse Width Clock Delay Time Reset Time
0.95 0.81 0.80 0.68 0.80 0.68 2.97 1.96 2.49 1.74 3.27 1.60 2.49 1.74 3.27 1.60
1.22 0.94 0.95 0.74 0.95 0.74 8.18 4.23 6.42 3.47 7.17 3.30 6.42 3.47 7.17 3.30
Compatible Input Buffer Compatible Buffer Input Mode Output Buffer
BUFINTTL
BIOT12 Propagation Time BOUT6
tPHL tPLH tPHL tPLH
Compatible Buffer
BIOT12 Enable Time
tPLH tPZH tPZL tPLH tPHL tPZH tPZL
Propagation Time State Output Buffer Tri-State B3STA12 Enable Time
Notes Fan-outs three internal loads NAND2 NAND4, four loads other internal macros input buffers. Loading BOUT6 BIOT12 B3STA12 Fan-outs internal loads NAND2, seven loads NAND4, nine loads other internal macros eight input buffer. Loading BOUT6 BIOT12 B3STA12
Rev.
May.
Series
Derating Factors: tNOMINAL Process
Process Best 0.82 Nominal 1.00 Worst 1.28
Ambient Temperature
0.74 0.79 0.92 1.00 1.15 1.20 1.32
Supply Voltage
1.89 1.66 3.13 1.58 1.49 3.47 1.41 1.35 1.23 4.75 1.05 5.25 0.96 0.93
External Timing Characteristics
(Over Operating Range)
These timing parameters provided information
only. Actual pin-to-pin timing characteristics guaranteed ULCs determined original FPGA data sheet plus specific parameters that agreed separately TEMIC.
Parameter
Symbol
Base Part
UG01 UG04-UG09
Unit
10.5 13.0 14.5 10.0 11.5 13.0 15.0 16.5
Propagation Time
UG14-UG20 UG33-UG90 UG120-UG140 UG01 UG04-UG09 UG01 UG04-UG09
10.0 11.0
Clock Delay Time
UG14-UG20 UG33-UG90 UG120-UG140
Hold Time
10.0 11.0
10.0 11.5 13.0 15.0 16.5
Output Enable Time
UG14-UG20 UG33-UG90 UG120-UG140
Rev.
May.
Series
Power Consumption
Static Power Consumption Series ULCs
There three main factors consider: Leakage core: ICCSB number used gates Leakage inputs tri-stated outputs: PLIO (IIX where: number inputs number tri-stated outputs Care must taken include appropriate figure pins with pull-ups pull-downs. practice, static consumption calculation typically done determine standby current device; this case only those pins sourcing current should included, i.e. where VOUT VDD. power dissipation driving buffers resistive loads: practice, static consumption calculation typically done determine standby current device, under circumstances where outputs tri-stated input mode. this term zero. Global formula static consumption: PLIO approximated purely capacitive loads, allowing this term treated zero. loads source significant current state, high state, allowing second summation ignored. duty cycle assumed dynamic outputs driving loads, this approximated (mW) IOLn/2 IOLm) (TTL loads) where dynamic outputs static outputs. Dynamic power dissipation internal gates: (mW) IDDOP fg)/1000 where: number gates toggling frequency clock frequency internal logic Note: actual toggle rates known, rule thumb assume that average used gate toggling half input clock frequency. Dynamic power dissipation outputs: (mW) VDD2 (COUT Cn)/1000 where: clocking frequency output output load capacitance output COUT output capacitance from Characteristics Global formula dynamic consumption: Example: Static calculation 100-pin with 3000 used gates, inputs, I/Os input mode, outputs tri-stated. pull-ups pull-downs. Half pins VDD, half VSS. Input clock toggling. this example only current calculation desired, term equations dropped. 3000 PLIO ((10 5)/2 Dynamic Calculation take 16-bit resettable ripple counter which approximately gates, operating clock frequency MHz, which gives average clock frequency MHz/16 each each output. There static outputs this device. Operation 6-mA outputs used loaded output buffers driving CMOS loads. Rev.
Dynamic Power Consumption Series ULCs
There four main factors consider: Static power dissipation negligible compared dynamic ignored. power dissipation buffers resistive loads: (mW) (DLn IOLn) VOH) (DHn IOHn) where: summation over outputs I/Os. IOLn IOHn appropriate values driver percentage time being driven percentage time being driven difficult obtain exact value this factor, since determined primarily external system parameters. However, practice this simplified cases where device either driving CMOS loads driving loads. CMOS loads
May.
Series
33/16/1000 33/16 2)/1000 22.5 Transient energy absorbed line prevent reflections which would lead inaccurate measurements. Figure Typical Test Conditions
Typical Test Conditions
specification purposes, improved output loading scheme been defined TEMIC high-drive mA), high-speed devices. schematic below (Figure describes typical conditions testing these devices, using standard loading scheme commonly available high-end ATE. Compared no-load condition, this provides following advantages: Output load more representative "real life" conditions during transitions.
D.U.T.
Comp
Rev.
May.

0.6µm Series series ULCs well suited conversion medium- to-large

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