High Speed CMOS Parallel FIFO Tolerant M67204F implements first-i

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High Speed CMOS Parallel FIFO Tolerant M67204F implements first-i

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M67204F
High Speed CMOS Parallel FIFO Tolerant
M67204F implements first-in first-out algorithm, featuring asynchronous read/write operations. FULL EMPTY flags prevent data overflow underflow. Expansion logic allows unlimited expansion word size depth with timing penalties. Twin address pointers automatically generate internal read write addresses, external address information required TEMIC FIFOs. Address pointers automatically incremented with write read pin. bits wide data used data communications applications where parity error checking necessary. Retransmit reset Read pointer zero without affecting write pointer. This very useful retransmitting data when error detected system. Using array eight transistors memory cell, M67204F combine extremely standby supply current (typ with fast access time over full temperature range. versions offer battery backup data retention capability with typical power consumption less than M67204F processed according methods latest revision (class 9000 QML.
Features
First-in first-out dual port memory 4096 organisation Fast Flag access times: Wide temperature range Fully expandable word width depth Asynchronous read/write operations Empty, full half flags single device mode Retransmit capability Bi-directional applications Battery back-up operation data retention compatible Single power supply High Performance SCMOS Technology
Rev. July 2000
Preliminary
M67204F
Interface
Block Diagram
4096
16384
Configuration
ceramic mils mils
(top view)
FL/RT XO/HF
Rev. July 2000
Preliminary
M67204F
Names
NAMES
I0-8 Q0-8 Inputs Outputs Write Enable Read Enable Reset Empty Flag
DESCRIPTION
NAMES
XO/HF FL/RT
DESCRIPTION
Full Flag Expansion Out/Half-Full Flag Expansion First Load/Retransmit Power Supply Ground
Signal Description
Data
Data inputs data pointers first location. reset required after power-up before write operation enabled. Both Read Enable Write Enable inputs must high state during period shown Figure (i.e. tRSS before rising edge should change until tRSR after rising edge Half-Full Flag (HF) will reset high After Reset (RS)
Reset (RS)
Reset occurs whenever Reset (RS) input taken state. Reset returns both internal read write Figure Reset
(tRR)
Notes
change status during reset, flags will valid tRSC. around rising edge
Write Enable
write cycle initiated falling edge this input Full Flag (FF) set. Data set-up hold times must maintained rise time leading edge Write Enable (W). Data stored sequentially array, regardless current read operation. Once half memory filled, during falling edge next write operation, Half-Full Flag (HF) Rev. July 2000 will remain this state until difference between write read pointers less than equal half total available memory device. Half-Full Flag (HF) then reset rising edge read operation. prevent data overflow, Full Flag (FF) will low, inhibiting further write operations. completion
Preliminary
M67204F
valid read operation, Full Flag (FF) will high after TRFF, allowing valid write begin. When FIFO stack full, internal write pointer blocked from that external changes will have effect full FIFO stack.
Expansion (XI)
This input dual-purpose pin. Expansion (XI) connected indicate operation single device mode. Expansion (XI) connected Expansion (XO) previous device Depth Expansion Daisy Chain modes.
Read Enable
read cycle initiated falling edge Read Enable provided that Empty Flag (EF) set. data accessed first in/first basis, with standing current write operations. After Read Enable goes high, Data Outputs will return high impedance state until next Read operation. When data FIFO stack been read, Empty Flag (EF) will low, allowing "final" read cycle, inhibiting further read operations whilst data outputs remain high impedance state. Once valid write operation been completed, Empty Flag (EF) will high after tWEF valid read then initiated. When FIFO stack empty, internal read pointer blocked from that external changes will have effect empty FIFO stack.
Full Flag (FF)
Full Flag (FF) will low, inhibiting further write operations when write pointer location less than read pointer, indicating that device full. read pointer moved after Reset (RS), Full Flag (FF) will after 16384 writes.
Empty Flag (EF)
Empty Flag (EF) will low, inhibiting further read operations when read pointer equal write pointer, indicating that device empty.
Expansion Out/Half-Full Flag (XO/HF) First Load/Retransmit (FL/RT)
This dual-purpose input. Depth Expansion Mode, this connected ground indicate that first loaded (see Operating Modes). Single Device Mode, this acts retransmit input. Single Device Mode initiated connecting Expansion (XI) ground. M67204F made retransmit data when Retransmit Enable Control (RT) input pulsed low. retransmit operation will internal read point first location will affect write pointer. Read Enable Write Enable must high state during retransmit. retransmit feature intended when number writes equals less than depth FIFO occured since last cycle. retransmit feature compatible with Depth Expansion Mode will affect Half-Full Flag (HF), accordance with relative locations read write pointers. This dual-purpose output. single device mode, when Expansion (XI) connected ground, this output acts indication half-full memory. After half memory filled falling edge next write operation, Half-Full Flag (HF) will will remain until difference between write read pointers less than equal half total memory device. Half-Full Flag (HF) then reset rising edge read operation. Depth Expansion Mode, Expansion (XI) connected Expansion (XO) previous device. This output acts signal next device Daisy Chain providing pulse next device when previous device reaches last memory location.
Data Output
DATA output 9-bit wide data. This data high impedance condition whenever Read high state.
Rev. July 2000
Preliminary
M67204F
Functional Description
Operating Modes Single Device Mode
single M67204F used when application requirements 4096 words less. M67204F Single Device Configuration when Expansion Figure Block Diagram Single 4096
(HALF-FULL FLAG) WRITE DATAIN DATAOUT READ
(XI) control input grounded (see Figure 2.). this mode Half-Full Flag (HF), which active output, shared with Expansion (XO).
FULL FLAG (FF) RESET (RS)
(EF) EMPTY FLAG (RT) RETRANSMIT
EXPANSION (XI)
M67204F
Width Expansion Mode
Word width increased simply connecting corresponding input control signals multiple devices.
Status flags (EF, detected from device. Figure demonstrates 18-bit word width using M67204F. word width attained adding additional M67204F.
Figure Block Diagram 4096 FIFO Memory Used Width Expansion Mode.
DATAIN READ WRITE FULL FLAG RESET (RS) (FF) (EF) EMPTY FLAG (RT) RETRANSMIT
M67204F
DATAOUT
Note Flag detection accomplished monitoring signals either (any) device used width expansion configuration. connect output control signals together.
Rev. July 2000
Preliminary
M67204F
Table Reset retransmit Single Device Configuration/Width Expansion Mode
INPUTS MODE
Reset Retransmit Read/Write
INTERNAL STATUS
OUTPUTS
Read Pointer
Location Zero Location Zero Increment(4)
Write Pointer
Location Zero Unchanged Increment(4)
Note Pointer will increment flag high.
Table Reset First Load Truth Table Depth Expansion/Compound Expansion Mode
INPUTS MODE
Reset First Device Reset Other Devices Read/Write
INTERNAL STATUS
OUTPUTS
Read Pointer
Location Zero Location Zero
Write Pointer
Location Zero Location Zero
Note connected previous device. Figure
Depth Expansion (Daisy Chain) Mode
M67204F easily adapted applications which require more than 4096 words. Figure demonstrates Depth Expansion using three M67204F. depth achieved adding additional 67204F. M67204F operates Depth Expansion configuration following conditions first device must designated connecting First Load (FL) control input ground. other devices must have high state. Expansion (XO) each device must connected Expansion (XI) next device. Figure External logic needed generate composite Full Flag (FF) Empty Flag (EF). This requires that EF's (i.e. must generate correct composite EF). Figure
Retransmit (RT) function Half-Full Flag (HF) available Depth Expansion Mode.
Compound Expansion Module
quite simple apply expansion techniques described above together create large FIFO arrays (see Figure 5.).
Bidirectional Mode
Applications which require data buffering between systems (each system being capable Read Write operations) created coupling M67204F shown Figure Care must taken ensure that appropriate flag monitored each system (i.e. monitored device which monitored device which use). Both Depth Expansion Width Expansion used this mode.
Rev. July 2000
Preliminary
M67204F
Data Flow Through Modes
types flow-through modes permitted read write flow-through mode (Figure 18.), FIFO flow-through write flow-through mode. read stack allows single word data written flow-through mode (Figure 17.) FIFO stack allows immediately after single word data been read single word read after word been written from full FIFO stack. line causes empty FIFO stack. data enabled reset, line, being low, causes again (tWEF after leading edge which anticipation data word. word known first write edge remains until loaded into FIFO stack leading edge line raised from high, after which line must toggled when order write will into three-state mode after tRHZ line data into FIFO stack increment write will show pulse indicating temporary reset then will pointer. set. interval which low, more words written FIFO stack (the subsequent writes after first write edge will reset Empty Flag) however, same word (written first write edge) presented output read pointer will incremented low. toggling remaining words written FIFO will appear output accordance with read cycle timings. Figure Block Diagram 12298 FIFO Memory (Depth expansion).
67204F
FULL
67204F
EMPTY
67204F
Figure Compound FIFO Expansion.
67204F DEPTH EXPANSION BLOCK 67204F DEPTH EXPANSION BLOCK 67204F DEPTH EXPANSION BLOCK Q(N-8) Q(N-8)
I(N-8)
I(N-8)
Notes depth expansion block section Depth Expansion Figure Flag detection section Width Expansion Figure
Rev. July 2000
Preliminary
M67204F
Figure Bidirectional FIFO Mode.
67204F
SYSTEM
SYSTEM
67204F
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC GND) Input Output voltage applied (GND (Vcc Storage temperature
OPERATING RANGE
Military
OPERATING SUPPLY VOLTAGE
OPERATING TEMPERATURE
Parameters
Parameter
ICCOP ICCSB ICCPD (10)
Description
Operating supply current Standby supply current Power down current
67204F-30
67204F-15
UNIT
VALUE
Notes measurements made with outputs open. FL/RT VIH. input Vcc.
Rev. July 2000
Preliminary
M67204F
PARAMETER
(11) (12) (13) (13) (14) (14) (15) (15) Notes
DESCRIPTION
Input leakage current Output leakage current Input voltage Input high voltage Output voltage Output high voltage Input capacitance Output capacitance
M67204F
UNIT
VALUE
Vcc. VIH, VOUT VCC. -0.3 pulse width input, VIH= 2.8V min, Guaranteed tested.
Rev. July 2000
Preliminary
M67204F
Test Conditions
Input pulse levels Input rise/Fall times Input timing reference levels Output reference levels Output load Figure Figure Output Load.
OUTPUT
includes scope capacitance
SYMBOL (17) SYMBOL (16)
READ CYCLE TRLRL TRLQV TRHRL TRLRH TRLQX TWHQX TRHQX TRHQZ WRITE CYCLE TWLWL TWLWH TWHWL TDVWH TWHDX RESET CYCLE TRSLWL TRSLRSH TWHRSH TRSHWL TRTLWL TRTLRTH TWHRTH TRTHWL FLAGS TRSLEFL TRSLFFH TRLEFL TRHFFH TEFHRH TWHEFH TWLFFL TWLHFL TRHHFH TFFHWH tEFL tHFH, tFFH tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF Reset Reset HF/FF high Read Read high high Read width after high Write high high Write Write Read high high Write width after high tRSC tRSS tRSR tRTC tRTS tRTR Reset cycle time Reset pulse width (19) Reset set-up time Reset recovery time Retransmit cycle time Retransmit pulse width (19) Retransmit set-up time (20) Retransmit recovery time tWPW Write cycle time Write pulse width (19) Write recovery time Data set-up time Data hold time tRPW tRLZ tWLZ tRHZ Read cycle time Access time Read recovery time Read pulse width (19) Read data (20) Write data (20, Data valid from read high Read high data high (20)
PARAMETER (18) (22)
M67204F MIN.
M67204F MIN.
UNIT
MAX.
MAX.
RETRANSMIT CYCLE
Rev. July 2000
Preliminary
M67204F
SYMBOL (16) SYMBOL (17)
EXPANSION TWLXOL TWHXOH TXILXIH TXIHXIL TXILRL Notes tXOL tXOH tXIR tXIS Read/Write Read/Write high pulse width recovery time set-up time
PARAMETER (18) (22)
M67204F MIN. MAX.
M67204F MIN. MAX.
UNIT
symbol. symbol. Timings referenced test conditions. Pulse widths less than minimum value allowed. Values guaranteed design, currently tested. Only applies read data flow-through mode. parameters tested only.
Figure Asynchronous Write Read Operation.
Rev. July 2000
Preliminary
M67204F
Figure Full Flag from Last Write First Read.
Figure Empty Flag from Last Read First Write.
Figure Retransmit.
Note
change status during Retransmit, flags will valid tRTC.
Rev. July 2000
Preliminary
M67204F
Figure Empty Flag Timing
Figure Full Flag Timing
Figure Half-Full Flag Timing.
HALF FULL OFFSET LESS HALF FULL OFFSET LESS
MORE THAN HALF FULL
Rev. July 2000
Preliminary
M67204F
Figure Expansion Out.
Figure Expansion
Figure Read Data Flow Through Mode.
Rev. July 2000
Preliminary
M67204F
Figure Write Data Flow Through Mode.
Rev. July 2000
Preliminary
M67204F
Ordering Information
TEMPERATURE RANGE PACKAGE DEVICE 67204FV SPEED FLOW* /883
mils side brazed Flat pack pins mils Dice form
blank /883 SB/SC
standards Class 9000 level
Military Space
-55° +125°C -55° +125°C
67204 4096 FIFO Very power Radiation Tolerant
ordering quality level, according 5962-89568.
information contained herein subject change without notice. responsibility assumed TEMIC using this publication and/or circuits described herein possible infringements patents other rights third parties which result from use.
Rev. July 2000
Preliminary

High Speed CMOS Parallel FIFO Tolerant M67204F implements first-i

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