FN4793.1 Advanced Triple Linear Power Controller HIP6021A pr

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

FN4793.1 Advanced Triple Linear Power Controller HIP6021A pr

Datasheet Thumbnail

Top Searches for this datasheet

HIP6021A
FN4793.1
Advanced Triple Linear Power Controller
HIP6021A provides power control protection four output voltages high-performance, graphics intensive microprocessor computer applications. integrates voltage-mode controller three linear controllers, well monitoring protection functions into lead SOIC package. synchronous-rectified buck converter includes Intelcompatible, 5-input digital-to-analog converter (DAC) that adjusts core output voltage from 1.3VDC 2.05VDC 0.05V steps from 2.1VDC 3.5VDC 0.1V increments. precision reference voltage-mode control provide static regulation. TTL-compatible signal applied SELECT dictates which method control used power: state results linear control 1.5V, while high state transitions output through linearly controlled softstart 3.3V, followed full enhancement external MOSFET pass input voltage. other linear regulators provide fixed output voltages 1.5V power 1.8V power North/South Bridge core and/or cache memory. These levels user-adjustable means external resistor divider pulling low. linear controllers employ either N-Channel MOSFETs bipolar NPNs pass transistor. HIP6021A monitors output voltages. single Power Good signal issued when core within ±10% setting other outputs above their undervoltage levels. Additional built-in over-voltage protection core output uses lower MOSFET prevent output voltages above 115% setting. controller's over-current function monitors output current using voltage drop across upper MOSFET's rDS(ON).
Features
Provides Regulated Voltages Microprocessor Core, Bus, Memory, Power Drives N-Channel MOSFETs Linear Regulator Drives Compatible with both MOSFET Bipolar Series Pass Transistors Fixed Externally Resistor-Adjustable Linear Outputs Simple Single-Loop Control Design Voltage-Mode Control Fast Converter Transient Response High-Bandwidth Error Amplifier Full 100% Duty Ratio Excellent Output Voltage Regulation Core Output: Over Temperature Other Outputs: Over Temperature TTL-Compatible 5-Bit Core Output Voltage Selection Shutdown Feature Removed When Inputs High Wide Range 1.3VDC 3.5VDC Power-Good Output Voltage Monitor Over-Voltage Over-Current Fault Monitors Switching Regulator Does Require Extra Current Sensing Element, Uses Upper MOSFET's rDS(ON) Small Converter Size Constant Frequency Operation 200kHz Free-Running Oscillator; Programmable From 50kHz Over 1MHz Small External Component Count
Applications
Motherboard Power Regulation Computers
Pinout
HIP6021A (SOIC) VIEW
DRIVE2 UGATE PHASE LGATE PGND OCSET VSEN1 COMP VSEN3 DRIVE3 VAUX DRIVE4
Ordering Information
PART NUMBER HIP6021ACB HIP6021EVAL1 TEMP. RANGE (oC) PACKAGE SOIC PKG. M28.3
VID4 VID3 VID2 VID1
Evaluation Board
VID0 PGOOD VSEN2 SELECT FAULT/RT VSEN4
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2001. Rights Reserved
Block Diagram
VSEN3
VSEN1
OCSET
VAUX
POWER-ON 1.10 RESET (POR) 0.90 1.26V LINEAR UNDERVOLTAGE 1.15 200µA 0.75 SOFTINHIBIT START FAULT FAULT LOGIC ERROR AMP1 GATE CONTROL COMP1 PWM1 28µA OSCILLATOR 4.5V DACOUT CONVERTER (DAC) FAULT COMP VID0 VID1 VID2 VID4 VID3
VAUX
HIP6021A
VSEN2
SELECT
1.5V 3.3VIN
DRIVE3
DRIVE4
PGOOD
VSEN4
DRIVE1 UGATE PHASE
DRIVE2
LGATE SYNCH DRIVE PGND
0.75
HIP6021A Simplified Power System Diagram
+5VIN +3.3VIN LINEAR CONTROLLER VOUT2 CONTROLLER VOUT1
HIP6021A
VOUT3 LINEAR CONTROLLER LINEAR CONTROLLER
VOUT4
Typical Application
+12VIN +5VIN OCSET +3.3VIN PGOOD DRIVE2 UGATE VSEN2 PHASE LOUT1 VOUT1 1.3V 3.5V POWERGOOD
VOUT2 1.5V 3.3VIN
COUT2 LGATE PGND TYPEDET SELECT VSEN1 VAUX COUT1
HIP6021A
VOUT3 1.5V DRIVE3 VSEN3
COMP
COUT3
FAULT VID0
VOUT4 1.8V
DRIVE4 VSEN4
VID1 VID2 VID3
COUT4
VID4
HIP6021A
Absolute Maximum Ratings
Supply Voltage, +15V PGOOD, RT/FAULT, DRIVE, PHASE, GATE Voltage 0.3V 0.3V Input, Output Voltage -0.3V Classification Class
Thermal Information
Thermal Resistance (Typical, Note
(oC/W)
SOIC Package Maximum Junction Temperature (Plastic Package) 150oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Supply Voltage, +12V ±10% Ambient Temperature Range 70oC Junction Temperature Range. 125oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER SUPPLY CURRENT Nominal Supply Current POWER-ON RESET Rising Threshold Falling Threshold Rising VAUX Threshold VAUX Threshold Hysteresis Rising VOCSET Threshold OSCILLATOR Free Running Frequency Total Variation Ramp Amplitude
Recommended Operating Conditions, Unless Otherwise Noted. Refer Block Simplified Power System Diagrams, Typical Application Schematic SYMBOL TEST CONDITIONS UNITS
UGATE, LGATE, DRIVE2, DRIVE3, DRIVE4 Open
VOCSET 4.5V VOCSET 4.5V VOCSET 4.5V VOCSET 4.5V
1.26
10.4
FOSC
OPEN 200k
VP-P
VOSC
Open
BANDGAP REFERENCE DAC(VID0-VID4) Input Voltage DAC(VID0-VID4) Input High Voltage DACOUT Voltage Accuracy Bandgap Reference Voltage Bandgap Reference Tolerance LINEAR REGULATORS (OUT2, OUT3, OUT4) Regulation (All Linears) VSEN2 Regulation Voltage VSEN3 Regulation Voltage VSEN4 Regulation Voltage Under-Voltage Level (VSEN/VREG) Under-Voltage Hysteresis (VSEN/VREG) Output Drive Current (All Linears) VREG2 VREG3 VREG4 VSENUV VSEN Rising VSEN Falling VAUX-VDRIVE 0.6V Except OUT2 when SELECT 2.0V SELECT 0.8V -1.0 -2.5 1.265 +1.0 +2.5
HIP6021A
Electrical Specifications
PARAMETER Recommended Operating Conditions, Unless Otherwise Noted. Refer Block Simplified Power System Diagrams, Typical Application Schematic (Continued) SYMBOL TEST CONDITIONS UNITS
SYNCHRONOUS CONTROLLER ERROR AMPLIFIER Gain Gain-Bandwidth Product Slew Rate CONTROLLER GATE DRIVER UGATE Source UGATE Sink LGATE Source LGATE Sink PROTECTION VSEN1 Over-Voltage (VSEN1/DACOUT) FAULT Sourcing Current OCSET1 Current Source Soft-Start Current POWER GOOD VSEN1 Upper Threshold (VSEN1/DACOUT) VSEN1 Under-Voltage (VSEN1/DACOUT) VSEN1 Hysteresis (VSEN1/DACOUT) PGOOD Voltage VPGOOD VSEN1 Rising VSEN1 Rising Upper/Lower Threshold IPGOOD -4mA IOVP IOCSET VSEN1 Rising VFAULT/RT 2.0V VOCSET 4.5VDC IUGATE RUGATE ILGATE RLGATE 12V, VUGATE VGATE-PHASE 12V, VLGATE VLGATE GBWP COMP 10pF V/µs
Typical Performance Curve
1000 RESISTANCE
PULLUP +12V
PULLDOWN
SWITCHING FREQUENCY (kHz)
1000
FIGURE RESISTANCE FREQUENCY
HIP6021A Functional Descriptions
(Pin
Provide bias supply this pin. This also provides gate bias charge MOSFETs controlled voltage this monitored Power-On Reset (POR) purposes. soft-start capacitor, disabling outputs. Dedicated internal circuitry insures core output voltage does negative during this process. When re-enabled, undergoes soft-start cycle. Left open, this pulled internal pull-down resistor, enabling operation.
(Pin
Grounding this bypasses internal resistor dividers that output voltage 1.5V 1.8V linear regulators. This way, output voltage regulators adjusted from 1.26V input voltage (+3.3V +5V) external resistor divider connected corresponding VSEN pin. output voltage external resistor divider determined using following formula:
1.265V
(Pin
Signal ground voltage levels measured with respect this pin.
PGND (Pin
This power ground connection. synchronous converter's lower MOSFET source this pin.
VAUX (Pin
This provides boost current linear regulators' output drives event bipolar transistors (instead N-Channel MOSFETs) employed pass elements. voltage this monitored power-on reset (POR) purposes.
where ROUT resistor connected from VSEN output regulator, RGND resistor connected from VSEN ground. Left open, pulled high, enabling fixed output voltage operation.
(Pin
Connect capacitor from this ground. This capacitor, along with internal 28µA current source, sets softstart interval converter.
VID0, VID1, VID2, VID3, VID4 (Pins
VID0-4 TTL-compatible input pins 5-bit DAC. logic states these five pins program internal voltage reference (DACOUT). level DACOUT sets microprocessor core converter output voltage, well corresponding PGOOD thresholds.
FAULT (Pin
This provides oscillator switching frequency adjustment. placing resistor (RT) from this GND, nominal 200kHz switching frequency increased according following equation:
200kHz
OCSET (Pin
Connect resistor from this drain respective upper MOSFET. This resistor, internal 200µA current source, upper MOSFET's on-resistance converter over-current trip point. over-current trip cycles soft-start function. voltage this monitored power-on reset (POR) purposes pulling this with open drain device will shutdown
GND)
Conversely, connecting resistor from this reduces switching frequency according following equation:
200kHz
12V)
PHASE (Pin
Connect PHASE converter's upper MOSFET source. This represents gate drive return current path used monitor voltage drop across upper MOSFET over-current protection.
Nominally, voltage this 1.26V. event over-voltage over-current condition, this internally pulled VCC.
PGOOD (Pin
PGOOD open collector output used indicate status output voltages. This pulled when synchronous regulator output within ±10% DACOUT reference voltage when other outputs below their under-voltage thresholds. PGOOD output open `11111' code.
UGATE (Pin
Connect UGATE converter's upper MOSFET gate. This provides gate drive upper MOSFET.
LGATE (Pin
Connect LGATE converter's lower MOSFET gate. This provides gate drive lower MOSFET.
(Pin
This shuts down outputs. TTL-compatible, logic level high signal applied this immediately discharges
HIP6021A
COMP (Pin
COMP available external pins converter error amplifier. inverting input error amplifier. Similarly, COMP error amplifier output. These pins used compensate voltage-mode control feedback loop synchronous converter. level programmed 5-bit digital-to-analog converter (DAC). voltage (VOUT2) using SELECT either 1.5V linear regulated output 3.3VIN through pass device. Selection either output voltage depending logic level SELECT pin. remaining linear controllers supply 1.5V power (VOUT3) 1.8V memory power (VOUT4). These output voltages user adjustable. linear controllers designed employ external pass transistor.
VSEN1 (Pin
This connected converter's output voltage. PGOOD comparator circuits this signal report output voltage status over-voltage protection.
DRIVE2 (Pin
Connect this gate external MOSFET. This provides drive regulator's pass transistor.
Initialization
HIP6021A automatically initializes upon receipt input power. Special sequencing input supplies necessary. Power-On Reset (POR) function continually monitors input supply voltages. monitors bias voltage (+12VIN) pin, input voltage (+5VIN) OCSET pin, 3.3V input voltage (+3.3VIN) VAUX pin. normal level OCSET equal +5VIN less fixed voltage drop (see over-current protection). function initiates soft-start operation after supply voltages exceed their thresholds.
VSEN2 (Pin
Connect this output linear regulator. voltage this regulated level predetermined logic-level status SELECT pin. This also monitored under-voltage events.
SELECT (Pin
This determines output voltage linear regulator. input sets output voltage 1.5V linear controller regulates this voltage within ±3%. high input turns continuously, providing current path from input (+3.3VIN) output (VOUT2) controller.
Soft-Start
function initiates soft-start sequence. Initially, voltage rapidly increases approximately (this minimizes softstart interval). Then internal 28µA current source charges external capacitor (CSS) 4.5V. error amplifier reference input terminal) output (COMP pin) clamped level proportional voltage. voltage slews from output clamp allows generation PHASE pulses increasing width that charge output capacitor(s). After output voltage increases approximately value, reference input clamp slows output voltage rate-of-rise provides smooth transition final voltage. Additionally, linear regulators' reference inputs clamped voltage proportional voltage. This method provides rapid controlled output voltage rise. Figure shows soft-start sequence typical application. voltage rapidly increases approximately error amplifier output voltage reach valley oscillator's triangle wave. oscillator's triangular waveform compared clamped error amplifier output voltage. voltage increases, pulse width PHASE increases. interval increasing pulse width continues until each output reaches sufficient voltage transfer control input reference clamp. consider 2.5V core output (VOUT1) Figure this time occurs During interval between error amplifier reference ramps final value converter regulates output voltage proportional
DRIVE3 (Pin
Connect this gate external MOSFET. This provides drive 1.5V regulator's pass transistor.
VSEN3 (Pin
Connect this output 1.5V linear regulator. This monitored under-voltage events.
DRIVE4 (Pin
Connect this gate external MOSFET. This provides drive 1.8V regulator's pass transistor.
VSEN4 (Pin
Connect this output linear 1.8V regulator. This monitored under voltage events.
Description
Operation
HIP6021A monitors precisely controls output voltage levels (Refer Block Simplified Power System Diagrams, Typical Application Schematic). designed microprocessor computer applications with 3.3V, bias input from power supply. microprocessor core voltage (VOUT1) controlled synchronous-rectified buck converter configuration. controller regulates microprocessor core voltage
HIP6021A
voltage. input clamp voltage exceeds reference voltage output voltage regulation. Cycling bias input voltage (+12VIN then resets counter fault latch.
OVERCURRENT LATCH SOFT-START (1V/DIV) 0.15V INHIBIT
PGOOD
VOUT2 3.3VIN) VOUT1 (DAC 2.5V) VOUT4 1.8V) OUTPUT VOLTAGES (0.5V/DIV)
COUNTER FAULT LATCH FAULT
FIGURE FAULT LOGIC SIMPLIFIED SCHEMATIC
Over-Voltage Protection
VOUT3 1.5V)
TIME
During operation, short upper MOSFET regulator (Q1) causes VOUT1 increase. When output exceeds over-voltage threshold 115% DACOUT, over-voltage comparator trips fault latch turns This blows input fuse reduces VOUT1. fault latch raises FAULT/RT VCC. separate over-voltage circuit provides protection during initial application power. voltages below power-on reset (and above ~4V), output level monitored voltages above 1.3V. Should VSEN1 exceed this level, lower MOSFET, driven
FIGURE SOFT-START INTERVAL
remaining outputs also programmed follow voltage. PGOOD signal toggles `high' when output voltage levels have exceeded their under-voltage levels. waveform VOUT2 represents case where SELECT held `high'. voltage controlled same manner other linear regulators during softstart sequence. Once softstart sequence complete (T4), gate external pass device fully enhanced VOUT2 tracks 3.3VIN voltage. Soft-Start Interval section under Applications Guidelines procedure determine soft-start interval.
Over-Current Protection
outputs protected against excessive over-currents. controller uses upper MOSFET's on-resistance, rDS(ON) monitor current protection against shorted output. linear controllers monitor their respective VSEN pins under-voltage events protect against excessive currents. Figure illustrates over-current protection with overload OUT1. overload applied current increases through inductor (LOUT1). time OVER-CURRENT comparator trips when voltage across rDS(ON)) exceeds level programmed ROCSET. This inhibits outputs, discharges soft-start capacitor (CSS) with 10mA current sink, increments counter. recharges initiates soft-start cycle with error amplifiers clamped soft-start. With OUT1 still overloaded, inductor current increases trip over-current comparator. Again, this inhibits outputs, soft-start voltage continues increasing before discharging. counter increments soft-start cycle repeats trips over-current comparator. voltage increases counter increments This sets fault latch disable converter. fault reported FAULT/RT pin.
Fault Protection
four outputs monitored protected against extreme overload. sustained overload output overvoltage VOUT1 output (VSEN1) disables outputs drives FAULT/RT VCC. Figure shows simplified schematic fault logic. over-voltage detected VSEN1 immediately sets fault latch. sequence three over-current fault signals also sets fault latch. over-current latch dependent upon states over-current (OC), linear undervoltage (LUV) soft-start signals. window comparator monitors indicates when fully charged signal). under-voltage either linear output (VSEN2, VSEN3, VSEN4) ignored until after soft-start interval Figure This allows VOUT2 VOUT3 VOUT4 increase without fault start-
HIP6021A
linear controllers operate same response over-current faults. differentiating factor linear controllers that they monitor VSEN pins under-voltage events. Should excessive currents cause voltage VSEN pins fall below linear undervoltage threshold, signal sets over-current latch fully charged. Blanking signal during charge interval allows linear outputs build above under-voltage threshold during normal operation. Cycling bias input power then resets counter fault latch.
OVER-CURRENT TRIP: OCSET OCSET OCSET IOCSET 200µA OVERCURRENT DRIVE UGATE PHASE ROCSET
VSET
FAULT/RT COUNT SOFT-START OVERLOAD APPLIED COUNT COUNT FAULT REPORTED GATE CONTROL
PHASE OCSET
FIGURE OVER-CURRENT DETECTION
trip point varies with MOSFET's rDS(ON) temperature variations. avoid over-current tripping normal operating load range, determine ROCSET resistor from equation above with: maximum rDS(ON) highest junction temperature. minimum IOCSET from specification table. Determine IPEAK IPEAK IOUT(MAX) (I)/2, where output inductor ripple current.
INDUCTOR CURRENT
equation ripple current section under component guidelines titled `PWM Output Inductor Selection'.
TIME
OUT1 Voltage Program
output voltage converter programmed discrete levels between 1.3VDC 3.5VDC This output (OUT1) designed supply core voltage Intel's advanced microprocessors. voltage identification (VID) pins program internal voltage reference (DACOUT) with TTL-compatible 5-bit digital-to-analog converter. level DACOUT also sets PGOOD thresholds. Table specifies DACOUT voltage different combinations connections pins. pins left open logic input, because they internally pulled internal voltage about 10µA current source. Changing inputs during operation recommended, could toggle PGOOD signal exercise over-voltage protection.
FIGURE OVER-CURRENT OPERATION
resistor (ROCSET) programs over-current trip level converter. shown Figure internal 200µA current sink, IOCSET develops voltage across ROCSET (VSET) that referenced DRIVE signal enables over-current comparator (OVERCURRENT). When voltage across upper MOSFET (VDS) exceeds VSET, over-current comparator trips over-current latch. Both VSET referenced small capacitor across ROCSET helps VOCSET track variations MOSFET switching. over-current function will trip peak inductor current (IPEAK) determined
OCSET OCSET PEAK
HIP6021A
TABLE OUT1 VOLTAGE PROGRAM NAME VID4 VID3 VID2 VID1 VID0 NOMINAL DACOUT VOLTAGE 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85
DRIVE3 VSEN3 COUT3 +3.3VIN VAUX
circuitry. Left open, SELECT internally pulled `high' voltage regulated 3.3V during softstart sequence. Once complete, gate drive increased regulator becomes simple pass circuit 3.3V input voltage.
OUT3 OUT4 Voltage Adjustability
voltage (1.5V, OUT3) chip and/or cache memory voltage (1.8V, OUT4) internally simple, low-cost implementation typical Intel motherboard architectures. However, different voltage settings desired these outputs, provides necessary adaptability. Left open (NC), this sets fixed output voltages described above. Grounding this allows both output voltages means external resistor dividers shown Figure
1.90
VOUT3
1.95 2.00 2.05 2.00
COUT4 VOUT4
HIP6021A
DRIVE4 VSEN4
FIGURE ADJUSTING OUTPUT VOLTAGE OUTPUTS
Application Guidelines
Soft-Start Interval
Initially, soft-start function clamps error amplifier's output converter. This generates PHASE pulses increasing width that charge output capacitor(s). After output voltage increases approximately value, reference input error amplifier clamped voltage proportional voltage. resulting output voltages start-up shown Figure soft-start function controls output voltage rate rise limit current surge start-up. soft-start interval surge current programmed soft-start capacitor, CSS. Programming faster soft-start interval increases peak surge current. peak surge current occurs during initial output voltage rise value.
NOTE: connected GND, open connected through pull-up resistors.
OUT2 Voltage Selection
output voltage internally levels, based status SELECT pin. Grounding SELECT enables internal 1.5V regulator control
HIP6021A
Shutdown
HIP6021A features dedicated shutdown (SD). TTL-compatible, logic high signal applied this shuts down (disables) four outputs discharges soft-start capacitor. Following shutdown, logic signal re-enables outputs through initiation soft-start cycle. Left open this will asses logic state, internal pull-down resistor, thus enabling normal operation outputs. output does switch until soft-start voltage (VSS) exceeds oscillator's valley voltage. references each linear's error amplifier clamped soft-start voltage. Holding (with open drain collector signal) turns four regulators. multi-layer printed circuit board recommended. Figure shows connections critical components converter. Note that capacitors COUT each represent numerous physical capacitors. Dedicate solid layer ground plane make critical component ground connections with vias this layer. Dedicate another solid layer power plane break this plane into smaller islands common voltage levels. power plane should support input power output power nodes. copper filled polygons bottom circuit layers PHASE nodes, unnecessarily oversize these particular islands. Since PHASE nodes subjected very high dV/dt voltages, stray capacitor formed between these islands surrounding circuitry will tend couple switching noise. remaining printed circuit layers small signal wiring. wiring traces from control MOSFET gate source should sized carry peak currents.
Layout Considerations
MOSFETs switch very fast efficiently. speed with which current transitions from device another causes voltage spikes across interconnecting impedances parasitic circuit elements. voltage spikes degrade efficiency, radiate noise into circuit, lead device over-voltage stress. Careful component layout printed circuit design minimizes voltage spikes converter. Consider, example, turnoff transition upper MOSFET. Prior turn-off, upper MOSFET carrying full load current. During turn-off, current stops flowing upper MOSFET picked lower MOSFET Schottky diode. inductance switched current path generates large voltage spike during switching interval. Careful component selection, tight layout critical components, short, wide circuit traces minimize magnitude voltage spikes. Application Note AN9836 evaluation board drawings component placement printed circuit board layout typical application. There sets critical components DC-DC converter using HIP6021A controller. switching power components most critical because they switch large amounts energy, such, they tend generate equally large amounts noise. critical small signal components those connected sensitive nodes those supplying critical bypass current. power components controller should placed first. Locate input capacitors, especially highfrequency ceramic decoupling capacitors, close power switches. Locate output inductor output capacitors between MOSFETs load. Locate controller close MOSFETs. critical small signal components include bypass capacitor soft-start capacitor, Locate these components close their connecting pins control Minimize leakage current paths from node, since internal current source only 28µA.
Controller Feedback Compensation
controller uses voltage-mode control output regulation. This section highlights design consideration voltage-mode controller. Apply methods considerations only controller. Figure highlights voltage-mode control loop synchronous-rectified buck converter. output voltage (VOUT) regulated Reference voltage level. reference voltage level output voltage (DACOUT). error amplifier (Error Amp) output (VE/A) compared with oscillator (OSC) triangular wave provide pulse-width modulated (PWM) wave with amplitude PHASE node. wave smoothed output filter CO). modulator transfer function small-signal transfer function VOUT/VE/A This function dominated Gain, given VIN/VOSC shaped output filter, with double pole break frequency zero FESR
Modulator Break Frequency Equations
compensation network consists error amplifier (internal HIP6021A) impedance networks goal compensation network provide closed loop transfer function with high crossing frequency (f0dB) adequate phase margin. Phase margin difference between closed loop phase f0dB degrees. equations below relate compensation network's poles, zeros gain components (R1, Figure these guidelines locating poles zeros compensation network:
HIP6021A
Pick Gain (R2/R1) desired converter bandwidth Place Zero Below Filter's Double Pole (~75% FLC) Place Zero Filter's Double Pole Place Pole Zero Place Pole Half Switching Frequency Check Gain against Error Amplifier's Open-Loop Gain Estimate Phase Margin Repeat Necessary
+5VIN +12V CVCC +3.3VIN VOUT2 OCSET1 DRIVE2 UGATE1 PHASE1 LOAD COUT1 VOUT3 COUT3 +3.3VIN ISLAND POWER PLANE LAYER ISLAND CIRCUIT PLANE LAYER CONNECTION GROUND PLANE LGATE1 HIP6021A VOUT4 DRIVE3 DRIVE4 PGND LOAD COUT2 COMP COCSET1 ROCSET1 LOUT1 VOUT1 VE/A COMP DRIVER DRIVER PHASE VOUT
VOSC
(PARASITIC)
REFERENCE
ERROR
DETAILED COMPENSATION COMPONENTS VOUT
HIP6021A
DACOUT
LOAD
COUT4
LOAD
FIGURE VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN
Compensation Break Frequency Equations
FIGURE PRINTED CIRCUIT BOARD POWER PLANES ISLANDS
Figure shows asymptotic plot DC-DC converter's gain frequency. actual Modulator Gain high gain peak dependent quality factor output filter, which shown Figure Using above guidelines should yield Compensation Gain similar curve plotted. gain. Check compensation gain with capabilities error amplifier. Closed Loop Gain constructed log-log graph Figure adding Modulator Gain Compensation Gain dB). This equivalent multiplying modulator transfer function compensation transfer function plotting gain. compensation gain uses external impedance networks provide stable, high bandwidth (BW) overall loop. stable control loop gain crossing with -20dB/decade slope phase margin greater than degrees. Include worst case component variations when determining phase margin.
GAIN (dB) MODULATOR GAIN
OPEN LOOP ERROR GAIN
COMPENSATION GAIN
FESR 100K
CLOSED LOOP GAIN
FREQUENCY (Hz)
FIGURE ASYMPTOTIC BODE PLOT CONVERTER GAIN
HIP6021A Component Selection Guidelines
Output Capacitors
output capacitors each output have unique requirements. general, output capacitors should selected meet dynamic regulation requirements. Additionally, converters require output capacitor filter current ripple. load transient microprocessor core requires high quality capacitors supply high slew rate (di/dt) current demands.
Increasing value inductance reduces ripple current voltage. However, large inductance values increase converter's response time load transient. parameters limiting converter's response load transient time required change inductor current. Given sufficiently fast control loop design, HIP6021A will provide either 100% duty cycle response load transient. response time time interval required slew inductor current from initial current value post-transient current level. During this interval difference between inductor current transient current level must supplied output capacitor(s). Minimizing response time minimize output capacitance required. response time transient different application load removal load. following equations give approximate response time interval application removal transient load:
TRAN RISE TRAN FALL
Output
Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply transient current slow load rate-of-change seen bulk capacitors. bulk filter capacitor values generally determined (effective series resistance) voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should placed close power pins load physically possible. careful inductance circuit board wiring that could cancel usefulness these inductance components. Consult with manufacturer load specific decoupling requirements. only specialized low-ESR capacitors intended switching-regulator applications bulk capacitors. bulk capacitor's determines output ripple voltage initial voltage drop following high slew-rate transient's edge. aluminum electrolytic capacitor's value related case size with lower available larger case sizes. However, equivalent series inductance (ESL) these capacitors increases with case size reduce usefulness capacitor high slew-rate transient loading. Unfortunately, specified parameter. Work with your capacitor supplier measure capacitor's impedance with frequency select suitable component. most cases, multiple electrolytic capacitors small case size perform better than single large case capacitor.
where: ITRAN transient load current step, tRISE response time application load, tFALL response time removal load. sure check both these equations minimum maximum output levels worst case response time.
Input Capacitors
important parameters bulk input capacitors voltage rating current rating. reliable operation, select bulk input capacitors with voltage current ratings above maximum input voltage largest current required circuit. capacitor voltage rating should least 1.25 times greater than maximum input voltage voltage rating times conservative guideline. current rating requirement input capacitor buck regulator approximately summation load current. input bypass capacitors control voltage overshoot across MOSFETs. ceramic capacitance high frequency decoupling bulk capacitors supply current. Small ceramic capacitors placed very close upper MOSFET suppress voltage induced parasitic circuit impedances. through-hole design, several electrolytic capacitors (Panasonic series Nichicon series Sanyo MV-GX equivalent) needed. surface mount designs, solid tantalum capacitors used, caution must exercised with regard capacitor surge current rating. These capacitors must capable handling surgecurrent power-up. series available from AVX, 593D series from Sprague both surge current tested.
Linear Output Capacitors
output capacitors linear regulators provide dynamic load current. linear controllers dominant pole compensation integrated into error amplifier insensitive output capacitor selection. Output capacitors should selected transient load regulation.
Output Inductor
converter requires output inductor. output inductor selected meet output voltage ripple requirements sets converter's response time load transient. inductor value determines converter's ripple current ripple voltage function ripple current. ripple voltage current approximated following equations:
HIP6021A
MOSFET Considerations
HIP6021A requires external transistors. N-Channel MOSFETs used synchronous-rectified buck topology PWM1 converter. recommended that linear regulator pass element N-Channel MOSFET well. memory linear controllers also each drive MOSFET bipolar pass transistor. these transistors should selected based upon rDS(ON) current gain, saturation voltages, gate supply requirements, thermal management considerations.
+12V LESS
HIP6021A
UGATE PHASE NOTE:
LGATE PGND
NOTE:
MOSFETs
high-current applications, MOSFET power dissipation, package selection heatsink dominant design factors. power dissipation includes loss components; conduction loss switching loss. These losses distributed between upper lower MOSFETs according duty factor (see equations below). conduction losses main component power dissipation lower MOSFETs. Only upper MOSFET significant switching losses, since lower device turns into near zero voltage. equations below assume linear voltage-current transitions model power loss reverserecovery lower MOSFET's body diode. gatecharge losses dissipated HIP6021A don't heat MOSFETs. However, large gate-charge increases switching time, which increases upper MOSFET switching losses. Ensure that both MOSFETs within their maximum junction temperature high ambient temperature calculating temperature rise according package thermal-resistance specifications. separate heatsink necessary depending upon MOSFET power, package type, ambient temperature flow.
UPPER LOWER
FIGURE UPPER GATE DRIVE DIRECT DRIVE OPTION
Rectifier clamp that catches negative inductor swing during dead time between turn lower MOSFET turn upper MOSFET. diode must Schottky type prevent lossy parasitic MOSFET body diode from conducting. acceptable omit diode body diode lower MOSFET clamp negative inductor swing, efficiency could drop percent result. diode's rated reverse breakdown voltage must greater than maximum input voltage.
Linear Controller Transistors
main criteria selection transistors linear regulators package selection efficient removal heat. power dissipated linear regulator
LINEAR
Select package heatsink that maintains junction temperature below rating with maximum expected ambient temperature. When selecting bipolar transistors with linear controllers, insure current gain given operating sufficiently large provide desired output load current when base with minimum driver output current.
rDS(ON) different equations above even same device used both. This because gate drive applied upper MOSFET different than lower MOSFET. Figure shows gate drive where upper MOSFET's gate-to-source voltage approximately less input supply. main power +12VDC bias, gate-to-source voltage lower gate drive voltage +12VDC. logic-level MOSFET good choice logic-level MOSFET used absolute gate-to-source voltage rating exceeds maximum voltage applied VCC.
HIP6021A HIP6021A DC-DC Converter Application Circuit
Figure shows application circuit power supply microprocessor computer system. power supply provides microprocessor core voltage (VOUT1), voltage (VOUT2), voltage (VOUT3), memory voltage (VOUT4) from +3.3V, +5VDC, +12VDC. detailed information circuit, including Bill-ofMaterials circuit board description, Application Note AN9836. Also Intersil's page (http://www.intersil.com) Intersil AnswerFAX (407-724-7800) Document 99836 latest information.
+12VIN +5VIN C1-6 6x1000µF 1000pF
FAULT/RT +3.3VIN OCSET PGOOD 1.0K POWERGOOD
VAUX
DRIVE2 VOUT2 (3.3VIN 1.5V) VSEN2 HUF76121D3S
UGATE PHASE
2xHUF76143S3S
4.2µH
VOUT1 (1.3V-3.5V)
C10, 2x1000µF
LGATE PGND
C12-19 8x1000µF 10.2K
TYPEDET
SELECT
VSEN1 10pF 1.62K 0.22µF
HIP6021A
HUF76107D3S VOUT3 (1.5V) DRIVE3 VSEN3 C23, 2x1000µF HUF76107D3S VOUT4 (1.8V) C25, 2x1000µF DRIVE4 VSEN4 VID0 VID1 VID2 VID3 VID4 0.1µF 2.7nF 150K COMP
499K
FIGURE POWER SUPPLY APPLICATION CIRCUIT MICROPROCESSOR COMPUTER SYSTEM
HIP6021A Small Outline Plastic Packages (SOIC)
INDEX AREA SEATING PLANE 0.25(0.010)
M28.3 (JEDEC MS-013-AE ISSUE
LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 2.35 0.10 0.33 0.23 17.70 7.40 2.65 0.30 0.51 0.32 18.10 7.60 NOTES Rev. 12/93
0.0926 0.0040 0.013 0.0091 0.6969 0.2914
0.1043 0.0118 0.0200 0.0125 0.7125 0.2992
0.10(0.004)
0.05 0.394 0.01 0.016 0.419 0.029 0.050
1.27 10.00 0.25 0.40 10.65 0.75 1.27
0.25(0.010)
NOTES: Symbols defined Series Symbol List" Section Publication Number Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.25mm (0.010 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. lead width "B", measured 0.36mm (0.014 inch) greater above seating plane, shall exceed maximum value 0.61mm (0.024 inch) Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact.
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation 7585 Irvine Center Drive Suite Irvine, 92618 TEL: (949) 341-7000 FAX: (949) 341-7123 Intersil Corporation 2401 Palm Palm Bay, 32905 TEL: (321) 724-7000 FAX: (321) 724-7946 EUROPE Intersil Europe Sarl Ave. William Graisse, 1006 Lausanne Switzerland TEL: 6140560 FAX: 6140579 ASIA Intersil Corporation Unit 1804 18/F Guangdong Water Building Austin Road TST, Kowloon Hong Kong TEL: +852 2723 6339 FAX: +852 2730 1433

FN4793.1 Advanced Triple Linear Power Controller HIP6021A pr

Top Searches for this datasheet

Other recent searches