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Volt Intel® Dual-Plane Flash Memory
28F320D18 (x16)
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32-Mbit density with 16-Bit Data High Performance Reads 110/40 4-Word Page Mode (110/20 Zero Wait-State Synchronous Burst Mode Dual Partition Architecture 25%/75% Partition Sizes Program Erase during Reads Status Register Each Partition Power Operation Read Write Operations VCCQ Isolation System Compatibility Automatic Power Savings Mode Enhanced Code Data Storage Flash Data Integrator (FDI) Software Optimized Typical Program/Erase Suspends 128-Bit Protection Register Unique Device Identifier Bits User-Programmable Bits µBGA* 60-Ball Matrix (four support balls)
Flexible Blocking Architecture Eight, 4-Kword Parameter Code/Data Blocks Sixty-three, 32-Kword Main Code/Data Blocks Enhanced Data Protection Absolute Write Protection Erase/Program Lockout during Power Transitions Individual Dynamic Zero-Latency Block Locking Individual Block Lock-Down Automated Program/Erase Algorithms Low-Power µs/Word (Typ) Programming Glue Logic µs/Word (Typ) Production Programming Erase (Typ) Cross-Compatible Command Support Intel Basic Command Common Flash Interface (CFI) Extended Temperature -40° +85° Minimum 100,000 Block Erase Cycles ETOXVI Flash Technology (0.25
Volt Intel® Dual-Plane Flash memory provides high performance asynchronous synchronous burst reads. ideal memory low-voltage burst CPUs. Combining high read performance with flash memory's intrinsic nonvolatility, Volt Dual-Plane Flash memory eliminates traditional systemperformance paradigm shadowing redundant code memory from slow nonvolatile storage faster execution memory. reduces total memory requirement that increase reliability reduces overall system power consumption cost. Volt Dual-Plane Flash memory's partitions allow background programming erasing occur partition while program-execution reads take place other partition. This allows higher data write throughput compared single partition architectures. dual partition architecture also allows processors interleave code operations while program erase operations take place background. Volt Dual-Plane Flash memory manufactured Intel® 0.25 ETOXVI process technology. available industry-standard µBGA* package which ideal board-constrained applications.
Order Number: 290672-002 October 1999
28F320D18
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. 28F320D18 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1999 *Other brands names property their respective owners.
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28F320D18
Contents
10.0 Introduction Product Description Principles Operation Command Definitions Data Protection Program Erase Voltages.31 Design Considerations Electrical Specifications Ordering Information Additional Information APPENDIX Common Flash Interface APPENDIX Protection Register Addressing.79
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28F320D18
Revision History
Date Revision 09/20/99 10/12/99 Version -001 -002 Original version Corrected Figure "60-Ball µBGA* Package Ballout" Corrected titles Figure -Figure Description
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28F320D18
Introduction
This datasheet contains information about 32-Mbit Volt Intel® Dual-Plane Flash memory. Section provides flash memory overview. Sections through describe memory functionality. Section describes design considerations this device Section describes electrical specifications extended temperature product offerings.
Document Conventions
Throughout this document, references made bottom, top, parameter, main partitions. clarify these references, following convention been adopted:
Main partition: contains only main blocks. Parameter partition: contains mixture main parameter blocks. Bottom partition: partition located lowest physical device address. This partition
main partition parameter partition.
partition: partition located highest physical device address. This partition
main partition parameter partition.
Bottom parameter device: parameter partition bottom memory with
parameter blocks bottom that partition. This formerly referred bottomboot. Since many applications actually boot execute code from (main) blocks treat bottom (parameter) blocks data blocks, bottom-boot top-boot have become misnomers, thus nomenclature change.
parameter device: parameter partition memory with
parameter blocks top. This formerly referred top-boot device.
Main block(s): 32-Kword block Parameter block(s): 4-Kword block
Product Overview
Volt Dual-Plane Flash memory provides simultaneous read while write/erase capability. memory provides high performance reads voltage with 16-bit data bus. Individually erasable blocks optimally sized code data storage. eight 4-Kword parameter blocks located parameter partition. rest device grouped into sixty-three 32-Kword main blocks within main parameter partitions. dividing flash memory array into isolated partitions, simultaneous operation capability permits program block-erase operations during read operations. main partition memory contains only main blocks. parameter partition total memory contains parameter blocks main blocks. Burst reads limited within partition. Usage simultaneous modes will described further throughout this document. device's optimized architecture interface dramatically increases read performance beyond asynchronous reads. device supports asynchronous word accesses, 4-word page mode synchronous burst reads from main blocks. Parameter blocks support asynchronous word accesses, 4-word page mode single synchronous reads only.
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28F320D18
Upon initial power return from reset, device defaults standard asynchronous pagemode read configuration. Writing read configuration register device address enables both partitions' synchronous burst reads. synchronous burst mode, input increments internal burst address generator, synchronizes flash memory with host CPU, outputs data every cycle. WAIT# output signal provides easy CPU-to-flash memory communication synchronization. addition enhanced architecture interface, Volt Dual-Plane Flash memory incorporates technology that enables fast factory programming/erasing low-power designs. Specifically designed low-voltage systems, Volt Dual-Plane Flash memory supports read operations block erase program operations VPP. option renders fastest program/erase performance that increase factory throughput. With option, tied together simple, ultra low-power design. addition voltage flexibility, dedicated gives complete data protection when VPPLK. device's Command User Interface (CUI) system processor's interface Volt DualPlane Flash memory's internal operation. Writing valid command sequence initiates device Write State Machine (WSM) controlled automation that automatically executes blockerase program algorithms timings. status register indicates WSM's state indicating block erase program completion status. industry-standard command sequence invokes block-erase program automation. Each block erase operation erases block. Data programmed word increments. Erase suspend allows system software pause block erase read program data another block same partition. Program suspend allows system software suspend programming read from another location same partition. also possible nest suspends follows: suspend erase first partition, start programming second partition, suspend programming second partition then read from second partition. Volt Dual-Plane Flash memory offers low-power savings features: Automatic Power Savings (APS) standby mode. device automatically enters mode following read cycle completion. Standby mode initiated when system deselects device driving inactive. RST# also resets device read array mode, provides write protection, clears status register. Combined, these features significantly reduce power consumption.
Product Description
Ballouts
Intel Volt Dual-Plane Flash memory available 60-ball matrix with four support balls) µBGA* (Chip Scale Package) package with 0.75 ball pitch that ideal board-constrained applications. Figure "60-Ball µBGA* Package Ballout" page shows component ballout.
Ball Description
Figure "Ball Descriptions" page describes ball usage.
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28F320D18
Table
A0-A20 DQ0-DQ15
Ball Descriptions
Type Name Function ADDRESS INPUTS: memory addresses. 32-Mbit: A0-20 DATA INPUT/OUTPUTS: Inputs data commands during write cycles, outputs data during memory, status register, configuration code reads. Data balls float when chip outputs deselected. Data internally latched during writes. CLOCK: Synchronizes memory system operating frequency synchronous-read configuration. first rising falling RCR.6 edge latches address when ADV# active upon rising ADV# edge. This used only synchronous operation. ADDRESS VALID: ADV# indicates valid address presence address inputs. Addresses latched ADV#'s rising edge during read write operations. This used only synchronous operation. RESET: When low, RST# resets internal automation inhibits write operations. This provides data protection during power transitions. RST#-high enables normal operation. Exit from reset places device asynchronous read array mode. OUTPUT ENABLE: gates device's outputs during read cycle. WRITE ENABLE: controls writes array. Addresses data latched pulse's rising edge. WRITE PROTECT: Controls lock-down function flexible Locking feature. When logic low, lock-down mechanism enabled blocks marked lock-down cannot unlocked through software.
ADV#
RST#
When logic high, lock-down mechanism disabled blocks previously locked-down locked unlocked locked through software. After goes low, blocks previously marked lock-down revert that state. Section details block locking. WAIT: Feeds back data valid status synchronous burst mode while asserted. When high during burst sequence, data valid. WAIT#-low indicates invalid data. WAIT# pulled high internal register. Several component WAIT# signals tied together drive system WAIT signal. WAIT# used only synchronous operation. also works during 8-word burst mode No-Wrap (RCR.3) BLOCK ERASE PROGRAM POWER: valid voltage this allows block erase data programming. Memory contents cannot altered when VPPLK. Block erase program invalid voltages should attempted. 11.4 V-12.6 applied main blocks 1000 cycles maximum parameter blocks 2500 cycles. Maximum connected hours maximum total. this beyond these limits reduce block cycling capability cause permanent damage. DEVICE POWER SUPPLY (1.65 V-1.95 Flash memory writes inhibited VLKO. Device operations invalid voltages should attempted. OUTPUT POWER SUPPLY (1.65 V-1.95 Enables outputs driven 1.65 1.95 This input tied directly VCC. GROUND: float ground pins. GROUND: float ground pins. CONNECT: Lead internally connected; driven floated. DON'T USE: this pin. This should connected power supplies, signals other pins.
WAIT#
VCCQ VSSQ
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28F320D18
Figure 60-Ball µBGA* Package Ballout
VCCQ VSSQ VCCQ VSSQ VSSQ VCCQ VSSQ VCCQ WAIT# WAIT# ADV# ADV# RST# RST#
View Ball Side Down Complete Mark Shown
Bottom View Ball Side
NOTE: Flash upgrade address lines shown (64-Mbit flash) (128-Mbit flash) information purposes only since these devices currently available. Lower density devices will have upper address solder balls. Routing recommended this area.
Memory Blocking Organization
device divided into physical partitions. This allows perform simultaneous readwhile-write read-while-erase operations. device's asymmetrically blocked architecture enables system code data integration within single flash device. Each block erased independently. Figure "32-Mbit Parameter Memory Map" page Figure "32-Mbit Bottom Parameter Memory Map" page block address locations.
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28F320D18
2.3.1
Dual Physical Partitions
device 8-Mb partition parameter blocks plus main blocks) 24-Mb partition main blocks). Only partition time allowed program erase mode. also possible burst reads that cross partition boundaries. Table page summarizes simultaneous commands allowed with dual partitions. detailed description commands allowed using dual partitions Table page
2.3.2
Parameter Blocks
memory architecture includes parameter blocks that allow storage frequently updated small parameters that would normally stored EEPROM. using software techniques, wordrewrite functionality EEPROMs emulated. device contains eight 4-Kword (4,096words) parameter blocks within parameter partition.
2.3.3
Main Blocks
remainder array divided into equal-size 32-Kword main blocks that store code and/or data. Figure "32-Mbit Parameter Memory Map" page Figure "32Mbit Bottom Parameter Memory Map" page
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28F320D18
Figure 32-Mbit Parameter Memory
4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 1FF000h 1FFFFFh 1FE000h 1FEFFFh 1FD000h 1FDFFFh 1FC000h 1FCFFFh 1FB000h 1FBFFFh 1FA000h 1FAFFFh 1F9000h 1F9FFFh 1F8000h 1F8FFFh 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 0D8000h 0DFFFFh 0D0000h 0D7FFFh 0C8000h 0CFFFFh 0C0000h 0C7FFFh 0B8000h 0BFFFFh 0B0000h 0B7FFFh 0A8000h 0AFFFFh 0A0000h 0A7FFFh 098000h 09FFFFh 090000h 097FFFh 088000h 08FFFFh 080000h 087FFFh 078000h 07FFFFh 070000h 077FFFh 32-KWord
0F8000h 0FFFFFh 0F0000h 0F7FFFh 0E8000h 0EFFFFh 0E0000h 0E7FFFh
32-KWord 1F0000h 1F7FFFh 1E8000h 1EFFFFh 1E0000h 1E7FFFh 1D8000h 1DFFFFh 1D0000h 1D7FFFh 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 1C8000h 1CFFFFh 1C0000h 1C7FFFh 1B8000h 1BFFFFh 1B0000h 1B7FFFh 1A8000h 1AFFFFh 1A0000h 1A7FFFh 198000h 19FFFFh 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord
(Parameter) Partition
Bottom (Main) Partition
32-KWord 190000h 197FFFh 188000h 18FFFFh 180000h 187FFFh 178000h 17FFFFh 170000h 177FFFh 168000h 16FFFFh 160000h 167FFFh 158000h 15FFFFh 150000h 157FFFh 148000h 14FFFFh 140000h 147FFFh 138000h 13FFFFh 130000h 137FFFh 128000h 12FFFFh 120000h 127FFFh 32-KWord 118000h 11FFFFh 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord
Bottom (Main) Partition (continued)
068000h 06FFFFh 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord
060000h 067FFFh 058000h 05FFFFh 050000h 057FFFh 048000h 04FFFFh 040000h 047FFFh 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 038000h 03FFFFh 030000h 037FFFh 028000h 02FFFFh 020000h 027FFFh 018000h 01FFFFh
32-KWord 32-KWord 32-KWord Block Number
110000h 117FFFh 108000h 10FFFFh 100000h 107FFFh Address Range
32-KWord 32-KWord 32-KWord Block Number
010000h 017FFFh 008000h 00FFFFh 000000h 007FFFh Address Range
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28F320D18
Figure 32-Mbit Bottom Parameter Memory
32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 088000h 08FFFFh 080000h 087FFFh 078000h 07FFFFh 070000h 077FFFh 068000h 06FFFFh 060000h 067FFFh 058000h 05FFFFh 050000h 057FFFh 090000h 097FFFh 098000h 09FFFFh 0A0000h 0A7FFFh 0A8000h 0AFFFFh 0B0000h 0B7FFFh 0B8000h 0BFFFFh 0C0000h 0C7FFFh 0C8000h 0CFFFFh 0D0000h 0D7FFFh 0D8000h 0DFFFFh 0E0000h 0E7FFFh 0E8000h 0EFFFFh 0F0000h 0F7FFFh
0F8000h 0FFFFFh
(Main) Partition
32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 178000h 17FFFFh 180000h 187FFFh 188000h 18FFFFh 190000h 197FFFh 198000h 19FFFFh 1A0000h 1A7FFFh 1A8000h 1AFFFFh 1B0000h 1B7FFFh 1B8000h 1BFFFFh 1C0000h 1C7FFFh 1C8000h 1CFFFFh 1D0000h 1D7FFFh 1D8000h 1DFFFFh 1E0000h 1E7FFFh 1E8000h 1EFFFFh 1F0000h 1F7FFFh
1F8000h 1FFFFFh
(Main) Partition (continued)
32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 158000h 15FFFFh 150000h 157FFFh 148000h 14FFFFh 140000h 147FFFh 138000h 13FFFFh 130000h 137FFFh 128000h 12FFFFh 120000h 127FFFh 118000h 11FFFFh 110000h 117FFFh 108000h 10FFFFh 100000h 107FFFh 160000h 167FFFh
168000h 16FFFFh
Bottom (Parameter) Partition
32-KWord
170000h 177FFFh
32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord
048000h 04FFFFh 040000h 047FFFh 038000h 03FFFFh 030000h 037FFFh 028000h 02FFFFh 020000h 027FFFh 018000h 01FFFFh 010000h 017FFFh 008000h 00FFFFh 007000h 007FFFh 006000h 006FFFh 005000h 005FFFh 004000h 004FFFh 003000h 003FFFh 002000h 002FFFh 001000h 001FFFh 000000h 000FFFh
Block Number
Address Range
Block Number
Address Range
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28F320D18
Principles Operation
Volt Dual-Plane Flash memory component includes on-chip Write State Machine (WSM) manage block erase program. allows CMOS-level control inputs, fixed power supplies, minimal processor overhead with RAM-like interface timings.
Operations
local reads writes flash memory in-system. flash memory read write cycles conform standard microprocessor cycles.
3.1.1
Read
flash memory's bottom partition, whether top- bottom-parameter configuration, three read modes available: read array, identifier/CFI codes, status register. partition only read array status register read modes. Each partition read modes independent other partition's mode. However simultaneous read commands both partitions allowed. Page mode synchronous burst mode both partitions enabled writing Read Configuration Register command device address. This sets read configuration, burst order, burst length, frequency configuration. read operations, must driven active enable device. device internally decodes upper address inputs determine which partition activated. controls data outputs (DQ0-DQ15) onto when active. must VIH.
3.1.2
Output Disable
With logic-high level (VIH), device outputs disabled. Output pins DQ0-DQ15 placed high-impedance state.
3.1.3
Standby
Deselecting device bringing logic-high level (VIH) places device standby mode, which substantially reduces device power consumption. standby, outputs placed high-impedance state independent OE#. deselected during program erase operation, device continues consume active power until program erase operation complete.
3.1.4
Write
Command User Interface (CUI) does occupy addressable memory location within partition, must accessed system processor correct partition address range. Programming/erasing occur only partition time. other partition must read modes (see Table page
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28F320D18
Table
Simultaneous Commands Allowed with Dual Partitions
(1,2)
Then commands allowed other partition are:
Program Suspend Erase Suspend Read Status Read ID/CFI
Program
partition
Idle Reading Reading Status Register Reading ID/CFI Programming Erasing Program Suspended Erase Suspended
Erase
Read
NOTES: detailed description command allowed using dual partitions Table page Dual Partition Restrictions: Status register reflects partition state, state this allows status register each partition. Only partition programmed erased time command queuing. Commands must written address within block targeted that command. possible burst reads that cross partition boundaries.
3.1.5
Reset
device enters reset mode when RST# driven low. reset mode, internal circuitry turned outputs placed high-impedance state. After return from reset, time tPHQV required until outputs valid, delay (tPHWL tPHEL) required before write sequence initiated. After this wake-up interval, normal operation restored. device defaults read array mode, status register 80H, read configuration register defaults asynchronous reads. RST# taken during block erase program operation, operation will aborted memory contents aborted location longer valid. Figure Waveform Reset Operations" page detailed information regarding reset timings.
3.1.6
Read Query
read query mode only available bottom partition requires that Read Query command written bottom partition. mode outputs Common Flash Interface (CFI) data when device read. data structure contains information such block size, density, command electrical specifications. this mode, read cycles retrieve information. return read array mode, write Read Array command (FFH).
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28F320D18
Flexible Block Locking
both configuration status modes, Volt Dual-Plane Flash memory will decode block locking status registers within each partition. Volt Dual-Plane Flash memory offers instant, individual block locking scheme that allows block locked unlocked with latency, enabling instant code data protection. Volt Dual-Plane Flash memory also features hardware lock-down main blocks parameter blocks. This enables critical code data security while other blocks programmed erased. This locking scheme offers levels protection. first level allows software-only control block locking (useful data blocks that change frequently), while second level requires hardware interaction before locking changed (useful code blocks that change infrequently). Each block Locked, Unlocked, Lock-Down, described following sections. comprehensive state table locking functions shown Table "Block Locking State Transitions" page flowchart locking operations shown Figure "Locking Operations Flowchart" page block Locked, Unlocked LockedDown partition while programming erasing other partition. following sections will discuss operation locking system. term "state [XYZ]" will used specify locking states; e.g., "state [001]," where value WP#, Block Lock status, Block Lock status. Table defines these possible locking states.
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28F320D18
Table
Block Locking State Transitions
Current State Erase/Program Allowed? Lock Command Input Result (Next State) Lock Goes [001] Change Change Goes [101] Change Goes [111] Change Unlock Change Goes [000] Change Change Goes [100] Change Goes [110] Lock-Down Goes [011] Goes [011] Change Goes [111] Goes [111] Goes [111] Change
Name "Unlocked" "Locked" (Default) "Locked-Down" "Unlocked" "Locked" Lock-Down Disabled Lock-Down Disabled
NOTES: this table, notation [XYZ] denotes locking state block, where WP#, DQ1, DQ0. current locking state block defined state bits block lock status (DQ0, DQ1). indicates block locked unlocked (0). indicates block been lockeddown (0). power-up device reset, blocks default Locked state [001] Holding recommended default. "Erase/Program Allowed?" column shows whether erase program operations enabled (Yes) disabled (No) that block's current locking state. "Lock Command Input Result [Next State]" column shows result writing three locking commands (Lock, Unlock, Lock-Down) current locking state. example, "Goes [001]" would mean that writing command block current locking state would change [001].
3.2.1
Locking Operation
following summarizes locking operation.
blocks locked power-up. They then unlocked locked with Unlock
Lock commands.
Lock-Down command locks block prevents from being unlocked when
When Lock-Down overridden. Commands then unlock/lock locked-down blocks. When returns locked-down blocks return Lock-Down. Lock-Down cleared only when device reset powered-down.
3.2.2
Locked State
blocks default locked power-up reset (states [001] [101]). program erase operation attempted locked block will return error SR.1 status register. status locked block changed unlocked lock-down using appropriate command. unlocked block locked writing Lock command sequence, followed 01H.
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28F320D18
3.2.3
Unlocked State
Unlocked blocks (states [000], [100], [110]) programmed erased. unlocked blocks return locked state when device reset powered down. status unlocked block changed locked locked-down using appropriate command. locked block unlocked writing Unlock command sequence, followed D0H.
3.2.4
Lock-Down State
Blocks that locked-down (state [011]) protected from program erase operations (just like locked blocks), their protection status cannot changed using software commands alone. locked unlocked block locked-down writing Lock-Down command sequence, followed 2FH. Locked-down blocks revert locked state when device reset powered down. Lock-Down function dependent input pin. When blocks lock-down [011] protected from program, erase, lock status changes. When lock-down function disabled ([111]) locked-down blocks individually unlocked software command [110] state, where they erased programmed. These blocks then re-locked [111] unlocked [110] desired while remains high. When goes low, blocks that were previously locked-down return lock-down state [011] regardless changes made while high. Device reset power-down resets blocks, including those lock-down, locked state.
3.2.5
Reading Block's Lock Status
lock status every block read device identifier read mode device. enter this mode, write device. Subsequent reads Block Base Address 00002 will output lock status that block. lock status represented lowest output pins, DQ1. indicates block lock/unlock status Lock command cleared Unlock command. also automatically when entering lock-down. indicates lockdown status lock-down command. cannot cleared software, only device reset power-down.
Table
Block Lock Status
Item Block Lock Configuration Block Unlocked Block Locked Block Locked-Down Address Block Base Address +002 Data LOCK
3.2.6
Locking Operations during Erase Suspend
Changes block lock status performed during erase suspend using standard locking command sequences unlock, lock, lock-down block. This useful case when another block needs updated while erase operation progress.
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28F320D18
change block locking during erase operation, first write erase suspend command (B0H), then check status register until indicates that erase operation been suspended. Next write desired lock command sequence block lock status will changed. After completing desired lock, read, program operations, resume erase operation with Erase Resume command (D0H). block locked locked-down during suspended erase same block, locking status bits will changed immediately, when erase resumed, erase operation will complete. Locking operations cannot performed during program suspend.
3.2.7
Status Register Error Checking
Using nested locking program command sequences during erase suspend introduce ambiguity into status register results. Since locking changes performed using cycle command sequence, e.g., followed lock block, following Configuration Setup command (60H) with invalid command will produce lock command error (SR.4 SR.5 will status register. lock command error occurs during erase suspend, SR.4 SR.5 will will remain after erase resumed. When erase complete, possible error during erase cannot detected status register because previous locking command error. similar situation happens error occurs during program operation error nested within erase suspend.
3.2.8
VPPLK Complete Protection
programming voltage held complete write protection blocks flash device. When below VPPLK, block erase program operation will result error, prompting corresponding status register (SR.3) set.
128-Bit Protection Register
Volt Dual-Plane Flash memory includes 128-bit protection register than used enhance security system design. example, number contained protection register used match flash component with other system components such ASIC, preventing device substitution. Additional application information found Intel application note AP-657 Designing with Advanced+ Boot Block Flash Memory Architecture. 128-bit protection register divided into 64-bit segments (Figure "Protection Register Memory Map" page 14). Intel segment programmed Intel factory with unique 64bit number, which changeable. customer segment blank allowing customers program desired. Once customer segment programmed, locked prevent reprogramming.
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28F320D18
Figure Protection Register Memory
0088H
0085H 0084H
Words Customer Programmed
Words Intel Programmed 0081H 0080H Word Lock
3.3.1
Reading Protection Register
protection register read using Read Device Identifier command (90H). Once this mode, read cycles from addresses shown Appendix retrieve specified protection register information. return read array mode, Read Array command (FFH).
3.3.2
Programming Protection Register
protection register bits programmed using two-cycle Protection Program command. 64-bit number programmed bits time. First write Protection Program Setup command, C0H. next write device will latch address data program specified location. allowable addresses shown Appendix Figure "Protection Register Programming Flowchart" page attempt address Protection Program commands outside defined protection register address space should performed. Attempting program previously locked protection register segment will result status register error (program error SR.4 lock error SR.1
3.3.3
Locking Protection Register
customer-programmable segment protection register lockable programming PR-LOCK location this location programmed Intel factory protect unique device number. This using Protection Program command program "FFFD" PR-LOCK location. After these bits have been programmed, further changes made values stored protection register. Protection Program commands locked section will result status register error program error SR.4 lock error SR.1 will Protection register lockout state reversible.
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Table
Command Definitions(1)
Cycles First Cycle Notes Oper Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr(2) Data(3) 40H/ Write Write Write Write Write FFFDH Write Write Read Read Read Oper Addr(2 Data(3) Second Cycle
Command Read Array/Reset Read Device Identification Codes READ PROGRAM ERASE LOCK CONFIGURATION Read Query Read Status Register Clear Status Register Block Erase Program Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-down Block Protection Program Lock Protection Program
Read Configuration Register
Write
Write
NOTE: Commands other than those shown above reserved Intel future device implementations should used. First cycle command addresses should same operation's target address. Examples: firstcycle address Read Device Identification Codes command should same Identification Code address (IA); first cycle address Program command should same word address (WA) programmed; first cycle address Erase/Program Suspend command should same address within block suspended; etc. Identification code address. Address within block. Lock Protection Address obtained from (via Read Query command). Dual-Plane Flash memory's 0080h. User programmable 4-word protection address device identification plane. Address within partition. Query code address. Word address memory location written. Data read from status register. Data written location latched rising edge (whichever goes high first). Identifier code data. =User programmable 4-word protection data. Query code data. Read Configuration register code data presented device addresses A15-0. Upper address bits select either partition. Table read configuration register bits descriptions. Following Read Device Identification Codes Read Query commands, read operations output manufacturer device configuration query information read configuration register. Read Device Identification Read Query addresses must within bottom partition. Following block erase, program, suspend operation, read operations access status register. recognizes either program setup commands.
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Command Definitions
Device operations selected writing specific commands into partition's CUI. Since commands partition-specific, it's important write commands within target partition's address range (see Table page 15).
Read Array Command
Upon initial device power-up after reset, both partitions default read array mode asynchronous read configuration power-up state. Read Array command places addressed partition into read array mode. Once starts block erase program partition, will recognize Read Array command until completes operation until suspended Erase Program Suspend command. However, Read Array command other partition will accepted.
Read Device Identification Command
read device identification mode initiated writing Read Device Identification command bottom partition. partition's mode affected this operation. Table device identifier code values.
Table
Identifier Codes
Code Manufacturer Code Device Code Mbit Mbit Block Lock Configuration Block Unlocked Block Locked Block Locked-Down Read Configuration Register Protection Register Lock Protection Register
Address 00000 00001 00001
Data 0089 88D2 88D3 Lock
Block Address +002
RCR(2) PR-LK(3) PR(4)
00005 0080 0081-0088
NOTE: Sampled, 100% tested. Read Configuration Register PR-LK Protection Register Lock Protection Register
Read Query Command
Read Query command available only bottom partition puts that partition into read query mode. Partition reads will output Common Flash Interface (CFI) information.
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Read Status Register Command
partition's status register read time writing Read Status Register command partition's CUI. Subsequent single transfer read operations that partition will output status register data until another valid command written. This operation does affect other partition's mode. Table status register definitions.
Table
WSMS
Status Register Definition
VPPS NOTES:
SR.7 WRITE STATE MACHINE STATUS (WSMS) Ready Busy SR.6 ERASE SUSPEND STATUS (ESS) Block Erase Suspended Block Erase Progress/Completed SR.5 ERASE STATUS (ES) Error Block Erasure Successful Block Erase SR.4 PROGRAM STATUS (PS) Error Program Successful Program SR.3 STATUS (VPPS) Detect, Operation Abort SR.2 PROGRAM SUSPEND STATUS (PSS) Program Suspended Program Progress/Completed SR.1 DEVICE PROTECT STATUS (DPS) Block Erase Program Attempted Locked Block, Operation Abort Unlocked SR.0 RESERVED FUTURE ENHANCEMENTS
Check SR.7 determine block erase program completion. SR.6-0 invalid while SR.7 "0." When Erase Suspend command issued, halts execution sets both SR.7 SR.6 "1." SR.6 remains until Erase Resume command written CUI. both SR.5 SR.4 "1"s after block erase lock block attempt, improper command sequence entered.
SR.3 does provide continuous feedback. interrogates indicates level only after block erase program operation. SR.3 guaranteed report accurate feedback when VPP1/2 VPPLK. When Program Suspend command issued, halts execution sets both SR.7 SR.2 "1." SR.2 remains until Program Resume command written CUI. block erase program operation attempted locked block, SR.1 aborts operation VIL. SR.0 reserved future should masked when polling status register.
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, SR.1 "1"s only cleared issuing Clear Status Register command. These bits indicate various error conditions. allowing system software reset these bits, several operations performed (such cumulatively erasing writing several bytes sequence). status register polled determine problem occurred during sequence. Clear Status Register command functions independently applied voltage. After executing this command, device returns read array mode. Clear Status Register command clears only status register addressed partition.
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Block Erase Command
two-cycle Block Erase command initiates block erase addressed block within selected partition. After writing command, device automatically outputs status register data when address within partition read. detect block erase completion analyzing partition's status register SR.7. partition will remain status register read mode until another command written CUI. Only partition erase mode time; other partition must read modes.
Program Command
two-cycle command sequence written target partition initiates program operation. Only partition program mode time; other partition must read modes. Program setup (standard alternate 10H) written, followed second write that specifies address data. then takes over, controlling internal program algorithm. After program sequence written, device automatically outputs status register data when read (see Figure "Automated Program Flowchart" page 26). detect completion program event analyzing status register SR.7. When program operation completes, check status register SR.4 error flag ("1"). error detected, check status register bits SR.4, SR.3, SR.1 understand what caused problem. status register partition being programmed examined addressing block address. After examining status register, should cleared error detected before issuing command. partition remains status register read mode until another command written CUI.
Block Erase Suspend/Resume Command
Block Erase Suspend command allows block erase interruption read program data another block within target partition. Once block erase process starts, writing Block Erase Suspend command requests that suspend block erase operation after certain latency period. device continues output status register data when read after Block Erase Suspend command issued. Status Register bits SR.7 SR.6 indicate when block erase operation been suspended (both will "1"). Specification tWHRH2 defines block erase suspend latency. this point, Read Array command written read data from blocks other than that which suspended. Program command sequence also issued during erase suspend program data other blocks. Using Program Suspend command (see Section 4.9), program operation suspended during erase suspend. only other valid commands while block erase suspended Read Status Register, Block Erase Resume, Lock Block, Unlock Block, Lock Down Block Read Configuration Register. During block erase suspend, chip into pseudo-standby mode taking VIH, which reduces active current draw. must remain VPP1/2 while block erase suspended. must also remain VIH.
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28F320D18
resume block erase operation, write Block Erase Resume command CUI. This will automatically clear status register bits SR.6 SR.7. After Erase Resume command written, device automatically outputs status register data when read (seeFigure "Block Erase Suspend/Resume Flowchart" page 27). Block erase cannot resume until program operations initiated during block erase suspend have completed. also possible nest suspends follows: Suspend erase first partition, start programming second partition, suspend programming second partition then read from second partition.
Program Suspend/Resume Command
Program Suspend command allows program interruption read data other flash memory locations within target partition. Once program process starts, writing Program Suspend command requests that suspend program operation after certain latency period. device continues output status register data when read after issuing Program Suspend command. Status register bits SR.7 SR.2 indicate when program operation been suspended (both will "1"). Specification tWHRH1 defines program suspend latency. this point, Read Array command written read data from locations other than that which suspended. only other valid commands while block erase suspended Read Status Register, Program Resume, Read Query Read Device Identification. During program suspend, chip into pseudo-standby mode taking VIH, which reduces active current draw. must remain unchanged. resume program, write Program Resume command CUI. This will automatically clear status register bits SR.7 SR.2. After Program Resume command written, device automatically outputs status register data when read (see Figure "Program Suspend/Resume Flowchart" page 28). also possible nest suspends follows: Suspend erase first partition, start programming second partition, suspend programming second partition then read from second partition.
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28F320D18
Table
Read Configuration Register Definition
NOTES:
RCR.15 READ MODE (RM) Synchronous Burst Reads Enabled Asynchronous Reads Enabled (Default) RCR.14 RESERVED FUTURE ENHANCEMENTS RCR.13-11 FREQUENCY CONFIGURATION (FC2-0) Code reserved future Code reserved future Code Code Code Code reserved future Code reserved future Code reserved future (Default) RCR.10 RESERVED FUTURE ENHANCEMENTS RCR.9 DATA OUTPUT CONFIGURATION (DOC) Hold Data Clock Reserved future (Default) RCR.8 WAIT CONFIGURATION (WC) WAIT# Asserted During Delay WAIT# Asserted Data Cycle Before Delay (Default) RCR.7 BURST SEQUENCE (BS) Intel Burst Order Linear Burst Order (Default) RCR.6 CLOCK CONFIGURATION (CC) Burst Starts Data Output Falling Clock Edge Burst Starts Data Output Rising Clock Edge (Default) RCR.5-4 RESERVED FUTURE ENHANCEMENTS RCR.3 BURST WRAP (BW) Wrap bursts within burst length RCR.2-0 Don't wrap accesses within burst length RCR.2-0.(Default) RCR.2-0 BURST LENGTH (BL2-0) Word Burst Word Burst Reserved future Continuous (Linear) Burst (Default)
Read mode configuration affects reads from main blocks. Parameter block, status register, configuration reads support single read cycles. This reserved future use. reserved bits "0." Section 4.10.2 information about frequency configuration effect initial read. Undocumented combinations bits RCR.14-11 reserved Intel Corporation future implementations should used.
This reserved future use. reserved bits "0." Undocumented combinations bits RCR.10-9 reserved Intel Corporation future implementations should used.
These bits reserved future use. reserved bits "0." Section 4.10.7 information about BURST WRAP configuration.
asynchronous page mode, burst length always equals four words.
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4.10
Read Configuration Command
Read Configuration command writes data Read Configuration register (RCR). This operation initiated two-cycle command sequence. configured writing command device address. Read configuration setup written followed second write that specifies data written read configuration register. This data placed address bus, A15:0, latched rising edge ADV#, CE#, (whichever occurs first). read configuration data sets device's read configuration, burst order, frequency configuration, burst length. command functions independently applied voltage. After executing this command, device returns read array mode. Note: read Read Device Identification command (90H). Address 00005 contains data. Table "Identifier Codes" page bits device power-up reset.
4.10.1
Device Read Configuration
Each partition supports high performance synchronous burst mode read configuration. read configuration register sets read configuration. read Read Device Identification command (90H) address 00005. main partition contains only main blocks supports asynchronous, page mode, synchronous read configurations. status register supports only single asynchronous single synchronous reads. parameter partition's parameter blocks status register support only single asynchronous single synchronous read operations. main blocks support asynchronous, page mode, synchronous read configurations.
4.10.2
Frequency Configuration
frequency configuration informs device number clocks that must elapse after ADV# driven active before data will available. This value determined input clock frequency. Table specific input frequency configuration code.
Table
Frequency Configuration Settings
Frequency Configuration Code Input Frequency (VCC 1.65 V-1.95 -110 Reserved -120 Reserved
Figure "Frequency Configuration" page illustrates data output latency from ADV# going active different frequency configuration codes.
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Figure Frequency Configuration
A20-0
Valid Address
ADV#
Code
DQ15-0 (D/Q)
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Code
DQ15-0 (D/Q)
Valid Output
Valid Output
Valid Output
Valid Output
Code
DQ15-0 (D/Q)
Valid Output
Valid Output
Valid Output
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4.10.3
Data Output Configuration
output configuration determines number clocks that data will held valid. data hold time Dual-Plane Flash memory clock.
Figure Output Configuration
Data Hold DQ15-0 (D/Q)
Valid Output Valid Output Valid Output
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4.10.4
WAIT# Configuration
WAIT# configuration controls behavior WAIT# output signal. This output signal asserted during cycle before output delay when continuous burst length enabled. setting will depend system characteristic. WAIT# also asserted 8-word burst length when RCR.3 (no-wrap mode) no-wrap read crosses first 16-word boundary.
4.10.5
Burst Sequence
burst sequence specifies order which data addressed synchronous burst mode. This order programmable either linear Intel burst order. continuous burst length only supports linear burst order. order chosen will depend characteristic. Table "Sequence Burst Length" page more details.
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Table Sequence Burst Length
Burst Addressing Sequence (Dec) Starting Address (Dec)
Wrap
NoWrap(1) RCR.3
4-Word Burst Length (RCR.2-0 001) Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Intel 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0
8-Word Burst Length (RCR.2-0 010) Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Intel 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-35-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
Continuous Burst (RCR.2-0 111) Linear 0-1-2-3-4-5-6-. 1-2-3-4-5-6-7-. 2-3-4-5-6-7-8-. 3-4-5-6-7-8-9-. 4-5-6-7-8-9-10. 5-6-7-8-9-10-11. 6-7-8-9-10-11-12-. 7-8-9-10-11-12-13.
RCR.3
14-15-16-17-18-19-20-. 15-16-17-18-19-20-21-.
4.10.6
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0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14
0-1-2-3-4-5-6-. 1-2-3-4-5-6-7-. 2-3-4-5-6-7-8-. 3-4-5-6-7-8-9-. 4-5-6-7-8-9-10. 5-6-7-8-9-10-11. 6-7-8-9-10-11-12-. 7-8-9-10-11-12-13.
NOTE: burst wrap (RCR.3) determines whether 8-word burst-accesses wrap within burst-length boundary whether they cross word-length boundaries perform linear accesses. no-wrap mode (RCR.3 device operates similar continuous linear burst mode consumes less power during 8-word bursts.
Clock Configuration
clock configuration configures device start burst cycle, output data, assert WAIT# rising falling edge clock. This flexibility enables interfacing Volt Dual-Plane Flash memory wide range burst CPUs.
14-15-16-17-18-19-20-. 15-16-17-18-19-20-21-.
28F320D18
4.10.7
Burst Wrap
burst wrap determines whether 8-word burst-accesses wrap within burst-length boundary whether they cross word-length boundaries perform linear accesses. No-wrap mode (RCR.3 enables WAIT# hold system processor, does continuous burst mode. no-wrap mode, device operates similar continuous linear burst mode consumes less power during 8-word bursts. example, RCR.3 (wrap mode) RCR.2-0 (4-word burst length), then possible linear burst sequences 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2. RCR.3 (no-wrap mode) RCR.2-0 (4-word burst length), then possible linear burst sequences 0-1-2-3, 1-2-3-4, 2-3-4-5, 3-4-5-6. RCR.3 only enables limited nonaligned sequential burst, also reduces power minimizing number internal read operations. above 4-word burst sequences also achieved setting RCR.2-0 bits continuous linear burst mode (111). However, significantly more power consumed. 1-2-3-4 sequence, example, will consume power during initial access, again during internal pipeline lookup processor reads word possibly again, depending system timing, near sequence device pipelines next 4-word sequence. RCR.3 mode reduces this excess power consumption.
4.10.8
Burst Length
burst length number words that device will output. device supports burst lengths four eight words. also supports continuous burst mode. continuous burst mode, device will linearly output data until internal burst counter reaches device's burst-able address space partition boundary. Bits RCR.2-0 read configuration register burst length.
4.10.8.1
Continuous Burst Length
When operating continuous burst mode 8-word burst with burst wrap (RCR.3 flash memory incur output delay when burst sequence crosses first sixteen word boundary. starting address dictates whether delay will occur. starting address aligned four word boundary, delay will seen. starting address four word boundary, output delay will equal frequency configuration setting; this worst case delay. delay will only take place once during continuous burst access. burst sequence never crosses sixteen word boundary, delay will never happen. flash memory uses WAIT# output continuous burst configuration inform system this output delay occurs.
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28F320D18
Figure Automated Block Erase Flowchart
Start
Operation
Command
Comments Data Addr Within Block Erased Data Addr Within Block Erased Status Register Data Addr Within Block Erased Check SR.7 Ready Busy
Write 20H, Block Address Write D0H, Block Address Suspend Blk. Erase Loop Full Status Check Desired Suspend Block Erase
Write
Erase Setup
Write
Erase Confirm
Read
Read Status Register
Standby
Repeat subsequent block erasures. Full status check done after each block erase after sequence block erasures. Write after last operation place device read array mode.
SR.7
Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.1 SR.4, SR.5 Block Erase Successful
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Operation Standby
Command
Comments Check SR.3 Error Detect Check SR.1 Device Protect Detect Check SR.4, Both Command Sequence Error Check SR.5 Block Erase Error
Range Error
Standby
Device Protect Error
Standby
Standby
Command Sequence Error
SR.5, SR.4, SR.3 SR.1 only cleared Clear Staus Register command, cases where multiple blocks erased before full status checked. error detected, clear status register before attempting retry other error recovery.
Block Erase Error
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Figure Automated Program Flowchart
Start
Operation
Command
Comments Data Addr Location Written Data Data Written Addr Location Written Status Register Data Addr Location Written Check SR.7 Ready Busy
Write 40H, Address Write Data Address
Write
Program Setup
Write
Data
Read
Read Status Register Suspend Program
Suspend Program Loop
Standby Repeat subsequent byte writes.
SR.7 Full Status Check Desired
full status check done after each word write after sequence program operations. Write after last word write operation place device read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above)
Operation Command Comments Check SR.3 Error Detect Check SR.1 Device Protect Detect Check SR.4 Program Error
SR.3 SR.1 SR.4 Program Successful Program Error Range Error Device Protect Error
Standby Standby
Standby
SR.4, SR.3 SR.1 only cleared Clear Staus Register command, cases where multiple locations written before full status checked. error detected, clear status register before attempting retry other error recovery.
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Figure Block Erase Suspend/Resume Flowchart
Start
Operation Write
Command Erase Suspend
Comments Data Addr Block Address Status Register Data Addr Block Address Check SR.7 Ready Busy Check SR.6 Block Erase Suspended Block Erase Completed
Write
Read
Read Status Register
Standby
SR.7 SR.6 Read Read Write? Done Write
Standby
Write
Erase Resume
Data Addr Block Address
Block Erase Completed
Program
Read Array Data
Program Loop
Write
Block Erase Resumed
Read Array Data
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Figure Program Suspend/Resume Flowchart
Start
Operation Write
Command Program Suspend
Comments Data Addr Block Address Status Register Data Addr Block Address Check SR.7 Ready Busy Check SR.2 Program Suspended Program Completed
Write
Read
Read Status Register
Standby
SR.7 SR.2 Write
Standby
Write
Read Array
Data Addr Block Address Read array locations from block other than that being written
Program Completed
Read
Write
Program Resume
Data Addr Block Address
Read Array Data
Done Reading Write
Write
Program Resumed
Read Array Data
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Figure Locking Operations Flowchart
Start
Operation Write
Command Config. Setup
Comments Data Addr Within block lock Data= (Lock Block) (Unlock Block) (Lockdown Block) Addr=Within block lock Status Register Data Addr=Within block lock Check Status Register error Lock Command Sequence Error
Write (Configuration Setup) Write 01H, D0H,
Write
Lock, Unlock, Lockdown
Read (Optional) Standby (Optional)
Read Status Register Lock Command Sequence Error
Write (Optional) Read (Optional) Read Configuration Block Lock Status
Data Addr=Within block lock Block Lock Status Data Addr Second addr block Confirm Locking Change DQ1, DQ0. (See Block Locking State Table valid combinations.)
SR.4, SR.5 Write (Read Configuration)
Standby (Optional)
Read Block Lock Status
Locking Change Confirmed?
Locking Change Complete
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Figure Protection Register Programming Flowchart
Start
Operation Write Write
Command Protection Program Setup Protection Program
Comments Data Data Data Program Addr Location Program Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Write (Protection Reg. Program Setup) Write Protect. Register Address/Data
Read
Standby
Read Status Register
SR.7 Full Status Check Desired
Protection Program operations only addressed within protection register address space. Addresses outside defined space will return error. Repeat subsequent programming operations. Full Status Check done after each program after sequence program operations. Write after last program operation reset device read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3, SR.4 Range Error SR.1, SR.4
Standby Operation Standby Command Comments SR.1 SR.3 SR.4 Prot. Reg. Prog. Error Register Locked: Operation Aborted
Protection Register Programming Error Attempted Program Locked Register Aborted
Standby
SR.3 MUST cleared, during program attempt, before further attempts allowed Write State Machine.
SR.1, SR.4
SR.1, SR.3 SR.4 only cleared Clear Staus Register Command, cases multiple protection register program operations before full status checked. error detected, clear status register before attempting retry other error recovery.
Program Successful
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Data Protection
Volt Dual-Plane Flash memory architecture features dynamic hardware block-locking critical code kept secure while non-locked blocks programmed erased.
VPPLK Complete Protection
programming voltage held complete write protection flash device blocks. When below VPPLK, block erase program operations result error corresponding partition's status register; (SR.3) set.
Block Lock Down
Locked down blocks securely permanently locked down when VIL; block erase program operation locked-down block will result error, which will reflected status register.
Program Erase Voltages
Intel Volt Dual-Plane Flash memory provides in-system programming erase range. fast production programming, Volt Dual-Plane Flash memory includes low-cost, backward-compatible high-performance Improved-12 programming feature. When between VPP1 VPP1 max, program erase current drawn through pin. Note that driven logic signal, must remain above VPP1 perform in-system flash modifications. When connected power supply, device draws program erase current directly from pin. This eliminates need external switching transistor control voltage. Figure "Example Power Supply Configurations" page shows examples flash power supplies configured various usage models.
Improved-12 Programming Operation Fast Manufacturing
mode enhances programming performance during short period time typically found manufacturing processes; however, intended extended use. applied during program erase operations maximum 1000 cycles main blocks 2500 cycles parameter blocks. connected total hours maximum. Stressing device beyond these limits cause permanent damage.
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Design Considerations
This section will describe design with Volt Dual-Plane Flash memory. will focus dual partition architecture well integrated features device. Today's high-performance CPUs ASICs designed portable handheld applications place relentless demands memory increased data transfer speeds, well very power operation. This requires memory approach help bridge performance between processor memory. Volt Dual-Plane Flash memory satisfies both these requirements operating volts also providing hardware simultaneous read-while-program/erase capabilities through dual partition architecture. also supports high-performance interfaces (asynchronous page mode synchronous burst mode max) with zero wait states. This section will cover these features implement them designs using Volt Dual-Plane Flash memory. following list topics that will covered:
Flash Hardware Design Considerations. Flash Software Design Considerations. System Design Considerations. Design Tools Software
detailed device specifications more information, refer Section 10.0 full list companion documents.
7.1.1
Flash Hardware Design Considerations
Flash Power Consumption
While operation, flash device consumes active power. Intel® Flash devices have power saving features, Automatic Power Savings (APS) standby modes that reduce overall memory system power consumption.
7.1.1.1
Active Power
With logic-low level RST# logic-high level, device active mode. Only partition time active both partitions read mode. However, both partitions active simultaneously read mode other performing background program erase. active "read" partition selected when valid partition address present. Table page simultaneous commands allowed with dual partitions.
7.1.1.2
Using No-Wrap Mode
burst wrap (RCR.3) Read Configuration Register determines whether 8-word burst-accesses wrap within burst-length boundary whether they cross word-length boundaries perform linear accesses. No-wrap mode (RCR.3 enables WAIT# hold system processor, does continuous burst mode. no-wrap mode, device operates similar continuous linear burst mode consumes less power during 8-word bursts. RCR.3 lower power operation non-wrapped linear bursts.
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example, RCR.3 (wrap mode) RCR.2-0 (4-word burst length), then possible linear burst sequences 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2. RCR.3 (no-wrap mode) RCR.2-0 (4-word burst length), then possible linear burst sequences 0-1-2-3, 1-2-3-4, 2-3-4-5, 3-4-5-6. RCR.3 only enables limited nonaligned sequential burst, also reduces power minimizing number internal read operations. above 4-word burst sequences also achieved setting RCR.2-0 bits continuous linear burst mode (111). However, significantly more power consumed. 1-2-3-4 sequence, example, will consume power during initial access, again during internal pipeline lookup processor reads word possibly again, depending system timing, near sequence device pipelines next 4-word sequence. RCR.3 (no-wrap mode) mode reduces this excess power consumption.
7.1.1.3
Automatic Power Savings
Automatic Power Savings (APS) provides low-power operation during active mode, allowing flash itself into current state when being accessed. After data read from memory array, device's power consumption enters mode where typical current comparable ICCS. flash memory stays this static state with outputs valid until location read.
7.1.1.4
Standby Power
With logic-high level (VIH) both partitions read mode, flash memory standby mode. Outputs (DQ0-DQ15) placed high-impedance state independent signal's state. transitions logic-high during erase program operations, device continues operation, consuming corresponding active power until operation completes.
7.1.1.5
Power-Up/Down Operation
device protected against accidental block erasure programming during power transitions. Power supply sequencing required, since device does care which power supply, VPP, VCC, VCCQ, powers first.
7.1.1.5.1
RST# Connection
RST# during system reset important with automated program/erase devices since system expects read from flash memory when comes reset. reset occurs without flash memory reset, proper initialization will occur because flash memory providing status information instead array data. Intel recommends connecting RST# system reset signal allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when voltages above VLKO active. Since both must command write, driving either signal will inhibit writes device. architecture provides additional protection since alteration memory contents only occur after successful completion two-step command sequences. device also disabled until RST# brought VIH, regardless state control inputs. holding device reset during power-up/down, invalid conditions during power-up masked, providing another level memory protection.
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7.1.1.5.2
VCC, VPP, RST# Transitions
latches commands issued system software altered transitions actions. default state upon power-up, after exit from deep power-down mode after transitions above VLKO (lockout voltage), read array mode. After block erase program operation complete (even after transitions down VPPLK), must reset read array mode Read Array command access flash memory array desired.
Figure Example Power Supply Configurations
System Supply
System Supply Supply Fast Programming Absolute Write Protection With VPPLK System Supply
(Note
Prot# (Logic Signal)
Low-Voltage Programming Absolute Write Protection Logic Signal System Supply
Low-Voltage Programming
PSU_CONF
Supply Voltage Fast Programming
NOTE: resistor used supply sink adequate current based resistor value. AP-657 Designing with Advanced+ Boot Block Flash Memory Architecture details.
7.1.1.6
Power Supply Decoupling
Flash memory's power switching characteristics require careful device de-coupling. System designers should consider three supply current issues:
Standby current levels (ICCS) Active current levels (ICCR) Transient peaks produced falling rising edges CE#.
Transient current magnitudes depend device outputs' capacitive inductive loading. Twoline control proper de-coupling capacitor selection will suppress these transient voltage peaks. Each flash device should have ceramic capacitor connected between each VCC, VCCQ VSSQ, between VSS. These high-frequency, inherently low-inductance capacitors should placed close possible package leads.
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7.1.1.6.1
Circuit Board Trace
Designing in-system writes flash memory requires special consideration power supply trace printed circuit board designer. supplies flash memory cells current programming erasing. trace widths layout should similar that VCC. Adequate supply traces, decoupling capacitors placed adjacent component, will decrease spikes overshoots.
7.1.2
Flash Core Voltage
Volt Dual-Plane Flash memory matches true EIA/JEDEC Standard from 1.65 1.95 read program down 1.65 flash device separated into sections, core (Figure 14). There separate power pins, VCCQ which provide power device's core, respectively. separate VCCQ help provide noise isolation from power supply when connected separate Volt supply. must always same higher voltage than voltage applied VCCQ, they connected together.
Figure Flash Core Voltage Separation
VCCQ
Data Pins
CORE
total power consumption device power consumed core power consumed I/Os. total power used pins function voltage, operating frequency, capacitance pins shown following equation. load capacitance switching frequency. PREAD_I/O (VCCQ)2 (number pins) More information power consumption found applications note AP-641 Achieving Power with Advanced Boot Block Flash Memory. fast production programming, Volt Dual-Plane Flash memory includes programming feature. With connected VPP, programming time significantly reduced, which important fast factory programming. When used mobile applications where second supply unavailable, program voltage must 1.65 V-1.95 during program erase cycles. Connecting supply (11.4 V-12.6 should only done maximum 1000 cycles main blocks 2500 cycles parameter blocks, should connected more than hours.
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7.2.1
Flash Software Design Considerations
Conventions Definitions
Throughout this section references made words phrases which explained below.
Plane Partition: Both these words refer memory areas within flash device.
memory plane memory area with address range. main array, status register, ID/protection register query different read planes. These planes accessed putting device into desired mode commands Command User Interface. main array plane split into physical partitions, with continuous address range throughout partitions.
Writing command Writing array: write memory cycle where
asserted. used command data into device. write command issued change device's mode. does need valid during write command operations. Writing array, programming, refers storing memory into array plane. This done with two-cycle write command, valid during program operation.
Current Partition: This partition which commands currently being written.
example, data being programmed into bottom partition, this becomes current partition partition referred other partition. after that, program command issued partition, then becomes current partition bottom partition other partition.
Other Partition: partition, which either idle busy, which commands
currently being written.
Current State: state that Command User Interface currently either
current partition other partition.
Next State: This will state flash component after received command
into this state.
Setup: This refers current state either partition. Setup refers erase, program,
protection register, block lock/unlock/lock-down Read Configuration Register setup.
Busy: other partition busy state when erase, program protection register
program mode.
Idle: other partition idle mode when setup, busy, erase/program suspend
mode.
Lock Block Unlock Block One-Time Programmable Protection Register Read Configuration Register Erase Suspend Program Suspend Block Erase
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7.2.2
Using Dual Partitions
This section describes four examples synthesizing flash component's next state, knowing current state each partition input. These examples will Table page these examples, partitions will referred partition bottom partition. Also, each example assumes that both partitions start read array mode. Table will help with software design showing allowable commands that partition accept based mode other partition. Sheets Table should read placing them adjacent each other. Sheets continuations Sheets shown numbers.
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Table Write State Machine Next State Table (Sheet
Current State Current Command Input Current Partition (and Next State Partition Current Partition) Data when SR.7 read Mode
Read Array Program Setup Erase Setup Program/Erase Suspend (B0H) Number Read Array Read Array Read Array Read Array Query Read Read Array Program Setup Erase Setup Read Array Read Array Device Identification Read Array Program Setup Erase Setup Read Array Read Array Status Status Read Array Program Setup Erase Setup Read Array Setup Status Lock/RCR Error Read Array Error Status Read Array Program Setup Erase Setup Read Array Lock/RCR Read Array Lock/Unlock Block Status Read Array Program Setup Erase Setup Read Array Read Array Array Read Array Program Setup Erase Setup Read Array Setup Protection Register Busy Status Status Protection Register (Busy) Protection Register (Busy) Read Array Done Status Read Array Program Setup Erase Setup Read Array Read Array Read Array Read Array Read Array Read Array Read Array Read Array Read Array LB/ULB L/RCR Error Read Array Read Array Read Array Read Array Read Array Read Array Confirm, Resume, Confirm (D0H)
Number
Current state Other Partition
Setup Busy Idle Erase Suspend Prog. Suspend Setup Busy Idle Erase Suspend Prog. Suspend Setup Busy Idle Erase Suspend Prog. Suspend Setup Busy Idle Erase Suspend Prog. Suspend State Setup Busy Idle Erase Suspend Prog. Suspend Setup Busy Idle Erase Suspend Prog. Suspend Setup Busy Idle Erase Suspend Prog. Suspend Idle Idle Setup Busy Idle Erase Suspend Prog. Suspend
State
(FFH)
(10H/40H)
(20H) Read Array
Array
Array
Read Array
Program Setup
Erase Setup
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Table Write State Machine Next State Table (Sheet
Command Input Current Partition (and Next State Current Partition)
Number Clear Status Register (50H) Lock Block Confirm (01H) Read Array Read Status Read Array Read Device Read Query Lock/RCR Setup Setup Read Array Read Array Read Array Read Status Read Array Read Device Read Query Lock/RCR Setup Setup Read Array Read Array Read Array Read Status Read Array Read Device Read Query Lock/RCR Setup Setup Read Array Read Array Read Array Read Status Read Array Read Device Read Query Lock/RCR Setup Setup Read Array Read Array Lock/RCR Error LB/ULB LB/ULB Lock-Down Block Confirm (2FH) Write Confirm (03H) Number Read Array Read Status Read Array Read Device Read Query Lock/RCR Setup Setup Read Array Read Array Read Array Read Status Read Array Read Device Read Query Lock/RCR Setup Setup Read Array Read Array Protection Register (Busy) Protection Register (Busy) Read Array Read Status Read Array Read Device Read Query Lock/RCR Setup Setup Read Array Read Array Lock/Unlock, Lock-Down, Write Setup (60H)
Read Status
Read Device
Read Query
Setup
(70H)
(90H)
(98H)
(C0H)
Read Status Read Array Read Device Read Query Lock/RCR Setup Setup
Read Array Read Array Read Array
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Table Write State Machine Next State Table (Sheet
Current State Current Command Input Current Partition (and Next State Current Partition) Partition Current state Other Partition Data when SR.7 read
Status Status Read Array Program Setup Erase Setup Confirm, Resume, Confirm Program/Erase Suspend
Number
Mode
State
(FFH) State Idle Program Setup Busy Idle Erase Suspend Prog. Suspend Setup Idle Erase Suspend Program Suspend Setup Idle Erase Suspend Setup Idle Erase Suspend Setup Idle Erase Suspend Idle Setup Busy Idle Erase Suspend Erase Prog. Suspend Setup Busy Idle Erase Suspend Prog. Suspend Idle Setup Busy Idle Prog. Suspend Setup Busy Idle Prog. Suspend Setup Busy Idle Prog. Suspend Setup Busy Idle Prog. Suspend Read Query Erase Suspend Read Array Array Read Status Status Busy Status Done Status Read Array Error Status Read Array Setup Status Read Query Read Array Array Read Status Status Setup Busy
(10H/40H)
(20H) Program (Busy)
(D0H)
(B0H) Read Status Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Erase Error Read Array Read Array Read Status Read Array Read Array Read Array Read Array Read Array Read Array Read Array Read Array
Program (Busy) Read Array
Done
Status
Read Array
Program Setup
Erase Setup Read Array
Read Array
Program Suspend Read Array
Program (Busy)
Program Suspend Read Array
Program (Busy)
Read Device
Program Suspend Read Array
Program (Busy)
Program Suspend Read Array Erase Error Read Array Program Setup Erase Setup Read Array Read Array Program Setup Erase Setup Read Array Erase (Busy)
Program (Busy) Erase (Busy)
Read Array
Read Array
Erase (Busy) Erase Suspend Read Array Erase Suspend Read Array Read Array Program Setup Read Array Erase (Busy) Erase Suspend Read Array Erase (Busy) Erase Suspend Read Array Erase Suspend Read Array Read Array Program Setup Read Array Erase (Busy) Erase Suspend Read Array Erase (Busy) Erase Suspend Read Array Erase Suspend Read Array Read Array Program Setup Read Array Erase (Busy) Erase Suspend Read Array Erase (Busy) Erase Suspend Read Array Erase Suspend Read Array Read Array Program Setup Read Array Erase (Busy) Erase Suspend Read Array
Read Device
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28F320D18
Table Write State Machine -Next State Table (Sheet
Command Input Current Partition (and Next State Current Partition)
Lock/Unlock, Lock-Down, Write Setup (60H) Program (Busy) Program (Busy) Read Array Read Status Read Array Read Device Read Query Lock/RCR Setup Setup Read Array Read Array
(70H)
(50H)
(90H)
(98H)
(C0H)
(01H)
(2FH)
(03H)
Program Program Program Program Suspend Read Suspend Read Suspend Read Suspend Read Status Device Array Query Program Program Program Program Suspend Read Suspend Read Suspend Read Suspend Read Status Array Device Query Program Program Program Program Suspend Read Suspend Read Suspend Read Suspend Read Array Device Query Status Program Program Program Program Suspend Read Suspend Read Suspend Read Suspend Read Array Device Query Status Erase Erase Erase Erase Suspend Suspend Read Suspend Read Suspend Read Read Device Status Array Query Erase Erase Erase Erase Suspend Suspend Read Suspend Read Suspend Read Read Device Status Array Query Erase Erase Erase Erase Suspend Suspend Read Suspend Read Suspend Read Read Device Array Status Query Erase Erase Erase Erase Suspend Suspend Read Suspend Read Suspend Read Read Device Status Array Query Lock/RCR Setup Lock/RCR Setup Lock/RCR Setup Lock/RCR Setup Block Erase (Busy) Read Status Read Array Read Device Read Query Lock/RCR Setup Read Status Read Array Read Device Read Query Lock/RCR Setup Erase Error
Program Suspend Read Array
Program Suspend Read Array
Program Suspend Read Array
Program Suspend Read Array
Read Array Setup Read Array Read Array Read Array Setup Read Array Read Array
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Read Array
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Number
Read Status
Clear Status Register
Read Device
Read Query
Setup
Lock Block Confirm
Lock-Down Block Confirm
Write Confirm
28F320D18
7.2.2.1
Basic Status Register Read
first example shows read status register partition. current state partition read array mode, bottom partition idle. This shown state table When Read Status Register command (70H) issued, next state becomes Read Status (Table 18). Subsequent reads from this partition will output status register data. Throughout these operations, bottom partition stays idle.
7.2.2.2
Erase Suspend Read
next example will show suspend erase operation partition read information from same partition. current state partition read array mode, bottom partition idle (row When Erase Setup command (20H) issued, partition into Erase Setup state (row 63). order start erase, Erase Confirm command given which puts partition into Erase (busy) state (row 74). Before erase completed, information needs read from different block within same partition. this, Erase Suspend (B0H) command issued. This only command that this partition will accept; other commands will ignored. partition then goes into Erase Suspend Read Status state (row 77). status register read determine when erase been successfully suspended. this point Read Array command given which puts partition into erase suspend read array mode (row 81). Array data read. partition will stay this mode, erase will stay suspended until Erase Resume command (D0H) issued which returns partition back Erase (busy) state. When erase completed, partition will into Erase (done) state (row 72), partition ready accept another command.
7.2.2.3
Read While Erase/Program
This example will describe reading from bottom partition while partition erase mode. bottom partitions both initially read array mode (row partition issued Erase Setup (20H) command putting partition into Erase Setup state (row 63). Erase Confirm command then given, putting partition into Erase (busy) state. Information from bottom partition then needs read. state table used show state bottom partition, which become current partition. state shown partition already read array mode, Read Array command does have issued. however, device different read mode, such read status mode, then Read Array command will have issued. block partition continues erased throughout read cycle. When erase completed, current state partition shown partition ready accept command.
7.2.2.4
Read While Program-Suspend During Erase-Suspend
This example will outline reading from bottom partition while partition erase suspend mode bottom partition program mode. Both bottom partitions initially read array mode. Erase Setup command issued partition, putting into Erase Setup, Erase Confirm command then issued partition which starts erasing block (row 74). this point data needs programmed into bottom partition. erase partition suspended issuing Erase Suspend command. state table used show state bottom partition. current state shown read array mode while other partition Erase Suspend mode. Program Setup command issued bottom partition. next command partition programs device, puts partition into Program (busy) state, this point, data from bottom partition needs read. program cycle suspended with Program Suspend command. current state shown Issuing Read Array command bottom partition will into
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Program Suspend Read Array state, Array data read. When array data been read, program resumed writing Program Resume command. partition goes back program mode, then completes programming device. bottom partition then idle, partition still erase suspend mode. state table shows current state partition Erase Resume command resumes erase. When erase completed, both partitions idle, accept commands.
7.2.3
Addresses during Writes Flash
previous Intel Flash products such Fast Boot Block Intel® StrataFlashmemory families, address while writing command don't care. Volt Dual-Plane Flash memory this address should address location which command referring (see Table page 15). example, first address block erase command should address within that block; first address program command should address word programmed.
7.3.1
System Design Considerations
Compatibility
Volt Dual-Plane Flash memory supports high-performance read modes:
Asynchronous page mode Synchronous burst mode
These read modes allow processor, capable, achieve much higher bandwidth than previously possible using single read accesses. asynchronous page mode ideal nonclocked memory systems compatible with standard page-mode ROM. memory subsystem access external processor referenced clock, synchronous burst mode used increased read performance, provided clock frequency below MHz. system ASIC does support burst page-mode reads, single synchronous asynchronous reads possible. Whether flash component synchronous asynchronous mode depends setting Configuration Register. Setting enables synchronous burst reads, setting enables asynchronous reads. Upon reset, device defaults asynchronous page mode, into read array mode. This corresponds state most processors upon startup. important reset flash memory device when processor reset. This because when processor returns from reset will request memory from flash array. flash been reset, possible read status read mode, which would then return unwanted data processor.
7.3.2
Flash Integrated Features
enabling compatibility between Volt Dual-Plane Flash memory today's burstcapable microprocessors Volt Dual-Plane Flash memory's integrated features. These features, listed explained below, help simplify eliminate excess system interface logic.
Address Latch
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Read Configuration Register Status Register WAIT# Output
7.3.2.1 Address Latch
address latch latches address during read write cycles. internal address latch controlled ADV#. When ADV# low, latch open. latch closes when ADV# driven high upon first rising falling) edge when ADV# low. This stores current address into flash memory device lets address change without affecting flash. This works same write operations; address written gets latched rising ADV# edge. Since writes asynchronous, ignored address latched clock edge. During asynchronous reads address latch does need used, addresses must then stay stable during entire read operation. ADV# used, addresses latched rising edge during reads, rising edge during writes, whichever goes high first.
7.3.2.2
Read Configuration Register
read configuration register 16-bit register which sets device's read configuration, burst order, frequency configuration burst length. This register stored volatile memory within memory device, initialized upon return from reset. With Read Configuration Register, features flash memory device easily changed. Previous flash memory devices such Advanced Boot Block Intel StrataFlash memory families contain this register; rather features these devices were hardware were unchangeable. Being able change these features allows single flash memory component have several different hardware features, configurable user. This allows this flash chip work with wide array processors, regardless their hardware requirements.
7.3.2.3
Status Register
Volt Dual-Plane Flash memory contains status registers, each partition. Each eight-bit register which contains current information about write state machine, logic which controls programming erasing device's memory blocks. This register will report program erase command completed successfully, not, reason error. Also this register will report when program erase been suspended, that processor then issue program, erase, read command. This register cannot written only cleared, issuing Clear Status Register command, resetting device.
7.3.2.4
WAIT# Output
Volt Dual-Plane Flash memory supports four-word, eight-word, continuous burst lengths. continuous burst length, 8-word burst accesses with RCR.3 output ball, WAIT# provided simplify memory communication. WAIT# informs system when data valid. logic there valid data bus, logic data invalid. Figure "WAIT# Connection Using Multiple Flash Memory Components" page shows WAIT# signal OR'd interface CPU, multiple flash components.
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28F320D18
Figure WAIT# Connection Using Multiple Flash Memory Components
Wire OR'd WAIT#
READY#
WAIT#
Burst System Wait-State Logic
Volt Dual-Plane Flash Memory
Data
DQ15-0
WAIT#
Volt Dual-Plane Flash Memory
DQ15-0
7.3.3
Using Asynchronous Page Mode
Upon power-up return from reset, device defaults asynchronous page mode, with page size four words. This read mode only supported from main blocks, supported from other locations within device, such parameter blocks, device identification codes, query information, status register. asynchronous page mode, ignored ADV# must held throughout page access. With ADV# low, internal address latch open, allowing page accesses. initial valid address will store four words data internal page buffer. Each word then output onto data lines toggling address lines A1-0. application only uses asynchronous page mode capability, ADV# tied VSS, shown Figure "Different Clock Options" page This shows ideal, glueless interface. processor does provide these signals, some glue logic required. More information signal generation covered later this section. Grounding ADV# will minimize power consumed these pins will simplify interface, making compatible with standard flash memory industry standard page mode ROMs. With ADV# signal tied low, addresses cannot latched into device. This means that addresses must stay valid throughout entire read write cycle, until either high. Figure "Asynchronous Page Mode Read Waveform" page shows asynchronous read timing diagram with ADV# held low. Note that address lines A1-0 toggled clock data.
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28F320D18
Figure Asynchronous Page Mode Block Diagram
Reset RST# Address A20-0 Volt Dual-Plane Flash Memory DQ15-0 ADV#
Burst
Data
Figure Asynchronous Page Mode Read Waveform
A1-0 DQ15-0 Valid Output Valid Output Valid Output Valid Output
A20-2
Valid Address Valid Address Valid Address Valid Address Valid Address
ADV#
7.3.4
Using Synchronous Burst Mode
Synchronous burst mode provides performance increase over asynchronous page-mode reads. supports effective zero wait-state performance MHz. This read mode only supported from main blocks, supported from other locations within device, such parameter blocks, device identification mode, Query information, Status Register. However, read operations from these locations while synchronous burst mode transpire single synchronous
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reads. Burst reads limited within partition, possible burst read across partition boundary. block diagram showing signal connections shown Figure This ideal interface, some glue logic required processor does provide these signals. Figure shows synchronous burst mode read timing diagram. Note that only address needed from processor generate four valid data outputs. Figure Synchronous Burst Read Interface Block Diagram
Reset RST# Address A20-0 ADV# Burst Data Volt Dual-Plane Flash Memory DQ15-0
Figure Synchronous Burst Mode Read Waveform
A20-0 Valid Address
Note
ADV# transition informs device latch address start burst cycle
ADV# DQ15-0 Valid Output Valid Output Valid Output Valid Output
Data held valid clock cycle NOTE: Clock cycles insterted based frequency configuration code: Frequency Configuration insert clock cycles. Frequency Configuration insert three clock cycles. Frequency Configuration insert four clock cycles.
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28F320D18
Different interface considerations need made when booting from Volt Dual-Plane Flash memory depending whether processor supports burst read operations boot-up.
Case processor does support burst read mode boot-up, rather boots
asynchronous page mode. This initial state flash memory, special design considerations need made. After booting processor can, possible, configure flash memory synchronous burst mode.
Case processor does support burst mode boot-up. After return from reset, flash
memory defaults asynchronous read mode, which inherently slower than synchronous burst mode. External interface logic will needed inform processor this, insert wait states match flash memory's timing with processor's timing. This logic only necessary until processor chance switch memory device synchronous burst mode, which time external logic must notified this change. This accomplished write-able register within system wait-state logic general purpose (GPIO) pin. GPIO operate input into system logic.
7.3.5
Signal Generation
Other than address data pins, Volt Dual-Plane Flash memory several control pins well. This section will cover these pins generate these signals.
ADV# derived from processor's transaction start signal. processor does
have this type signal, other standard control signals used control ADV#. characteristic this signal that must toggle inform device latch address. this signal used, asynchronous page mode only, then must toggle inform flash memory address.
derived from processor's memory clock output. processor does
supply this control signal memory subsystem, signal received from clock signal generator through clock buffer. This buffer minimizes clock load skew. clock signal must have period least Figure illustrates different clock options. Figure Different Clock Options
option does provide system output
Clock
Clock Buffer
INCLK MCLK
option provides system output
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28F320D18
WP#: Fast Boot Block other Intel Flash memory families, this only
locking unlocking lockable blocks. Volt Dual-Plane Flash memory, locking unlocking lockable blocks possible through both hardware software. Initially, upon reset, blocks locked cannot programmed erased regardless value WP#. order write erase block, must first unlocked. This done through software. unlocked block programmed erased regardless value WP#. Only when block marked "lock-down" does have effect memory. order program/erase locked-down block, must high, block must then unlocked. block then programmed erased long high. When goes low, block reverts lock-down longer programmed erased. only block lock-down mode reset device. used, should tied high. This will insure that blocks locked unlocked through software, even after setting lock-down bit. With tied low, blocks still locked unlocked through software, block locked down, will remain lock-down state, cannot programmed erased until flash memory reset.
OE#: Processors that have separate pins signal reads writes can, most cases,
connect directly these pins flash memory component. Processors that have single which determines read write this signal directly either OE#, depending what value means that pin. other input signal will then need generated external logic ensure that goes high right times.
RST# flash connected reset signal processor provided that time
from deserting reset processor's first memory request longer than time required flash. maximum delay from deasserting reset valid data Volt Dual-Plane Flash memory processor takes less time than that requires memory before flash component ready, data will invalid. processor takes longer than flash reset, there problem. this kept power-up will prevent possible spurious writes. ramps before drops before VPP, random noise data pins possibly enter program command (40H) with high. With RST# will prevent this spurious write.
Most processors will expect data during read cycles much sooner than flash memory
component provide this reason processor needs able pause wait flash memory. This done programming processor generate number wait states, possible. processor unable internally generate wait-states, input processor tells when pause wait valid data from flash memory. This then also used input from flash memory's WAIT# signal during continuous reads during 8-word reads non-wrap mode (RCR.3
7.3.6
Using WAIT# Burst Mode
Volt Dual-Plane Flash memory supports 4-word, 8-word, continuous burst lengths. continuous burst length, 4-word 8-word burst lengths with no-wrap (RCR.3 output pin, WAIT#, provided simplify memory communication. WAIT# informs system when data valid.
WAIT# Logic means Valid Data WAIT# Logic means Invalid Data
When operating continuous burst mode, during 8-word reads non-wrap mode (RCR.3 flash memory incur output delay when burst sequence crosses first 16-word boundary. starting address dictates whether delay will occur. starting address aligned four-word boundary, delay will seen. starting address four-word boundary, output delay will equal frequency configuration setting;
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28F320D18
this worst case delay. delay will only take place once during continuous burst access, burst sequence never crosses 16-word boundary, delay will never happen. When output delay encountered, WAIT# will asserted. This signal should into systems wait-state control logic directly CPU. WAIT# output gated CE#. either inactive, WAIT# output buffer turns off. internal pull-up resistor holds WAIT# logic state. resistor value approximately This output configuration allows multiple banks flash enable wire ORing, shown Figure "WAIT# Connection Using Multiple Flash Memory Components" page WAIT# also configured couple different characteristics help simplify system usage. configured assertion during delay data cycle before delay.
7.3.7
Write Operations
Write operations used switch memory device between modes, initiate program erase, lock unlock blocks, write memory device stored. Commands that switch modes device suspend/resume program erase take write cycle. Commands which initiate program erase lock/unlock blocks take write cycles. program command required before each data word programmed into flash device, even multiple data words programmed back back. Write operations transpire asynchronous operations, similar other Intel Flash memory families, such Advanced Advanced+ Boot Block Fast Boot Block memory. flash memory latches address during writes same during reads. data, Intel Flash memory components, latched rising edge WE#, whichever goes high first. write cycle, interchangeable. After completing program erase program/erase suspend command, flash device automatically goes into read status mode. reads flash this point will return status register data. This data updated output pins continually, rather and/or need toggled updated status register data. After Read Configuration Register command, flash device goes into read array mode.
7.4.1
Design Tools Software
Design Tools
Several tools available which will simplify designing Volt Dual-Plane Flash memory components into system. They include VHDL Verilog functional models, Timing Designer* files, IBIS files. Some these tools found Intel's website, otherwise they obtained contacting Intel field representative. Visit flash/swtools/ more details.
7.4.2
Flash Data Integrator (FDI)
Intel® Flash Data Integrator software code plus data storage manager real-time embedded applications. This software enables code execution data storage single flash device. handles parameter, data-stream, packet storage, well sophisticated file-system features like wear-leveling, power-loss recovery block reclaims. consolidating code data storage single flash device, reduces component count, allowing decreases board
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28F320D18
size, power consumption cost. designed fully support special features Volt Dual-Plane Flash memory. More information Flash Data Integrator (FDI) software available Intel's website
Electrical Specifications
Absolute Maximum Ratings
Parameter Temperature under Bias Storage Temperature Voltage (except VPP) Voltage VCCQ Voltage Output Short Circuit Current Maximum Rating -40°C +85°C -65°C +125°C -0.5 +2.45 V(1) -2.0 +14.0 V(1,2,4) -0.2V +2.45V mA(3)
NOTES: specified voltages with respect VSS. Minimum voltage -0.5 input/output pins -0.2 pins. During transitions, this level undershoot -2.0 periods Maximum voltage input/output pins +0.5 which, during transitions, overshoot +2.0 periods Maximum voltage overshoot +14.0 periods Output shorted more than second. more than output shorted time. Program voltage normally 1.65 V-1.95 Connection 11.4 V-12.6 supply done maximum 1000 cycles main blocks 2500 cycles parameter blocks during program/erase. connected total hours maximum.
NOTICE: This datasheet contains information products design phase development. finalize design with this information. Revised information will published when product becomes available. Verify with your local Intel Sales office that have latest datasheet before finalizing design.
Warning:
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability.
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28F320D18
Symbol VCCQ VPP1 VPP2
Extended Temperature Operation
Parameter Operating temperature supply voltage supply voltage supply voltage when used logic control supply voltage Main block erase cycling; Parameter block erase cycling; Notes 1.65 1.65 11.4 100,000 100,000 1000 2500 Nominal 1.95 1.95 1.95 12.6 Unit Cycles Cycles Cycles Cycles Hours
Cycling
Main block erase cycling; hrs. Parameter block erase cycling; hrs. Maximum hours
NOTES: Characteristics tables voltage range-specific specifications. Applying =11.4 12.6 during program erase done maximum 1000 cycles main blocks 2500 cycles parameter blocks. permanent connection 11.4 12.6 allowed cause damage device.
Capacitance
+25°C,
COUT Parameter(1) Input Capacitance Output Capacitance Unit Condition VOUT
NOTE: Sampled, 100% tested.
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28F320D18
Characteristics
Parameter(1) Input Load Current Output Leakage Current Note Unit Test Condition Max, VCCQ VCCQ Max, VCCQ VSSQ Max, VCCQ VCCQ Max, VCCQ VSSQ Max, RST# =VCCQ, VCCQ VSSQ, 0.2V Word Read CE#=VIL, OE#=VIH, Inputs
ICCS
Standby Current Average Read Current
ICCR
Page Mode Synchronous
VCCQ +0.4
Burst length Burst length Burst length Continuous Burst length Burst length Burst length Continuous
Synchronous
CE#=VIL, OE#=VIH, Inputs
ICCW IPPW ICCE+ IPPE ICCWS ICCES IPPS IPPR IPPWS IPPES
Program Current
VPP1, program progress VPP2, program progress VPP1, block erase progress VPP2, block erase progress VIH, program suspend progress VIH, block erase suspend progress VPP1/2, program suspended VPP1/2, erase suspended
Block Erase Current
Program Suspend Current Erase Suspend Current Standby Current Read Current Program Suspend Current Erase Suspend Current Input Voltage Input High Voltage
-0.4 VCCQ
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Characteristics, continued
Parameter(1) Output Voltage Note Unit Test Condition Min, VCCQ VCCQ Min, Output High Voltage VCCQ Min, VCCQ VCCQ Min, -100
VPPLK VLKO
Lock-Out Voltage Lock Voltage
NOTE: currents unless noted. Typical values typical VCC, +25°C. WAIT# max. Automatic Power Savings (APS) reduces ICCR approximately standby levels static operation. burst wrap (RCR.3) determines whether 8-word burst-accesses wrap within burst-length boundary whether they cross word-length boundaries perform linear accesses. no-wrap mode (RCR.3 device operates similar continuous linear burst mode consumes less power during 4and 8-word bursts. Sampled, 100% tested. read program current summation Read program currents. read program current summation Read block erase currents. ICCES specified with device deselected. device read while erase suspend, current draw ICCES ICCR. Erase program operations inhibited when VPPLK guaranteed outside valid VPP1 VPP2 ranges.
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28F320D18
Test Conditions
Figure Input/Output Reference Waveform
VCCQ Input
0672_21
VCCQ/2
Test Points
VCCQ/2
Output
NOTE: test inputs driven 1.65 Logic Logic "0." Input timing begins, output timing ends, VCCQ/2. Input rise fall times (10% 90%) Worst case speed conditions when 1.65
Figure Transient Equivalent Testing Load Circuit
VCCQ
Device Under Test
0672_22
NOTE: table component values. Test configuration component value worst case speed conditions Test Configuration Standard Test (pF) 16.7K 16.7K
NOTE: includes capacitance.
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28F320D18
Read Characteristics
Product -110 Notes -120 Unit Parameter()
Clock Specifications tCLK (tCL) tCHCL (tCLCH) period high (Low) time fall (Rise) time
Synchronous Specifications tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTL (tCHTH) tEHEL Address valid setup ADV# setup setup output delay Output hold from Address hold from WAIT# delay high between subsequent synchronous reads
Asynchronous Specifications tAVVH tELVH tAVQV tELQV tVLQV tVLVH tVHVL tVHAX tAPA tGLQV tPHQV tEHQZ tGHQZ Address setup ADV# high ADV# going high Address output delay output delay ADV# output delay ADV# pulse width ADV# pulse width high Address hold from ADV# high Page address access time output delay RST# high output delay high output high whichever occurs first Output hold from first occurring address, CE#, change
NOTES: input/output reference waveform timing measurements maximum allowable input slew rate. Tested worst case processor conditions. Sampled, 100% tested. Applies only subsequent synchronous reads. delayed tELQV-tGLQV after falling edge without impact tELQV.
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Figure Waveform Input
0672_23
Figure Waveform Single Asynchronous Read Operations from Parameter Blocks, Status Register, Identifier Codes
A20-0
Valid Address
ADV#
WAIT#
High Valid Output
15-0 [D/Q]
RST#
0672_24
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Figure Waveform Asynchronous Page-Mode Read Operations from Main Blocks
A20-2
Valid Address
Valid Address Valid Address Valid Address
A1-0
Valid Address
ADV#
WAIT#
Valid Output Valid Output Valid Output
Valid Output
DQ15-0 [D/Q]
High
RST#
0672_25
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Figure Waveform Single Synchronous Read Operations from Parameter Blocks, Status Register, Identifier Codes
Note
A20-0
Valid Address
ADV#
WAIT#
High Valid Output
15-0 [D/Q]
0672_26
NOTE: Depending upon frequency configuration code value read configuration register, insert clock cycles: Frequency Configuration insert clock cycles Frequency Configuration insert three clock cycles Frequency Configuration insert four clock cycles 4.10.2 further information about frequency configuration effect initial read.
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Figure Waveform Synchronous Burst Read Operations, Four-Word Burst Length from Main Blocks
Note
A20-0
Valid Address
ADV#
WAIT#
High Valid Output
Valid Output
Valid Output Valid Output
15-0 [D/Q]
0672_27
NOTE: Depending upon frequency configuration code value read configuration register, insert clock cycles: Frequency Configuration insert clock cycles Frequency Configuration insert three clock cycles Frequency Configuration insert four clock cycles 4.10.2 further information about frequency configuration effect initial read.
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Figure Waveform Continuous Burst Read Showing Output Delay with Data Output Configuration Clock
Note
A20-0 ADV#
WAIT#
Note
Valid Output Valid Output
DQ15-0 [D/Q]
Valid Output
Valid Output
0672_28
NOTES: This delay occurs only certain burst configurations. 4.10.4 further information about WAIT# behavior. WAIT# configuration allows assertion cycle before during output. 4.10.4 further information.
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28F320D18
Write Characteristics
tPHWL (tPHEL) tELWL (tWLEL) tWLWH tVLVH tDVWH (tDVEH) tAVWH (tAVEH) tVLWH (tVLEH) tAVVH tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tVHAX tWHWL (tWHWL) tBHWH (tBHEH) tVVWH (tQVEH) tWHGL (tEHGL) tQVBL tQVVL tWHQV Parameter(1,2) RST# High Recovery (CE#) Going (WE#) Setup (CE#) Going Write Pulse Width ADV# Pulse Width Data Setup (CE#) Going High Address Setup (CE#) Going High ADV# Setup (CE#) Going High Address Setup ADV# Going High (WE#) Hold from (CE#) High Data Hold from (CE#) High Address Hold from (CE#) High Address Hold from ADV# Going High Write Pulse Width High Setup (CE#) Going High Setup (CE#) Going High Write Recovery before Read Hold from Valid Hold from Valid high data valid Notes tAVQV Unit
NOTES: Read timing characteristics during block erase program operations same during read-only operations. write operation initiated terminated with either WE#. Sampled, 100% tested. Refer Table page valid block erase program. should held VPP1/2 until block erase program success determined. Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes last). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. tWHQV after Read Query, Device Identifier Protection Register command tAVQV
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28F320D18
Figure Waveform Write Operations
Note Note
Valid Address
Note
Valid Address
Note
Valid Address
Note
A20-0
ADV#
Note
Notes
Valid
DQ15-0 [D/Q] RST#
Data Data
VPPH1/2
VPPLK
0672_29
NOTES: power-up standby. Write block erase program setup. Write block erase confirm valid address data. Automated erase program delay. Read status register data. read operations, must driven active, de-asserted.
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28F320D18
Reset Operations
Figure Waveform Reset Operations
RST#
Reset while device read mode
RST#
Abort Complete
Reset during program block erase, Abort Complete
RST#
Reset during program block erase,
0672_30
Table Reset Specifications(1)
Symbol tPLPH tPLRH Parameter RST# reset during read RST# tied VCC, this specification applicable) RST# reset during block erase RST# reset during program Notes Unit
NOTES: These specifications valid product versions (packages speeds). tPLPH device still reset this guaranteed. RST# asserted while block erase word program operation executing, reset will complete within Sampled, 100% tested.
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28F320D18
Block Erase Program Performance
Symbol Parameter
VPP1 system)
VPP2 manufacturing)
Unit
Note tBWPB tBWMB tWHQV1 tEHQV1 tWHQV2 tEHQV2 tWHQV3 tEHQV3 tWHRH1 tEHRH1 tWHRH2 tEHRH2 4-KW Parameter Block Program Time 32-KW Main Block Program Time Word Program Time 4-KW Parameter BlockErase Time 32-KW Main Block Erase Time Program Suspend Latency Erase Suspend Latency
0.03 0.24
0.80
NOTES: Typical values measured nominal voltages. Excludes external system-level overhead. Sampled, 100% tested.
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28F320D18
Ordering Information
Access Speed (ns) (110,120)
Package Extended temp. 60-Ball matrix µBGA*
Parameter Blocking Bottom Parameter Blocking Product line designator Intel® Flash products Device Density (32-Mbit) Product Family 1.8V Dual-Plane Flash Memory 1.65 1.95 1.95 11.4 12.6
Valid Combinations (All Extended Temperature)
60-Ball matrix µBGA CSP(1) GT28F320D18B110 GT28F320D18B120
NOTE: 60-Ball (7x8 matrix
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