IND:-20 PALLV16V8-10 PALLV16V8Z-20 Voltage, Zero Power 20-Pi

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IND:-20 PALLV16V8-10 PALLV16V8Z-20 Voltage, Zero Power 20-Pi

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COM'L:-10
IND:-20
PALLV16V8-10 PALLV16V8Z-20
Voltage, Zero Power 20-Pin CMOS Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS
Low-voltage operation, JEDEC compatible
GENERAL DESCRIPTION
PALLV16V8 advanced device built with low-voltage, high-speed, electrically-erasable CMOS technology. functionally compatible with 20-pin devices. macrocells provide universal device architecture. PALLV16V8 will directly replace PAL16R8, with exception PAL16C1. PALLV16V8Z provides zero standby power high speed. 30-µA maximum standby current, PALLV16V8Z allows battery powered operation extended period. PALLV16V8 utilizes familiar sum-of-products (AND/OR) architecture that allows users implement complex logic functions easily efficiently. Multiple levels combinatorial logic always reduced sum-of-products form, taking advantage very wide input gates available devices. equations programmed into device through floating-gate cells logic array that erased electrically. fixed array allows eight data product terms output logic functions. these products feeds output macrocell. Each macrocell programmed registered combinatorial with active-high active-low output. output configuration determined global bits local controlling four multiplexers each macrocell.
Publication# 17713 Amendment/0
Rev: Issue Date: September 2000
+3.0 +3.6 function compatible with 20-pin PAL® devices Electrically-erasable CMOS technology provides reconfigurable logic full testability Direct plug-in replacement PAL16R8 series Designed interface with both 3.3-V logic Outputs programmable registered combinatorial combination Programmable output polarity Programmable enable/disable control Preloadable output registers testability Automatic register reset power Cost-effective 20-pin plastic DIP, PLCC, SOIC packages Extensive third-party software programmer support Fully tested 100% programming functional yields high reliability
BLOCK DIAGRAM
CLK/I0
Programmable Array
MACRO
MACRO
MACRO MACRO MACRO MACRO
MACRO MACRO
OE/I9
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
17713D-1
FUNCTIONAL DESCRIPTION
PALLV16V8 low-voltage, CMOS version PALCE16V8. PALLV16V8Z low-voltage, CMOS version PALCE16V8. addition, PALLV16V8Z zero standby power unused product term disable feature reduced power consumption. PALLV16V8 universal device. eight independently configurable macrocells (MC0-MC7). Each macrocell configured registered output, combinatorial output, combinatorial dedicated input. programming matrix implements programmable logic array, which drives fixed logic array. Buffers device inputs have complementary outputs provide user-programmable input signal polarity. Pins serve either array inputs clock (CLK) output enable (OE), respectively, flip-flops. Unused input pins should tied directly GND. Product terms with bits unprogrammed (disconnected) assume logical HIGH state product terms with both true complement input signal connected assume logical state. programmable functions PALLV16V8 automatically configured from user's design specification. design specification processed development software verify design create programming file. This file, once downloaded programmer, configures device according user's desired function.
PALLV16V8-10 PALLV16V8Z-20 Families
user given design options with PALLV16V8. First, programmed standard device from PAL16R8 PAL10H8 series. programmer manufacturer will supply device codes standard device architectures used with PALLV16V8. programmer will program PALLV16V8 corresponding architecture. This allows user existing standard device JEDEC files without making changes them. Alternatively, device programmed PALLV16V8. Here user must PALLV16V8 device code. This option allows full utilization macrocell.
Adjacent Macrocell
SL0X
I/OX
SL1X
SL0X
*SG1
From Adjacent
17713D-004
macrocells MC7, replaced feedback multiplexer.
Figure PALLV16V8 Macrocell
CONFIGURATION OPTIONS
Each macrocell configured following: registered output, combinatorial output, combinatorial I/O, dedicated input. registered output configuration, output buffer enabled pin. combinatorial configuration, buffer either controlled product term always enabled. dedicated input configuration, always disabled. With exception MC7, macrocell configured dedicated input derives input signal from adjacent I/O. derives input from (OE) from (CLK). macrocell configurations controlled configuration control word. contains global bits (SG0 SG1) local bits (SL00 through SL07 SL10 through SL17). determines whether registers will allowed. determines whether PALLV16V8 will emulate PAL16R8 family. Within each macrocell, SL0x, conjunction with SG1, selects configuration macrocell, SL1x sets output either active active high individual macrocell. configuration bits work acting control inputs multiplexers macrocell. There four multiplexers: product term input, enable select, output select, feedback select multiplexer. SL0x control signals four multiplexers. MC7,
PALLV16V8-10 PALLV16V8Z-20 Families
replaces feedback multiplexer. This accommodates being adjacent adjacent MC0. Registered Output Configuration control settings SL0x There only registered configuration. eight product terms available inputs gate. Data polarity determined SL1x. flip-flop loaded LOW-to-HIGH transition CLK. feedback path from register. output buffer enabled Combinatorial Configurations PALLV16V8 three combinatorial output configurations: dedicated output nonregistered device, non-registered device registered device. control settings SL0x eight product terms available gate. Although macrocell dedicated output, feedback used, with exception MC4. feedback this mode. Because used non-registered device, pins available input signals. will feedback path MC7, will feedback path MC0. Combinatorial Non-Registered Device control settings SL0x Only seven product terms available gate. eighth product term used enable output buffer. signal back array feedback multiplexer. This allows used input. Because used non-registered device, pins available inputs. will feedback path MC7, will feedback path MC0. Combinatorial Registered Device control settings SL0x Only seven product terms available gate. eighth product term used output enable. feedback signal corresponding signal. Dedicated Input Configuration control settings SL0x output buffer disabled. Except MC7, feedback signal adjacent I/O. MC7, feedback signals pins These configurations summarized Table illustrated Figure
PALLV16V8-10 PALLV16V8Z-20 Families
Dedicated Output Non-Registered Device
Table Macrocell Configuration
SL0X Cell Configuration Devices Emulated SL0X Cell Configuration Devices Emulated
Device Uses Registers Registered Output Combinatorial PAL16R8, 16R6, 16R4 PAL16R6, 16R4
Device Uses Registers Combinatorial Output Input Combinatorial PAL10H8, 12H6, 14H4, 16H2, 10L8, 12L6, 14L4, 16L2 PAL12H6, 14H4, 16H2, 12L6, 14L4, 16L2 PAL16L8
Programmable Output Polarity
polarity each macrocell active-high active-low, either match output signal needs reduce product terms. Programmable polarity allows Boolean expressions written their most compact form (true inverted), output still desired polarity. also save "DeMorganizing" efforts. Selection through programmable SL1x which controls exclusive-OR gate output AND/OR logic. output active high SL1x active SL1x
PALLV16V8-10 PALLV16V8Z-20 Families
Registered active
Registered active high
Combinatorial active
Note
Combinatorial active high
Note
Combinatorial output active
Combinatorial output active high
Notes: Feedback available pins combinatorial output mode. dedicated-input configuration available pins Dedicated input
Adjacent Note
17713D-5
Figure Macrocell Configurations
PALLV16V8-10 PALLV16V8Z-20 Families
Benefits Lower Operating Voltage PALLV16V8 operating voltage range 3.0V voltage allows lower operating power consumption, longer battery life, and/or smaller batteries notebook applications. PALLV16V8 inputs accept they safe mixed voltage design. Because power proportional square voltage, reduction supply voltage from significantly reduces power consumption. This directly translates longer battery life portable applications. Lower power consumption also used reduce size weight battery. Thus, 3.3-V designs facilitate reduction form factor. lower operating voltage results reduction voltage swings. This reduces noise generation provides less hostile environment board design. lower operating voltage also reduces electromagnetic radiation noise makes obtaining approval easier. Power-Up Reset flip-flops power logic predictable system initialization. Outputs PALLV16V8 will depend whether they selected registered combinatorial. registered selected, output will HIGH. combinatorial selected, output will function logic. Register Preload register PALLV16V8 preloaded from output pins facilitate functional testing complex state machine designs. This feature allows direct loading arbitrary states, making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery. preload function disabled security bit. This allows functional testing after security programmed. security provided PALLV16V8 deterrent unauthorized copying array configuration patterns. Once programmed, this defeats readback programmed pattern device programmer, securing proprietary designs from competitors. However, programming verification also defeated security bit. only erased conjunction with array during erase cycle. Electronic Signature Word electronic signature word provided PALLV16V8 device. consists bits programmable memory that contain user-defined data. signature data always available user independent security bit. Programming Erasing PALLV16V8 programmed standard logic programmers. also erased reset previously configured device back unprogrammed state. Erasure automatically performed programming hardware. special erase operation required.
Security
PALLV16V8-10 PALLV16V8Z-20 Families
Quality Testability PALLV16V8 offers very high level built-in quality. erasability device provides direct means verifying performance parameters. addition, this verifies complete programmability functionality device yield highest programming yields post-programming function yields industry. Technology high-speed PALLV16V8Z fabricated with Vantis' advanced electrically-erasable (EE) CMOS process. array connections formed with proven cells. This technology provides strong input-clamp diodes grounded substrate clean switching. PALLV16V8 features zero-standby power mode. When none inputs switch extended period (typically ns), PALLV16V8Z will into standby mode, shutting down most internal circuitry. current will almost zero (ICC µA). outputs will maintain states held before device went into standby mode. There speed penalty associated with coming standby mode. When input switches, internal circuitry fully enabled, power consumption returns normal. This feature results considerable power savings operation medium frequencies. This saving illustrated frequency graph. PALLV16V8Z-20 free-running-clock feature. This means that more registers used, switching only will wake logic array macrocell. device will standby mode because buffer will draw some current, dynamic will typically less than Product-Term Disable programmed PALLV16V8Z, product terms that used disabled. Power from these product terms that they draw current. shown frequency graph, product-term disabling results considerable power savings. This saving greater higher frequencies. Further hints minimizing power consumption found separate document entitled, Minimizing Power Consumption with Zero-Power PLDs.
PALLV16V8-10 PALLV16V8Z-20 Families
Zero-Standby Power Mode
LOGIC DIAGRAM
CLK/I
I/O7
I/O6
SL16
I/O5
I/O4
17713D-17
PALLV16V8-10 PALLV16V8Z-20 Families
LOGIC DIAGRAM (CONTINUED)
I/O1
SL00
OE/I
17713D-18
PALLV16V8-10 PALLV16V8Z-20 Families
ABSOLUTE MAXIMUM RATINGS
Storage Temperature .-65°C +150°C Ambient Temperature with Power Applied .-55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latch-up Current 75°C)
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +3.0 +3.6
Operating ranges define those limits between which functionality device guaranteed.
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter Symbol Parameter Description Output HIGH Voltage Test Conditions -100 -100 -130 Unit
IOZH IOZL
Output Voltage Input HIGH Voltage Input Voltage
Input HIGH Leakage Current Input Leakage Current
Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current
Notes: These absolute values with respect device ground, overshoots system tester noise included. leakage worst case IOZL IOZL). more than output should shortened time, duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter guaranteed worst case under test conditions. Refer frequency graph typical measurements.
VCC, (Note (Note VOUT VCC, Max, (Note VOUT VCC, Max, (Note VOUT (Note
Guaranteed Input Logical HIGH Voltage Inputs (Note
Guaranteed Input Logical Voltage Inputs (Note
Outputs Open (IOUT mA), Max, (Note
PALLV16V8-10 (Com'l)
CAPACITANCE
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance VOUT Test Condition 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter Symbol
Parameter Description
Unit
Input Feedback Combinatorial Output (Note Setup Time from Input Feedback Clock Hold Time Clock Output Clock Width
71.4 83.3 83.3
HIGH
External Feedback
1/(tS tCO) 1/(tS tCF)
fMAX
Maximum Frequency (Notes Output Enable
Internal Feedback (fCNT Feedback
1/(tS
tPZX tPXZ
Output Disable
Notes: "Switching Test Circuit" test conditions. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
Input Output Enable Using Product Term Control
Input Output Disable Using Product Term Control
PALLV16V8-10 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature .-65°C +150°C Ambient Temperature with Power Applied .-55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latch-up Current -40°C 85°C)
OPERATING RANGES
Industrial Devices Ambient Temperature (TA) -40°C +85°C Supply Voltage (VCC) with Respect Ground. +3.0 +3.6
Operating ranges define those limits between which functionality device guaranteed.
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Parameter Symbol Parameter Description Output HIGH Voltage Test Conditions Unit
IOZH IOZL
Output Voltage Input HIGH Voltage Input Voltage
Input HIGH Leakage Current Input Leakage Current
Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current
Note: These absolute values with respect device ground, overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time, duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter guaranteed worst case under test conditions. Refer frequency graph typical measurements.
VCC, (Note (Note VOUT VCC, Max, (Note VOUT VCC, Max, (Note VOUT (Note Outputs Open (IOUT Max, (Note
Guaranteed Input Logical HIGH Voltage Inputs (Note
Guaranteed Input Logical Voltage Inputs (Note
PALLV16V8Z-20 (Ind)
CAPACITANCE
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance VOUT Test Condition 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Parameter Symbol
Parameter Description
Unit
Input Feedback Combinatorial Output (Note Setup Time from Input Feedback Clock Hold Time Clock Output Clock Width
66.7
HIGH
External Feedback
1/(tS tCO) 1/(tS tCF)
fMAX
Maximum Frequency (Notes Output Enable
Internal Feedback (fCNT) Feedback
1/(tS
tPZX tPXZ
Output Disable
Input Output Enable Using Product Term Control
Input Output Disable Using Product Term Control
Notes: "Switching Test Circuit" test conditions. This parameter tested Standby Mode. When device Standby Mode, will typically about faster. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALLV16V8Z-20 (Ind)
SWITCHING WAVEFORMS
Input Feedback Input Feedback Combinatorial Output
17713D-7
17713D-8
Clock Registered Output
Input
Combinatorial output
Registered output
0.5V 0.5V
17713D-10
Clock
Output
17713D-9
Clock width
Input output disable/enable
tPXZ
tPZX
Output
0.5V 0.5V
17713D-11
output disable/enable
Notes: input signals VCC/2 output signals. Input pulse amplitude Input rise fall times typical.
PALLV16V8-10 PALLV16V8Z-20 Families
SWITCHING WAVEFORM
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown
Does Apply Output Test Point
Center Line HighImpedance "Off" State
KS000010-PAL 17713D-12
SWITCHING TEST CIRCUIT
Specification tPD, tPZX, tPXZ,
Closed Open Closed Open Closed
Closed Closed Open Closed Open
Measured Output Value VCC/2
1.6K
1.6K
VCC/2
PALLV16V8-10 PALLV16V8Z-20 Families
TYPICAL CHARACTERISTICS 25°C
PALLV16V8-10 PALLV16V8Z-20
17713D-13
(mA)
Frequency (MHz)
Frequency
selected "typical" pattern utilized device resources. Half macrocells were programmed registered, other half were programmed combinatorial. Half available product terms were used each macrocell. vector, half outputs were switching. utilizing device, midpoint defined ICC. From this midpoint, designer scale graphs down estimate requirements particular design.
PALLV16V8-10 PALLV16V8Z-20 Families
ENDURANCE CHARACTERISTICS
PALLV16V8 manufactured using Vantis' advanced electrically-erasable (EE) CMOS process. This technology uses cell replace fuse link used bipolar parts. result, devices erased reprogrammed-a feature which allows 100% testing factory.
Symbol Parameter Pattern Data Retention Time Operating Temperature Reprogramming Cycles Normal Programming Conditions Years Cycles Test Conditions Storage Temperature Value Unit Years
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Protection Clamping
Programming Pins only
Programming Voltage Detection
PALLV16V8 some unique features that make extremely robust, especially when operating high-speed design environments. Pull-up resistors inputs pins cause unconnected pins default known state. Input clamping circuitry limits negative overshoot, eliminating possibility false clocking caused subsequent ringing. special noise filter makes programming circuitry completely insensitive positive overshoot that pulse width less than about
ROBUSTNESS FEATURES
Positive Overshoot Filter
Programming Circuitry
Typical Input
17713D-14
Protection
Provides Protection Clamping Preload Circuitry Feedback Input
17713D-15
Typical Output PALLV16V8-10 PALLV16V8Z-20 Families
POWER-UP RESET
PALLV16V8 been designed with capability reset during system power-up. Following power-up, flip-flops will reset LOW. output state will HIGH independent logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset wide range ways rise steady state, conditions required ensure valid power-up reset. These conditions are:
rise must monotonic.
Parameter Symbol
Parameter Descriptions
Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
1000 Unit
Power-Up Reset Time
Input Feedback Setup Time Clock Width
Switching Characteristics
Power
Registered Output
Clock
17713D-16
Figure Power-Up Reset Waveform
PALLV16V8-10 PALLV16V8Z-20 Families
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient lfpm PDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Parameter Symbol
lfpm lfpm
Plastic Considerations
data listed plastic reference only recommended calculating junction temperatures. heatflow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant temperature. Therefore, measurements only used similar environment.
PALLV16V8-10 PALLV16V8Z-20 Families
lfpm Thermal impedance, junction ambient with flow
CONNECTION DIAGRAMS (TOP VIEW)
DIP/SOIC
CLK/I
PLCC
CLK/I0
I/O6 I/O5 I/O4 I/O3 I/O2
OE/I9 I/O0 I/O1
I/O7
OE/I
17713D-2
DESIGNATIONS
Clock Ground Input Input/Output Connect Supply Voltage
17713D-3
Note: marked orientation.
PALLV16V8-10 PALLV16V8Z-20 Families
ORDERING INFORMATION
Commercial Industrial Products
Vantis programmable logic products industrial applications available with several ordering options. order number (Valid Combination) formed combination
NUMBER ARRAY INPUTS OUTPUT TYPE Versatile NUMBER OUTPUTS Zero Power Standby)
SPEED
PALLV16V8-10
PALLV16V8Z-20
Valid Combinations
PALLV16V8-10 PALLV16V8Z-20 Families
FAMILY TYPE Programmable Array Logic TECHNOLOGY Low-Voltage
OPERATING CONDITIONS Commercial (0°C +75°C) Industrial (-40°C 85°C)
PACKAGE TYPE 20-Pin Plastic 020) 20-Pin Plastic Leaded Chip Carrier 020) 20-Pin Plastic Gull-Wing Small Outline Package 020)
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local Vantis sales office confirm availability specific valid combinations check newly released

IND:-20 PALLV16V8-10 PALLV16V8Z-20 Voltage, Zero Power 20-Pi

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