MACH435-12/15/20, Q-20/25 High-Density CMOS Programmable Logic

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MACH435-12/15/20, Q-20/25 High-Density CMOS Programmable Logic

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COM'L: -12/15/20, Q-20/25
MACH435-12/15/20, Q-20/25
High-Density CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
Pins PLCC Macrocells 83.3 fCNT Inputs with pull-up resistors Outputs Flip-flops Macrocell flip-flops Input flip-flops product terms function, with
Lattice Semiconductor
Flexible clocking Four global clock pins with selectable edges Asynchronous mode available each macrocell "PAL33V16" blocks Input output switch matrices high routability Fixed, predictable, deterministic delays compatible with MACH130, MACH131, MACH230, MACH231
GENERAL DESCRIPTION
MACH435 member high-performance CMOS MACH family. This device approximately twelve times macrocell capability popular PAL22V10, with significant density functional features that PAL22V10 does provide. MACH435 consists eight blocks interconnected programmable central switch matrix. central switch matrix connects blocks each other input pins, providing high degree connectivity between fully-connected blocks. This allows designs placed routed efficiently. Routability further enhanced input switch matrix output switch matrix. input switch matrix provides input signals with alternative paths into central switch matrix; output switch matrix provides flexibility assigning macrocells pins. MACH435 macrocells that configured synchronous asynchronous. This allows designers implement both synchronous asynchronous logic together same device. types design mixed proportion, since selection each macrocell affects only that macrocell. product terms function assigned. possible allocate some product terms away from macrocell without losing that macrocell logic generation. MACH435 macrocell provides either registered combinatorial outputs with programmable polarity. registered configuration chosen, register configured D-type, T-type, J-K, help reduce number product terms used. flip-flop also configured latch. register type decision made designer software. macrocells connected cell through output switch matrix. output switch matrix makes possible make significant design changes while minimizing risk pinout changes.
Publication# 17469 Rev. Issue Date: 1995
Amendment
I/O0-I/O7 I/O8-I/O15 I/O16-I/O23 I/O24-I/031 Cells Macrocells Output Switch Matrix Cells Macrocells Macrocells Output Switch Matrix Output Switch Matrix Output Switch Matrix Macrocells Input Switch Matrix Input Switch Matrix Input Switch Matrix Logic Array Logic Allocator Logic Array Logic Allocator Cells Cells Clock Generator Clock Generator Clock Generator Input Switch Matrix Logic Array Logic Allocator
BLOCK DIAGRAM
Clock Generator
Logic Array Logic Allocator
Central Switch Matrix
CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4
MACH435-12/15/20, Q-20/25
Input Switch Matrix Input Switch Matrix Input Switch Matrix Logic Array Logic Allocator Macrocells Output Switch Matrix Cells Cells Output Switch Matrix Logic Array Logic Allocator Macrocells Output Switch Matrix Cells Macrocells Clock Generator Clock Generator I/O48-I/O55 I/O40-I/O47
Input Switch Matrix
Logic Array Logic Allocator
Logic Array Logic Allocator Macrocells
Clock Generator
Clock Generator
Output Switch Matrix Cells
17469E-1
I/O56-I/O63
I/O32-I/O39
CONNECTION DIAGRAM View PLCC
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I4 CLK2/I3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39
I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I0 CLK1/I1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23
I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
17469E-2
Note: Pin-compatible with MACH130, MACH131, MACH230, MACH231
DESIGNATIONS
CLK/I Clock Input Ground Input Input/Output Supply Voltage
MACH435-12/15/20, Q-20/25
ORDERING INFORMATION Commercial Products
Programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed DEVICE NUMBER Generation, Macrocells, Pins 435Q Generation, Macrocells, Pins, Quarter Power SPEED
OPTIONAL PROCESSING Blank Standard Processing
OPERATING CONDITIONS Commercial (0°C +70°C) PACKAGE TYPE 84-Pin Plastic Leaded Chip Carrier 084)
Valid Combinations MACH435-12 MACH435-15 MACH435-20 MACH435Q-20 MACH435Q-25
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult your local sales office confirm availability specific valid combinations check newly released combinations.
MACH435-12/15/20, Q-20/25
FUNCTIONAL DESCRIPTION
MACH435 consists eight blocks connected central switch matrix. There pins dedicated input pins feeding central switch matrix. These signals distributed eight blocks efficient design implementation. There global clock pins that also used dedicated inputs. inputs pins have built-in pull-up resistors. While always good design practice unused pins high, pull-up resistors provide design security stability event that unused pins left disconnected.
Product-Term Array
MACH435 product-term array consists product terms logic use, eight product terms output enable use, product terms global block initialization. Each macrocell nominal allocation product terms logic, although logic allocator allows logic redistribution. Each individual output enable term. initialization product terms provide asynchronous reset preset synchronous-mode macrocells block.
Logic Allocator
logic allocator MACH435 takes logic product terms allocates them macrocells needed. Each macrocell driven product terms synchronous mode, product terms asynchronous mode. When product terms routed away from macrocell, possible route product terms away, which precludes macrocell logic generation; possible route only product terms away, leaving simple function generation. design software automatically configures logic allocator when fitting design into device. logic allocator also provides exclusive-OR gate. This gate allows generation combinatorial exclusiveOR logic, such comparison addition. allows registered exclusive-OR functions, such generation, implemented more efficiently. also makes possible emulate flip-flop types with D-type flip-flop. Register type emulation automatically handled design software. Table illustrates which product term clusters available each macrocell within block. Refer Figure cluster macrocell numbers.
Blocks
Each block MACH435 (Figure contains clock generator, 90-product-term logic array, logic allocator, macrocells, output switch matrix, cells, input switch matrix. central switch matrix feeds each block with inputs. This makes block look effectively like independent "PAL33V16" with buried macrocells. addition logic product terms, individual output enable product terms block initialization product term provided. Each individually enabled. flip-flops that synchronous mode within block initialized together either block initialization product terms.
Central Switch Matrix Input Switch Matrix
MACH435 central switch matrix input switch matrices each block. Each block provides internal feedback signals, registered input signals, signals input switch matrix. these signals, decoded signals provided central switch matrix input switch matrix. central switch matrix distributes these signals back blocks very efficient manner that provides high performance. design software automatically configures input central switch matrices when fitting design into device.
Clock Generator
Each block clock generator that generate four clock signals throughout block. These four signals available macrocells cells block, whether synchronous asynchronous mode. clock generator chooses four signals from eight possible signals given true complement versions four global clock signals.
MACH435-12/15/20, Q-20/25
Table Logic Allocation
Macrocell Available Clusters C10, C10, C11, C10, C11, C12, C11, C12, C13, C12, C13, C14, C13, C14, C14,
macrocells configured registered, latched, combinatorial. combination with logic allocator, registered configuration standard flip-flop types. macrocell provides internal feedback whether configured with without flipflop, whether macrocell drives cell. flip-flop clock depends mode selected macrocell. synchronous mode, block clocks generated Clock Generator used. asynchronous mode, additional choice either edge individual product-term clock available. Initialization handled part bank macrocells block initialization terms synchronous mode, individually asynchronous mode. synchronous mode, block product terms available each preset reset. swap function determines which product term drives which function. This allows initialization polarity compatibility with MACH series. asynchronous mode, product term used either drive reset preset.
Macrocell Output Switch Matrix
MACH435 macrocells, half which drive pins; this selection made output switch matrix. Each macrocell drive four cells. allowed combinations shown Table Please refer Figure macrocell numbers. Table Output Switch Matrix Combinations
Macrocell M10, M12, M14, I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Routable Pins I/O5, I/O6, I/O7, I/O0 I/O6, I/O7, I/O0, I/O1 I/O7, I/O0, I/O1, I/O2 I/O0, I/O1, I/O2, I/O3 I/O1, I/O2, I/O3, I/O4 I/O2, I/O3, I/O4, I/O5 I/O3, I/O4, I/O5, I/O6 I/O4, I/O5, I/O6, I/O7 Available Macrocells M10, M10, M11, M12, M10, M11, M12, M13, M14, M10, M11, M12, M13, M14, M15, M12, M13, M14, M15, M14, M15,
Cell
cell MACH435 consists three-state buffer input flip-flop. cell driven macrocells, selected output switch matrix. Each cell take input from eight macrocells. three-state buffer controlled individual product term. input flip-flop configured register latch. Both direct signal registered/latched signal available input switch matrix, used simultaneously desired.
MACH435-12/15/20, Q-20/25
CLK0/I0 CLK1/I1
Clock Generator
CLK2/I3 CLK3/I4
Macrocell
Cell
I/O0
Macrocell
Macrocell
Cell
I/O1
Macrocell
Macrocell
Cell
I/O2
Macrocell
Macrocell
Cell
I/O3
Central Switch Matrix
Macrocell
Macrocell
Output Switch Matrix
Logic Allocator
Cell
I/O4
Macrocell
Macrocell
Cell
I/O5
Macrocell
Macrocell
Cell
I/O6
Macrocell
Macrocell
Cell
I/O7
Macrocell
Input Switch Matrix
17469E-3
Figure MACH435 Block
MACH435-12/15/20, Q-20/25
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 +0.5 Output Voltage -0.5 +0.5 Static Discharge Voltage 2001 Latchup Current +70°C)
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed. Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Typical) Test Conditions -3.2 (Note Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT MHz, 25°C (Note -100 -100 -160 Unit
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Notes: Total block should exceed These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 16-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled, reset. These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
MACH435-12 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output Setup Time from Input, I/O, Feedback Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock Output Product Term, Clock Width HIGH External Feedback fMAXA Maximum Frequency Using Product Term Clock (Note Internal Feedback (fCNTA) Feedback (Note tCOS tWLS tWHS External Feedback fMAXS Maximum Frequency Using Global Clock (Note Setup Time from Input, I/O, Feedback Global Clock Register Data Hold Time Using Global Clock Global Clock Output Global Clock Width HIGH D-type T-type D-type Internal Feedback (fCNTA) Feedback (Note tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS tPDL tSIR tHIR tICO Setup Time from Input, I/O, Feedback Product Term Clock Latch Data Hold Time Using Product Term Clock Product Term Gate Output Product Term Gate Width (for transparent) HIGH (for HIGH transparent) Setup Time from Input, I/O, Feedback Global Gate Latch Data Hold Time Using Global Gate Gate Output Global Gate Width (for transparent) HIGH (for HIGH transparent) Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output T-type D-type T-type D-type T-type D-type T-type D-type T-type 52.6 58.8 55.6 62.5 66.7 62.5 83.3 76.9 83.3 Unit
tCOA tWLA tWHA
MACH435-12 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol tICS tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Product Term Output Latch Gate Input Latch Gate Output Latch Setup Using Product Term Output Latch Gate Setup Time from Input, I/O, Feedback Through Transparent Input Latch Global Output Latch Gate Input Latch Gate Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable Input, I/O, Feedback Output Disable Parameter Description Input Register Clock Output Register Setup D-type T-type HIGH 83.3 Unit
tSLLA tIGSA tSLLS tIGSS tWIGL tPDLL tARW tARR tAPW tAPR
Notes: Switching Test Circuit this Data Book test conditions. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. This parameter does apply flip-flops emulated mode since feedback path required emulation.
MACH435-12 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 +0.5 Output Voltage -0.5 +0.5 Static Discharge Voltage 2001 Latchup Current +70°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 (Note Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT mA), MHz, 25°C (Note -100 -100 -160 Unit
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Notes: Total block should exceed These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 16-bit up/down counter pattern. This pattern programmed each Block capable being loaded, enabled, reset. actual value calculated using "Typical Dynamic ICCCharacteristics" Chart towards this data sheet. These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
MACH435-15/20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock Output (Note Product Term, Clock Width HIGH D-type External Feedback 1/(tSA tCOA) fMAXA Maximum Frequency Using Product Term Clock (Note T-type Internal Feedback (fCNTA) Feedback (Note 1/(tWLA tWHA) D-type T-type D-type T-type 47.6 45.4 55.6 Global Clock Width tWHS External Feedback 1/(tSS tCOS) fMAXS Maximum Frequency Using Global Clock (Note HIGH D-type T-type D-type Internal Feedback (fCNTS) Feedback (Note tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS tPDL tSIR tHIR tICO 1/(tWLS tWHS) T-type 47.6 66.6 62.5 83.3 38.5 47.6 62.5 30.3 35.7 41.7 D-type T-type 38.5 31.2 Unit
tCOA tWLA tWHA
Setup Time from Input, I/O, Feedback Global Clock Register Data Hold Time Using Global Clock Global Clock Output (Note
tCOS tWLS
Setup Time from Input, I/O, Feedback Product Term Clock Latch Data Hold Time Using Product Term Clock Product Term Gate Output (Note Product Term Gate Width (for transparent) HIGH (for HIGH transparent) Setup Time from Input, I/O, Feedback Global Gate Latch Data Hold Time Using Global Gate Gate Output (Note Global Gate Width (for transparent) HIGH (for HIGH transparent) Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output
MACH435-15/20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol Parameter Description tICS Input Register Clock Output Register Setup D-type T-type tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Product Term Output Latch Gate Input Latch Gate Output Latch Setup Using Product Term Output Latch Gate Setup Time from Input, I/O, Feedback Through Transparent Input Latch Global Output Latch Gate Input Latch Gate Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note Input Register Clock Width HIGH 1/(tWICL tWICH) 83.3 62.5 Unit
tSLLA tIGSA tSLLS tIGSS tWIGL tPDLL tARW tARR tAPW tAPR
Notes: Switching Test Circuit this Data Book test conditions. Parameters measured with outputs switching. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. This parameter does apply flip-flops emulated mode since feedback path required emulation.
MACH435-15/20 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 +0.5 Output Voltage -0.5 +0.5 Static Discharge Voltage 2001 Latchup Current +70°C)
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed. Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Typical) Test Conditions -3.2 (Note Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT MHz, 25°C (Note -100 -100 -160 Unit
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Notes: Total block should exceed These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 16-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled, reset. These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
MACH435Q-20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output Setup Time from Input, I/O, Feedback Product Term Clock tCOA tWLA tWHA Register Data Hold Time Using Product Term Clock Product Term Clock Output Product Term, Clock Width HIGH D-type External Feedback fMAXA Maximum Frequency Using Product Term Clock (Note Internal Feedback (fCNTA) Feedback (Note tCOS tWLS tWHS Setup Time from Input, I/O, Feedback Global Clock Register Data Hold Time Using Global Clock Global Clock Output Global Clock Width HIGH D-type External Feedback fMAXS Maximum Frequency Using Global Clock (Note T-type D-type Internal Feedback (fCNTA) Feedback (Note tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS tPDL tSIR tHIR tICO Setup Time from Input, I/O, Feedback Product Term Clock Latch Data Hold Time Using Product Term Clock Product Term Gate Output Product Term Gate Width (for transparent) HIGH (for HIGH transparent) Setup Time from Input, I/O, Feedback Global Gate Latch Data Hold Time Using Global Gate Gate Output Global Gate Width (for transparent) HIGH (for HIGH transparent) Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output T-type D-type T-type T-type D-type T-type D-type T-type 33.3 37.2 35.7 34.5 41.7 40.0 38.5 47.6 43.5 62.5 Unit
MACH435Q-20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol tICS tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Product Term Output Latch Gate Input Latch Gate Output Latch Setup Using Product Term Output Latch Gate Setup Time from Input, I/O, Feedback Through Transparent Input Latch Global Output Latch Gate Input Latch Gate Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width HIGH Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable Input, I/O, Feedback Output Disable Parameter Description Input Register Clock Output Register Setup D-type T-type HIGH 62.5 Unit
tSLLA tIGSA tSLLS tIGSS tWIGL tPDLL tARW tARR tAPW tAPR
Notes: Switching Test Circuit this Data Book test conditions. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. This parameter does apply flip-flops emulated mode since feedback path required emulation.
MACH435Q-20 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 +0.5 Output Voltage -0.5 +0.5 Static Discharge Voltage 2001 Latchup Current +70°C)
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed. Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 (Note Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT mA), f=25 MHz, 25°C, (Note -100 -100 -160 Unit
IOZH IOZL
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Notes: Total block should exceed These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 16-bit up/down counter pattern. This pattern programmed each Block capable being loaded, erased, reset. actual value calculated using "Typical Dynamic Characteristics" Chart towards this data sheet. These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
MACH435Q-25 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock Output (Note Product Term, Clock Width HIGH External Feedback fMAXA Maximum Frequency Using Product Term Clock (Note 1/(tSA tCOA) D-type T-type Internal Feedback (fCNTA) Feedback (Note 1/(tWLA tWHA) D-type T-type D-type T-type D-type T-type 21.7 21.3 24.4 23.8 26.3 HIGH D-type External Feedback fMAXS Maximum Frequency Using Global Clock (Note 1/(tSS tCOS) T-type D-type Internal Feedback (fCNTS) T-type Feedback (Note tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS tPDL tSIR tHIR tICO 1/(tSS tHS) 35.7 31.3 30.3 Unit
tCOA tWLA tWHA
Setup Time from Input, I/O, Feedback Global Clock Register Data Hold Time Using Global Clock Global Clock Output (Note Global Clock Width
tCOS tWLS tWHS
Setup Time from Input, I/O, Feedback Product Term Clock Latch Data Hold Time Using Product Term Clock Product Term Gate Output (Note Product Term Gate Width (for transparent) HIGH (for HIGH transparent) Setup Time from Input, I/O, Feedback Global Gate Latch Data Hold Time Using Global Gate Gate Output (Note Global Gate Width (for transparent) HIGH (for HIGH transparent) Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output
MACH435Q-25 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol Parameter Description tICS Input Register Clock Output Register Setup D-type T-type tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Product Term Output Latch Gate Input Latch Gate Output Latch Setup Using Product Term Output Latch Gate Setup Time from Input, I/O, Feedback Through Transparent Input Latch Global Output Latch Gate Input Latch Gate Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width HIGH Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note 1/(tWICL tWICH) Input Register Clock Width HIGH 62.5 Unit
tSLLA tIGSA tSLLS tIGSS tWIGL tPDLL tARW tARR tAPW tAPR
Notes: Switching Test Circuit this Data Book test conditions. Parameters measured with outputs switching. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. This parameter does apply flip-flops emulated mode since feedback path required emulation.
MACH435Q-25 (Com'l)
TYPICAL CURRENT VOLTAGE (I-V) CHARACTERISTICS
25°C
(mA) -1.0 -0.8 -0.6 -0.4 -0.2
17469E-4
Output,
(mA) -100 -125 -150
17469E-5
Output, HIGH (mA)
-100
17469E-6
Input
MACH435-12/15/20, Q-20/25
TYPICAL CHARACTERISTICS 25°C
(mA)
17469E-7
MACH435
MACH435Q
Frequency (MHz)
selected "typical" pattern 16-bit up/down counter. This pattern programmed each block capable being loaded, enabled, reset. Maximum frequency shown uses internal feedback D-type register.
MACH435-12/15/20, Q-20/25
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
MACH435-12/15/20, Q-20/25
SWITCHING WAVEFORMS
Input, I/O, Feedback
Combinatorial Output
17469E-8
Combinatorial Output
Input, I/O, Feedback Clock Registered Output
Input, I/O, Feedback Gate tPDL
17469E-9
17469E-10
Latched
Registered Output
Latched Output (MACH
Clock
17469E-11
Gate tGWS
17469E-12
Clock Width
Gate Width (MACH
Registered Input tSIR Input Register Clock Combinatorial Output tICO
tHIR
Registered Input Input Register Clock Output Register Clock
tICS
17469E-14
17469E-13
Registered Input (MACH
Input Register Output Register Setup (MACH
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH435-12/15/20, Q-20/25
SWITCHING WAVEFORMS
Latched tSIL Gate
tHIL tIGO
Combinatorial Output
17469E-15
Latched Input (MACH
tPDLL Latched Latched Input Latch Gate tIGOL
tIGS Output Latch Gate
tSLL
17469E-16
Latched Input Output (MACH
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH435-12/15/20, Q-20/25
SWITCHING WAVEFORMS
tWICH Clock tWICL
17469E-17
Input Latch Gate tWIGL
17469E-18
Input Register Clock Width (MACH
Input Latch Gate Width (MACH
tARW Input, I/O, Feedback Registered Output tARR Clock
17469E-19
tAPW Input, I/O, Feedback Registered Output tAPR Clock
17469E-20
Asynchronous Reset
Asynchronous Preset
Input, I/O, Feedback Outputs 0.5V 0.5V
17469E-21
Output Disable/Enable
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH435-12/15/20, Q-20/25
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
17469E-22
Commercial Specification tPD, Closed Open Closed Open Closed
Measured Output Value
*Switching several outputs simultaneously should avoided accurate measurement.
MACH435-12/15/20, Q-20/25
ENDURANCE CHARACTERISTICS
MACH families manufactured using advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar parts. result, device erased reprogrammed, feature which allows 100% testing factory.
Endurance Characteristics
Parameter Symbol Parameter Description Pattern Data Retention Time Reprogramming Cycles Units Years Years Cycles Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions
MACH435-12/15/20, Q-20/25
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Protection
Input
Preload Circuitry
Feedback Input
17469E-24
MACH435-12/15/20, Q-20/25
POWER-UP RESET
MACH devices have been designed with capability reset during system power-up. Following powerup, flip-flops will reset LOW. output state will depend logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset
Parameter Symbol
wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
Parameter Descriptions Power-Up Reset Time Input Feedback Setup Time Clock Width
Switching Characteristics
Unit
Power
Registered Output
Clock
17469E-25
Power-Up Reset Waveform
MACH435-12/15/20, Q-20/25
USING PRELOAD OBSERVABILITY
order testable, circuit must both controllable observable. achieve this, MACH devices incorporate register preload observability. preload mode, each flip-flop MACH device loaded from pins, order perform functional testing complex state machines. Register preload makes possible series tests from known starting state, load illegal states test proper recovery. This ability control MACH device's internal state shorten test sequences, since easier reach state interest. observability function makes possible internal state buried registers during test overriding each register's output enable activating output buffer. values stored output buried registers then observed pins. Without this feature, thorough functional test would impossible designs with buried registers. While implementation testability features fairly straightforward, care must taken certain instances insure valid testing. case involves asynchronous reset preset. MACH registers drive asynchronous reset preset lines preloaded such that reset preset asserted, reset preset remove preloaded data. This illustrated Figure Care should taken when planning functional tests, that states that will cause unexpected resets presets preloaded. Another case aware arises testing combinatorial logic. When output configured combinatorial, observability feature forces output into registered mode. When this happens, product terms forced zero, which eliminates combinatorial data. straight combinatorial output, correct value will restored after preload observe function, there will problem. function implements combinatorial latch, however, relies feedback hold correct value, shown Figure this value change during preload observe operation, cannot count data being correct after operation. insure valid testing these cases, outputs that combinatorial latches should tested immediately following preload observe sequence, should first restored known state. MACH devices support both preload observability. Contact individual programming vendors order verify programmer support.
Reset Figure Combinatorial Latch
17469E-27
Preloaded HIGH
Preloaded HIGH
Preload Mode
Figure Preload/Reset Conflict
17469E-26
MACH435-12/15/20, Q-20/25

MACH435-12/15/20, Q-20/25 High-Density CMOS Programmable Logic

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