In-System Programmable High Density Features HIGH-DENSITY PROGRAM
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ispLSI 3320
In-System Programmable High Density Features
HIGH-DENSITY PROGRAMMABLE LOGIC Pins 14000 Gates Registers High Speed Global Interconnect Wide Input Gating Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size Random Logic HIGH-PERFORMANCE E2CMOS® TECHNOLOGY fmax Maximum Operating Frequency Propagation Delay Compatible Inputs Outputs Electrically Erasable Reprogrammable Non-Volatile 100% Tested Time Manufacture Unused Product Term Shutdown Saves Power ispLSI FEATURES: In-System Programmable (ISPTM) Using Lattice Boundary Scan Test (IEEE 1149.1) Protocol Increased Manufacturing Yields, Reduced Time-toMarket, Improved Product Quality Reprogram Soldered Devices Faster Debugging 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
Functional Block Diagram
Output Routing Pool (ORP)
Boundary Scan
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Array
Array
Twin
Output Routing Pool (ORP)
Array
Output Routing Pool (ORP)
Global Routing Pool (GRP)
OFFERS EASE FAST SYSTEM SPEED PLDs WITH DENSITY FLEXIBILITY FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Combine Glue Logic Structured Designs Enhanced Locking Capability Five Dedicated Clock Input Pins Synchronous Asynchronous Clocks Programmable Output Slew Rate Control Minimize Switching Noise Flexible Placement Optimized Global Routing Pool Provides Global Interconnectivity Compatible with ispLSI 3160 ispDesignEXPERT- LOGIC COMPILER COMPLETE DEVICE DESIGN SYSTEMS FROM SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality Results Tightly Integrated with Leading Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator ispANALYZER- UNIX Platforms
Output Routing Pool (ORP)
Output Routing Pool (ORP)
0139/3320
Description
ispLSI 3320 High-Density Programmable Logic Device containing Registers, Universal pins, five Dedicated Clock Input Pins, Output Routing Pools (ORP) Global Routing Pool (GRP) which allows complete inter-connectivity between these elements. ispLSI 3320 features in-system programmability in-system diagnostic capabilities. ispLSI 3320 offers non-volatile reprogrammability logic, well interconnect provide truly reconfigurable systems. basic unit logic ispLSI 3320 device Twin Generic Logic Block (Twin GLB) labelled A1.J3. There total these Twin GLBs ispLSI 3320 device. Each Twin inputs, programmable array OR/Exclusive-OR Arrays, eight outputs which configured either combinatorial registered. Twin inputs come from GRP.
Copyright 1999 Lattice Semiconductor Corp. brand product names trademarks registered trademarks their respective holders. specifications information herein subject change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; (503) 268-8556; http://www.latticesemi.com
1999
3320_06
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Specifications ispLSI 3320
Functional Block Diagram
Figure ispLSI 3320 Functional Block Diagram
BSCAN/ispEN TMS/MODE TCK/SCLK
Input
Input Output Routing Pool (ORP)
Input Output Routing Pool (ORP)
Boundary Scan
GOE0
GOE1
TDI/SDI TRST TDO/SDO
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input
Input Input
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input
Output Routing Pool (ORP)
Global Routing Pool (GRP)
Output Routing Pool (ORP) Input
RESET
Output Routing Pool (ORP) Input
Output Routing Pool (ORP) Input
IOCLK IOCLK
0139/3320
Specifications ispLSI 3320
Description (continued)
local logic block outputs brought back into they connected inputs other logic block device. device also cells, each which directly connected pin. Each cell individually programmed combinatorial input, registered input, latched input, output bidirectional with 3-state control. signal levels compatible voltages output drivers source sink Each output programmed independently fast slow output slew rate minimize overall output switching noise. cells grouped into sets bits. Each these groups associated with logic Megablock through ORP. Each Megablock able provide Product Term Output Enable (PTOE) signal which globally distributed cells. That PTOE signal generated within Megablock. Each cell select available (two Global PTOEs). Four Twin GLBs, cells connected together make logic Megablock. Megablock defined resources that shares. outputs four Twin GLBs connected cells ORP. ispLSI 3320 Device contains these Megablocks. inputs outputs from Twin GLBs inputs from bidirectional cells. these signals made available inputs Twin GLBs. Delays through have been equalized minimize timing skew logic glitching. Clocks ispLSI 3320 device provided through five dedicated clock pins. five pins provide three clocks Twin GLBs clocks cells. table below lists attributes device along with number resources available. additional feature ispLSI 3320 Boundary Scan capability, which composed cells connected between on-chip system logic device's input output pins. pins have associated boundary scan registers, with 3-state using three boundary scan registers inputs using one. ispLSI 3320 supports IEEE 1149.1 mandatory instructions, which include BYPASS, EXTEST SAMPLE.
Attributes ispLSI 3320
Attribute Twin GLBs Registers Pins Global Clocks Global Test Quantity
Table 1-0003/3320
Specifications ispLSI 3320
Absolute Maximum Ratings
Supply Voltage -0.5 +7.0V Input Voltage Applied -2.5 +1.0V Off-State Output Voltage Applied -2.5 +1.0V Storage Temperature 150°C Case Temp. with Power Applied 125°C Max. Junction Temp. (TJ) with Power Applied (208-Pin PQFP MQFP) 150°C Max. Junction Temp. (TJ) with Power Applied (320-Ball BGA) 140°C
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation device these other conditions above those indicated operational sections this specification implied (while programming, follow programming specifications).
Recommended Operating Condition
SYMBOL PARAMETER Ambient Temperature Supply Voltage Input Voltage Input High Voltage MIN. 4.75 MAX. 5.25 UNITS
Table 2-0005/3320
Capacitance (TA=25°C,f=1.0 MHz)
SYMBOL PARAMETER Capacitance Clock Capacitance TYPICAL UNITS TEST CONDITIONS 5.0V, VI/O 2.0V 5.0V, 2.0V
Table 2-0006/3320
Data Retention Specifications
PARAMETER Data Retention ispLSI Erase/Reprogram Cycles MINIMUM 10000 MAXIMUM UNITS Years Cycles
Table 2-0008/3320
Specifications ispLSI 3320
Switching Test Conditions
Input Pulse Levels Input Rise Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels measured 0.5V from steady-state active level. 3.0V 1.5V 1.5V Figure
Table 2-0003/3320
Figure Test Load
Device Output Test Point
Output Load conditions (See Figure
TEST CONDITION Active High Active Active High -0.5V Active +0.5V 35pF 35pF 35pF
Table 0004A
includes Test Fixture Probe Capacitance.
0213A
Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Voltage Output High Voltage Input Leakage Current Input High Leakage Current ispEN Input Leakage Current Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL= (Max.) 3.5V VOUT 0.5V 0.0V, 3.0V, fCLOCK CONDITION MIN. TYP.
MAX. UNITS -150 -150 -200
IIL-isp IIL-PU IOS1 ICC2,
output time maximum duration second. VOUT 0.5V selected avoid test problems Table 2-0007/3320 tester ground degradation. Characterized 100% tested. Measured using twenty 16-bit counters. Typical values 25°C. Maximum varies widely with specific device configuration operating frequency. Refer Power Consumption section this data sheet Thermal Management section Lattice Semiconductor Data Book CD-ROM estimate maximum
Specifications ispLSI 3320
External Switching Characteristics1,
Over Recommended Operating Conditions
PARAMETER TEST COND.
DESCRIPTION
-100
70.0 50.0 83.0 11.0 12.0 15.0 18.0 10.0 15.0 21.0 21.0 12.0 12.0 15.0 15.0
MIN. MAX. MIN. MAX. 10.0 13.0 13.5 18.0 18.0 12.0 12.0
UNITS
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 tsu2 tco2 trw1 tptoeen tptoedis tgoeen tgoedis ttoeen ttoedis tsu3
Data Propagation Delay, Bypass, Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Maximum Toggle
tsu2 tco1
Clock Frequency with External Feedback
77.0
Reg. Setup Time before Clock, Bypass Reg. Clock Output Delay, Bypass Reg. Hold Time after Clock, Bypass Reg. Setup Time before Clock Reg. Clock Output Delay Reg. Hold Time after Clock Ext. Reset Output Delay Ext. Reset Pulse Duration Input Output Enable Input Output Disable Global Output Enable Global Output Disable Test Output Enable Test Output Disable Ext. Synchronous Clock Pulse Duration, High Ext. Synchronous Clock Pulse Duration, Setup Time before Ext. Synchronous Clock (Y3, Hold Time after Ext. Sync Clock (Y3,
Unless noted otherwise, parameters PTXOR path ORP. Refer Timing Model this data sheet further details. Standard 16-bit counter using feedback. fmax (Toggle) less than 1/(twh twl). This allow clock duty cycle other than 50%. Reference Switching Test Conditions section.
Table 2-0030/3320
Specifications ispLSI 3320
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Inputs
DESCRIPTION
-100
MIN. MAX. MIN. MAX. -3.0 13.0 -4.0 18.2 11.5
UNITS
tiobp tiolat tiosu tioh tioco tior
Register Bypass Latch Delay Register Setup Time before Clock Register Hold Time after Clock Register Clock Delay Register Reset Delay Delay Feedback Delay Product Term Bypass Path Delay (Comb.) Product Term Bypass Path Delay (Reg.) Product Term/XOR Path Delay Product Term/XOR Path Delay Adjacent Path Delay
tgrp tfeedback
t4ptbp t4ptbr t1ptxor t20ptxor txoradj tgbp tgsu tgco tgro tptre tptoe tptck
Register Bypass Delay Register Setup Time before Clock Register Hold Time after Clock Register Clock Output Delay Register Reset Output Delay Product Term Reset Register Delay Product Term Output Enable Cell Delay Product Term Clock Delay Delay Bypass Delay
torp torpbp
Internal Timing Parameters tested reference only. Refer Timing Model this data sheet further details. adjacent path only used hard macros.
Table 2-0036/3320
Specifications ispLSI 3320
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Outputs
DESCRIPTION
-100
MIN. MAX. MIN. MAX. 12.0 13.0 10.0
UNITS
tobs toen todis
Clocks
Output Buffer Delay Output Buffer Delay, Slew Limited Adder Cell Output Enabled Cell Output Disabled Clock Delay, Global Clock Line Clock Delay, Cell Global Clock Line Global Reset Registers Global Buffer Test Buffer
tgy0/1/2 tioy3/4
Global Reset
tgoe ttoe
Internal Timing Parameters tested reference only. Refer Timing Model this data sheet further details.
Table 2-0037/3320
Specifications ispLSI 3320
ispLSI 3320 Timing Model
Cell Feedback Cell
(Input)
Bypass Input Register
Bypass Delays
Bypass Delay
Bypass Delay
#47,
(Output)
Reset Y3,4
#49,
Control
Y0,1,2
GOE0,1
0902/3320
Derivations tsu, from Product Term Clock
11.7 Logic Clock (min) (tiobp tgrp t20ptxor) (tgsu) (tiobp tgrp tptck(min)) (#24+ #30+ #35) (#38) (#24+ #30+ #44) (1.5 4.5) (1.0) (1.5 3.2) Clock (max) Logic (tiobp tgrp tptck(max)) (tgh) (tiobp tgrp t20ptxor) (#24+ #30+ #44) (#39) (#24+ #30+ #35) (1.5 3.2) (4.9) (1.5 4.5) Clock (max) Output (tiobp tgrp tptck(max)) (tgco) (torp tob) (#24 #44) (#40) (#45 #47) (1.5 3.2) (0.5) (1.5 2.0)
Table 2-0042/3320
Note: Calculations based timing specs ispLSI 3320-100L.
Specifications ispLSI 3320
Power Consumption
Power consumption ispLSI 3320 device depends primary factors: speed which device operating number product terms used. Figure Typical Device Power Consumption fmax Figure shows relationship between power operating speed.
ispLSI 3320
(mA)
fmax (MHz)
Notes: Configuration 16-bit Counters Typical Current
estimated ispLSI 3320 using following equation: 0.5) nets Max. freq 0.0095) where: Number Product Terms used design nets Number Signals used device Max. freq Highest Clock Frequency device estimate based typical conditions (VCC 5.0V, room temperature) assumption loads average exists. These values estimates only. Since value sensitive operating conditions program device, actual should verified.
0127A/3320
Specifications ispLSI 3320
Signal Descriptions
Signal Name GOE0, GOE1 RESET BSCAN/ispEN Description Global Output Enable input pins. Input/Output Pins These general purpose pins used logic array. Test Output Enable This tristates pins when logic driven. Active Reset which resets registers device. Dedicated Clock inputs. These clock inputs connected clock inputs GLBs device. Dedicated Clock inputs. These clock inputs connected clock inputs cells device. Input Dedicated in-system programming enable input pin. When this high, BSCAN controller pins TMS, TDI, enabled. When this brought low, State Machine control pins MODE, SDI, SCLK enabled. High-to-low transition this will device programming mode pins high-Z state. Input This performs functions. Test Data input when ispEN logic high. When ispEN logic low, functions input load programming data into device. also used control pins State Machine. Input This performs functions. Test Clock input when ispEN logic high. When ispEN logic low, functions clock Serial Shift Register. Input This performs functions. Test Mode Select input when ispEN logic high. When ispEN logic low, functions control operation State Machine. Input Test Reset, active reset Boundary Scan State Machine. Output This performs functions. When ispEN logic low, functions read data. When ispEN high, functions Test Data Out. Ground (GND) Connect.
TDI/SDI
TCK/SCLK TMS/MODE TRST TDO/SDO
pins connected active signals, GND.
Specifications ispLSI 3320
Signal Locations
Signal GOE0, GOE1 RESET BSCAN/ispEN TDI/SDI TCK/SCLK TMS/MODE TRST TDO/SDO 133, 132, 130, 129, 128, 104, 115, 131, 146, 157, 169, 183, 196, 118, 143, 162, 181, 180, 182, 208-Pin PQFP/MQFP AD12, AC11 AA12, AC13, AB13, AA13, AD13 A16, B13, D19, F21, H22, N23, T24, W21, AA6, AA19, AB17, AC12, B10, B18, D21, K23, V23, AA4, AA21,AC7, AC15 A11, A14, A20, A23, A24, B16, B17, B20, B23, B24, C13, C17, C20, C24, D11, D14, D17, D20, E22, E23, F24, G21, G23, H23, J23, J24, L21, L24, M21, M22, M23, N21, N22, N24, P21, P24, R22, T23, U21, U22, U23, Y21, Y22, Y23, Y24, AA5, AA8, AA11, AA14, AA18, AB1, AB5, AB8, AB12, AB20, AC1, AC2, AC5, AC8, AC9, AC16, AC17, AC20, AC23, AC24, AD1, AD2, AD5, AD11, AD14, AD16, AD19, AD22, AD23, AD24 320-Ball
pins connected active signals, GND.
Specifications ispLSI 3320
Locations
Signal PQFP/ MQFP Signal PQFP/ MQFP Signal PQFP/ MQFP Signal PQFP/ MQFP
AA24 AA23 AB24 AA22 AB23 AB22 AC22 AB21 AA20 AC21 AD21 AB19 AD20 AC19 AB18 AA17 AC18 AD18 AA16 AB16 AD17 AA15 AB15 AD15 AB14 AC14
AB11 AD10 AC10 AB10 AA10
Specifications ispLSI 3320
Configuration
ispLSI 3320 208-Pin PQFP (with Heat Spreader) 208-Pin MQFP Pinout Diagram
TDO/SDO
TMS/MODE TCK/SCLK TDI/SDI BSCAN/ispEN RESET 1TRST/NC
ispLSI 3320
View
GOE1 GOE0
pins connected active signal, GND.
208MQUAD/3320
Specifications ispLSI 3320
Signal Configuration
ispLSI 3320 320-Ball Signal Diagram
TMS/ TRST MODE
ispEN/ BSCAN TDI/
TCK/ RESET SCLK
ispLSI 3320
Bottom View
SDO/
connected active signals, GND. Note: Ball indicator side package.
320BGA/3320
Specifications ispLSI 3320
Part Number Description
ispLSI 3320 XXXX
Device Family Device Number Speed fmax fmax Grade Blank Commercial Package PQFP (with Heat Spreader) B320 MQFP* Power
0212A/3320
Ordering Information
COMMERCIAL
FAMILY fmax (MHz) ispLSI (ns) ORDERING NUMBER ispLSI 3320-100LQ ispLSI 3320-100LB320 ispLSI 3320-100LM* ispLSI 3320-70LQ ispLSI 3320-70LB320 ispLSI 3320-70LM* PACKAGE 208-Pin PQFP 320-Ball 208-Pin MQFP 208-Pin PQFP 320-Ball 208-Pin MQFP
Table 2-0041A/3320
*Use 208-pin PQFP designs.
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