General Description SiI164 transmitter uses PanelLink® Digital te
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PanelLink Transmitter Data Sheet
General Description SiI164 transmitter uses PanelLink® Digital
technology support displays ranging from UXGA resolutions 165Mpps) single link interface. SiI164 transmitter highly flexible interface with either 12-bit mode pixel clock edge) 24-bit mode 1pixel/clock input true color (16.7 million) support. 24-bit mode, SiI164 supports single dual edge clocking. 12-bit mode, SiI164 supports dual edge single clocking single edge dual clocking. SiI164 programmed though interface. SiI164 support Receiver Plug Detection. PanelLink Digital technology simplifies design resolving many system level issues associated with high-speed mixed signal design, providing system designer with digital interface solution that quicker market lower cost.
Scaleable Bandwidth: Megapixels/sec (VGA UXGA) Flexible Graphics Controller Interface: 12-bit pixel) 24-bit mode pixel/clock inputs Flexible Input Clocking: Single clock single edge (24-bit), Single clock dual edge (12/24-bit), Dual clock single edge (12-bit) Slave Programming Interface Voltage Interface: 3.3V with option 1.8V Receiver Detection: Supports Plug Detection De-skewing Option: varies clock data timing Power: 3.3V core operation power down mode Cable Distance Support: over with twisted pair fiber-optics ready Standards Compliant with (DVI backwards compliant with VESA® P&Dand DFP)
SiI164 Diagram
EXT_SWING PVCC1
AGND
AGND
AGND
AVCC
AVCC
RESERVED DKEN
PGND
TXC+
TX2+
TX1+
TX0+
TXC-
TX2-
TX1-
TX0-
BSEL/SCL DSEL/SDA ISEL/RST MSEN EDGE/HTPLG CTL1/A1/DK1 CTL2/A2/DK2 CTL3/A3/DK3 VSYNC HSYNC VREF
64-Pin TQFP
(Top View)
PVCC2
IDCK-
Figure Diagram
Silicon Image, Inc.
IDCK+
Subject Change without Notice
SiI164
SiI/DS-0021-A
Functional Block Diagram
TXC[1:0] TX0[1:0] TX1[1:0] TX2[1:0] MSEN
Slave Machine
Registers Configuration Logic Block
PanelLink Digital core
EXT_RES
Data Capture Logic Block
VREF
HSYNC
HTPLG
VSYNC
EDGE
ISEL/RST
CTL[3:1]
Electrical Specifications
Absolute Maximum Conditions Symbol Parameter Supply Voltage 3.3V Input Voltage Output Voltage Ambient Temperature (with power applied) TSTG Storage Temperature Package Power Dissipation
Notes:
DK[3:1]
D[23:0]
-0.3 -0.3 -0.3
IDCK+
DKEN
IDCK-
PFEN
BSEL
A[3:1]
DSEL
VCC+ VCC+
Units
Permanent device damage occur absolute maximum conditions exceeded. Functional operation should restricted conditions described under Normal Operating Conditions.
Normal Operating Conditions Symbol Parameter Supply Voltage VCCN Supply Voltage Noise Ambient Temperature (with power applied)
Notes: Guaranteed design.
Units mVP-P
Silicon Image, Inc.
Subject Change without Notice
SiI164 Digital Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions High Swing High-level Input VREF Voltage High Swing Low-level Input VREF Voltage Swing Voltage VDDQ VCINL VCIPL
SiI/DS-0021-A
Units
VDDQ/2 300mV VDDQ/2 100mV -0.8
Swing High-level Input Voltage Swing Low-level Input Voltage Input Clamp Voltage Input Clamp Voltage Input Leakage Current
VREF VDDQ/2 VREF VDDQ/2 -18mA 18mA
Notes: Guaranteed design. VDDQ Defines voltage level swing input. actual input voltage.
Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions Differential Voltage RLOAD Single ended peak peak amplitude REXT_SWING VDOH Differential High-level Output Voltage VREF Input Reference Voltage Swing High Swing VOUT IDOS Differential Output Short Circuit Current 25°C Ambient, Power-down Current 3.3V ICCT Transmitter Supply Current DCLK 165MHz, pixel/clock mode, REXT_SWING Worst Case Pattern 25°C Ambient
Notes: Guaranteed design. Assumes inputs transmitter toggling. Black white checkerboard pattern, each checker pixel wide.
AVCC VDDQ/2
Units
Silicon Image, Inc.
Subject Change without Notice
SiI164 Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions TCIP IDCK Period, 1-pixel/clock FCIP IDCK Frequency, 1-pixel/clock TCIH IDCK High Time 165MHz TCIL IDCK Time 165MHz TIJIT Worst Case IDCK Clock Jitter TSIDF Data, VSYNC, HSYNC Single Edge Setup Time IDCK falling edge (DSEL DKEN EDGE THIDF Data, VSYNC, HSYNC Single Edge Hold Time from IDCK falling edge (DSEL DKEN EDGE TSIDR Data, VSYNC, HSYNC Single Edge Setup Time IDCK rising edge (DSEL DKEN EDGE THIDR Data, VSYNC, HSYNC Single Edge Hold Time from IDCK rising edge (DSEL DKEN EDGE Dual Edge TSID Data, VSYNC, HSYNC (DSEL DKEN Setup Time IDCK falling/rising BSEL edge Dual Edge THID Data, VSYNC, HSYNC Hold Time from IDCK falling/rising (DSEL DKEN BSEL edge TDDF VSYNC, HSYNC Delay from falling edge TDDR VSYNC, HSYNC Delay rising edge Vertical Blanking Only THDE high time Vertical Blanking Only TLDE time TSTEP De-skew step size increment DKEN SLHT Differential Swing Low-to-High CLOAD 5pF, Transition Time RLOAD REXT_SWING SHLT Differential Swing High-to-Low CLOAD 5pF, Transition Time RLOAD REXT_SWING
SiI/DS-0021-A
6.06
Units
1TCIP 1TCIP 8191TCIP 128TCIP
Notes: Guaranteed design. Jitter estimated triggering digital scope rising input clock measuring peak peak time spread rising edge input clock both 0.5µs 1.0µs after trigger. Actual jitter tolerance higher depending frequency jitter. time defined Specification, Section Link Timing Requirements.
Silicon Image, Inc.
Subject Change without Notice
SiI164 Input Timing Diagrams
SiI/DS-0021-A
TCIP TCIH
TCIL
Figure Clock Cycle/High/Low Times
SLHT
SHLT
Figure Differential Transition Times
IDCK+/IDCKTSIDF D[23:0], HSYNC,VSYNC,
THIDF
TSIDR THIDR
Figure Control Single-Edge-Data Setup/Hold Times IDCK+/IDCK-
Silicon Image, Inc.
Subject Change without Notice
SiI164
SiI/DS-0021-A
IDCK+ TSID THID TSID THID
D[23:0], VSYNC, HSYNC
Figure Dual Edge Data Setup/Hold Times IDCK+
TDDF
TDDR VSYNC, HSYNC
VSYNC, HSYNC
Figure VSYNC, HSYNC Delay Times from/to
THDE
TLDE
Figure High/Low Times
Silicon Image, Inc.
Subject Change without Notice
SiI164
SiI/DS-0021-A
Data Mapping
12-bit Input Mode (BSEL
half pixel High half pixel
D[11:0]
PN-1H
IDCK+
DSEL
IDCK+
DSEL
EDGE
IDCK-
IDCK+
DSEL
IDCK+
DSEL
EDGE
IDCKFirst Latch Edge
Figure Logical Interface Options 12-bit Mode
12-bit Mode Data Mapping Name
Notes:
High R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] G0[7] G0[6] G0[5] G0[4] G1[3] G1[2] G1[1] G1[0] B1[7] B1[6] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] High R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[7] G1[6] G1[5] G1[4] G2[3] G2[2] G2[1] G2[0] B2[7] B2[6] B2[5] B2[4] B2[3] B2[2] B2[1] B2[0]
High R2[7] R2[6] R2[5] R2[4] R2[3] R2[2] R2[1] R2[0] G2[7] G2[6] G2[5] G2[4]
G0[3] G0[2] G0[1] G0[0] B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0]
figure, clock edges represented arrows signify latching edge. primary latch edge indicated dark rows. lower half pixel latched primary clock edge. Color Pixel Components: RED, GREEN, BLUE significance within color: [7:0] [MSB:LSB]
Silicon Image, Inc.
Subject Change without Notice
SiI164 24-bit Input Mode (BSEL
SiI/DS-0021-A
D[23:0]
PN-1
IDCK+
DSEL EDGE
IDCK+
DSEL EDGE
IDCK+
First Latching Edge
DSEL
Figure Logical Interface Options 24-bit Mode
Note: 24-bit Single Clock Dual Edge Mode, SiI164 will look first clock edge (either falling rising) after goes high determine first pixel data. EDGE affect 24-bit Single Clock Dual Edge Mode.
24-bit Mode Data Mapping1,2,3
Name
Notes:
R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] G0[7] G0[6] G0[5] G0[4] G0[3] G0[2] G0[1] G0[0] B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0]
R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[7] G1[6] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[7] B1[6] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0]
R2[7] R2[6] R2[5] R2[4] R2[3] R2[2] R2[1] R2[0] G2[7] G2[6] G2[5] G2[4] G2[3] G2[2] G2[1] G2[0] B2[7] B2[6] B2[5] B2[4] B2[3] B2[2] B2[1] B2[0]
figure, clock edges represented arrows signify latching edge. Color Pixel Components: RED, GREEN, BLUE significance within color: [7:0] [MSB:LSB]
Silicon Image, Inc.
Subject Change without Notice
SiI164
SiI/DS-0021-A
Data De-skew
Input clock data setup/hold time adjusted through de-skew feature. should noted that clock that being adjusted. When DKEN HIGH, configuration pins DK[3:1] applicable registers used vary input setup/hold time amount given formula (DK[3:1] 260psec. Where: amount setup/hold timing variation DK[3:1] setting de-skew configuration pins registers This feature used both 12-bit 24-bit mode. DKEN SiI164 mode, DK[3:1] inputs ignored, default setting used.
D[23:0]
CLK+
CLK-
-TCD DK[3:1]
default Figure SiI164 De-skewing feature timing
Silicon Image, Inc.
Subject Change without Notice
SiI164
SiI/DS-0021-A
Pins Descriptions
Input Pins Name D23-D12 36-47 Type Description half 24-bit pixel bus. When BSEL HIGH, this inputs half 24-bit pixel bus. When BSEL LOW, these bits used input pixel data. this mode, state D[23:16] input register CFG. This allows 8bits user configuration data read graphics controller through interface (see register definition). D[15:12] reserved only should tied when use. Bottom half 24-bit pixel 12-bit pixel input. When BSEL HIGH, this inputs bottom half 24-bit pixel bus. When BSEL LOW, this inputs pixel (12-bits) every latch edge (both falling and/or rising) clock. Input Data Clock Input Data Clock This clock only used 12-bit mode when dual edge clocking turned (DSEL LOW). used provide latching edges dual clock single edge. (BSEL HIGH) (DSEL HIGH) this unused should tied GND. Data enable. This signal high when input pixel data valid transmitter otherwise. critical that this signal have same setup/hold timing data bus. Horizontal Sync input control signal. Vertical Sync input control signal. these multi-function inputs depends settings ISEL DKEN. These inputs regular high-swing 3.3V CMOS level inputs. These pins contain weak pull-down resistors that left unconnected, they will LOW. ISEL LOW, DKEN General Purpose Input CTL[3:1] active, backward compatibility. These pins must used send signals only during blanking time. ISEL LOW, DKEN HIGH DK[3:1] active, these inputs used select de-skewing setting input bus. ISEL HIGH, DKEN A[3:1] active, these bits used lower bits device address.
D11-D0
50-55, 58-63
IDCK+ IDCK-
HSYNC VSYNC CTL1/A1/DK1 CTL2/A2/DK2 CTL3/A3/DK3
Status Name MSEN
Type
Description Monitor Sense. This open collector output. behavior this output depends whether interface enabled disabled. disabled (ISEL LOW) HIGH level indicates powered receiver detected differential outputs. level indicates powered receiver detected. This function only used DC-coupling systems. enabled (ISEL HIGH) output programmable through interface (see register definitions). external pull-up resistor required this systems without internal pull-up resistor.
Silicon Image, Inc.
Subject Change without Notice
SiI164 Configuration/Programming Pins Name Type Description
ISEL/RST
SiI/DS-0021-A
Interface Select. HIGH, then interface active. LOW, inactive chip configuration read from configuration strapping pins. This also acts asynchronous reset interface controller. reset active when this input held LOW. Note: When interface active, DKEN must HIGH Input select clock. This open collector input. enabled (ISEL HIGH), then this clock input. disabled (ISEL LOW), then this selects input width. Input Select HIGH selects 24-bit input mode selects 12-bit input mode Dual edge clock select Data. This open collector input. enabled (ISEL HIGH), then this data line. disabled (ISEL LOW), then this selects whether single clock dual edge used. Dual edge clock select When HIGH, IDCK+ latches input data both falling rising clock edges. When LOW, IDCK+/IDCK- latches input data only falling rising clock edges. 24-/12-bit mode: HIGH (dual edge), IDCK+ used latch data both falling rising edges. (single edge), IDCK+ latches half data IDCK- latches half data. Edge select Plug input. enabled (ISEL HIGH), then this used monitor "Hot Plug" detect signal (Please refer VESA standards). NOTE: This Input ONLY 3.3V tolerant internal debouncer circuit. disabled (ISEL LOW), then this selects clock edge that will latch data. EDGE setting works depends whether dual single edge latching selected Dual Edge Mode (DSEL HIGH) EDGE LOW, primary edge (first/even latch edge after asserted) falling edge. EDGE HIGH, primary edge (first/odd latch edge after asserted) rising edge. Note: 24-bit single clock dual edge mode, EDGE ignored. Single Edge Mode (DSEL LOW) EDGE LOW, falling edge clock used latch data. EDGE HIGH, rising edge clock used latch data. De-Skewing enable. enabled (ISEL HIGH), then this must HIGH DK[3:1] ignored de-skewing increments selected through interface (see register definitions). disabled (ISEL LOW), then this enables de-skewing increments read through DK[3:1] pins. When DKEN LOW, then default de-skewing setting used. When DKEN HIGH, then DK[3:1] used de-skewing setting. deskewing increments 260psec.
BSEL/SCL
DSEL/SDA
EDGE/HTPLG
DKEN
Silicon Image, Inc.
Subject Change without Notice
SiI164
SiI/DS-0021-A
Input Voltage Reference Name Type Description VREF Analog Input Reference Voltage. Selects swing range digital parallel data inputs (D[23:0], VSYNC, HSYNC, IDCK). When VREF HIGH, digital parallel data inputs normal high swing 3.3V inputs. When VREF below 1.8V, digital parallel data inputs swing inputs. swing mode, VREF must VDDQ. Power Management Name Type
Description Power Down (active LOW). HIGH level indicates normal operation level indicates power down mode. During power down mode, digital input, output buffers interface disabled. PanelLink Digital core powered down. Note that when ISEL HIGH, this should tied ensure chip powered when RESET asserted.
Reserved Name RESERVED
Type
Description Must tied normal operation.
Differential Signal Data Pins Name Type Description Analog TMDSLow Voltage Differential Signal output data pairs. TX0+ Analog TX0Analog TX1+ Analog TX1Analog TX2+ Analog TX2TXC+ TXCEXT_SWING Analog TMDSLow Voltage Differential Signal output clock pairs. Analog Analog Voltage Swing Adjust. resistor should this AVCC. This resistance determines amplitude voltage swing. remote display applications, recommended. notebook computers, recommended.
Power Ground Pins Name Type Description 1,12,33 Power Digital VCC, must 3.3V nominal. 16,48,64 Ground Digital GND. AVCC AGND PVCC1 PVCC2 PGND 23,29 Power Analog VCC, must 3.3V nominal. 20,26,32 Ground Analog GND. Power Analog VCC, must 3.3V nominal. Power Analog VCC, must 3.3V nominal. Ground Analog GND.
Silicon Image, Inc.
Subject Change without Notice
SiI164
SiI/DS-0021-A
Registers
Register Mapping Addr. RSVD[1:0]
Notes:
VND_IDL (RO) VND_IDH (RO) DEV_IDL (RO) DEV_IDH (RO) DEV_REV (RO) RSVD[7:0] (RO) FRQ_LOW (RO) FRQ_HIGH (RO) (R/W) (R/W) DSEL BSEL EDGE (RW) (RW) (RW) VLOW (RO) MSEL[2:0] (RW) TSEL RSEN HTPLG (RW) (RO) (RO) DK[3:1] (RW) DKEN CTL[3:1] (RW) (RW) CFG[7:0] (D[23:16]) (RO) VDJK[7:0] (RW) Must "89h" normal operation. RSVD[3:0] (RW) RSVD[3:0] (RO) RSVD[7:0] (RW) RSVD[7:0] (RW)
(RW) (RW) RSVD (RW)
values [MSB] [LSB]. Read/Write register, Read Only register. RSVD Reserved register. available future Silicon Image, Inc. Values Bold/Italics Silicon Image, Inc. read/write register that RESERVED will require that user always write recommended values. There default value RESET except MSEL. registers must written least once before normal operation occur. other registers retain their values after RESET except MSEL.
Note that register must "89h" normal operation.
Silicon Image, Inc.
Subject Change without Notice
SiI164 Register Definitions Register Name Access VND_IDL VND_IDH DEV_IDL DEV_IDH DEV_REV FRQ_LOW FRQ_HIGH EDGE
SiI/DS-0021-A
BSEL DSEL HTPLG RSEN TSEL MSEL[2:0]
Description Vendor byte (01h) Vendor High byte (00h) Device byte (06h) Device High byte (00h) Device Revision (00h) frequency limit 1-pixel/clock mode (MHz) (19h) High frequency limit 1-pixel/clock mode minus 65MHz (MHz) (64h) Power Down mode(same function pin) Power Down (Default after RESET) Normal operation Edge Select (same function EDGE pin) Input data falling edge latched (falling edge latched first dual edge mode) Input data rising edge latched (rising edge latched first dual edge mode) Input Select (same function BSEL pin) Input data 12-bits wide Input data 24-bits wide Dual Edge Clock Select (same function DSEL pin) Input data single edge latched Input data dual edge latched Horizontal Sync Enable: HSYNC input transmitted fixed HSYNC input transmitted Vertical Sync Enable: VSYNC input transmitted fixed VSYNC input transmitted Monitor Detect Interrupt Detection signal changed logic level (write this clear) Detection signal changed state Plug Detect input, state HTPLG read from this This HIGH powered receiver connected transmitter outputs, otherwise. This function only available DC-coupled systems. Interrupt Generation Method Interrupt (MDI) generated monitoring RSEN (MDI) generated monitoring HTPLG Select source MSEN output Force MSEN outputs high (disabled default after RESET) Outputs (interrupt) Output RSEN (receiver detect) Outputs HTPLG (hot plug detect) This VREF signal indicates swing inputs. VREF indicates high swing inputs General purpose inputs (same CTL[3:1] pins) Contains state inputs D[23:16]. These pins used provide user selectable configuration data through bus. Only available 12-bit mode Must "89h" normal operation
VLOW CTL[3:1] CFG[7:0] VDJK[7:0]
Silicon Image, Inc.
Subject Change without Notice
SiI164
SiI/DS-0021-A
Register Definitions (cont'd) Register Name Access Description De-Skewing Setting. Increment 260psec. DK[3:1] step minimum setup maximum hold step step step step default step step step maximum setup minimum hold De-Skewing Enable through DK[3:1] bits. HIGH when enabled, DKEN otherwise. Slave Interface SiI164 slave state machine does require internal clock supports only byte read write (see Figures below). Page mode supported. 7-bit binary address machine "0111 A3A2A1X", where A[3:1] programmable "000" default.
Start
Start
Line
Activity
Data
Figure Byte Read
Start
Line
Activity
Figure Byte Write
Silicon Image, Inc.
Subject Change without Notice
Stop
Activity Master
Slave Address
Address
Data
Stop
Activity Master
Slave Address
Address
Slave Address
SiI164
SiI/DS-0021-A
RESET Description
input ISEL/RST serves asynchronous RESET (active LOW) slave controller mode. programming registers, that accessible over bus, retain their previous values during after RESET. Registers MSEL[2:0] both disabled after RESET. registers must manually ensure proper operation. minimum time proper RESET TCIP. state these bits during RESET period according following rules: After RESET, SiI164 will turned OFF. When RESET asserted, SiI164 power down control bit, forced LOW. When SiI164 comes RESET (ISEL/RST HIGH), SiI164 will turned OFF. turn SiI164 back must HIGH over bus. After RESET, MSEN output disabled. When RESET asserted, MSEN[2:1] forced `000'. This causes MSEN output tri-stated.
Package Dimensions
64-pin TQPF Package Dimensions
Lead Length 1.00mm Lead Width 0.22mm
64-pin Plastic TQFP
Lead Pitch 0.50mm Body Size 10.00mm Footprint 12.00mm
PanelLink
Device Date Code Rev. SiI164CT LNNNNN.NLLL XXYY X.XX
Package Height 1.0mm max.
Clearance 0.15mm max. Body Size 10.00mm Footprint 12.00mm
Body Thickness
Figure SiI164 Package Diagram
Silicon Image, Inc.
Subject Change without Notice
SiI164
SiI/DS-0021-A
Copyright Notice This manual copyrighted Silicon Image, Inc. reproduce, transform other format, send/transmit part this documentation without express written permission Silicon Image, Inc. Trademark Acknowledgment Silicon Image, Silicon Image logo, PanelLink PanelLink Digital logo registered trademarks Silicon Image, Inc. TMDS trademark Silicon Image, Inc. VESA registered trademark Video Electronics Standards Association. TMDS licensed trademark VESA other trademarks property their respective holders. Disclaimer This document provides technical information user. Silicon Image, Inc. reserves right modify information this document necessary. customer should make sure that they have most recent data sheet version. Silicon Image, Inc. holds responsibility errors that appear this document. Customers should take appropriate action ensure their products does infringe upon patents. Silicon Image, Inc. respects valid patent rights third parties does infringe upon assist others infringe upon such rights. Ordering Information Part Number: SiI164CT64 Revision History Revision Date 6/99 7/99 3/00
Comment First Draft Preliminary release Full release
2000 Silicon Image, Inc. 3/00 /DS-0009-A
Silicon Image, Inc. 1060 Arques Avenue Sunnyvale, 94086
Tel: (408) 616-4000, 1-888-PanelLink Fax: (408) 830-9529 E-mail: salessupport@siimage.com Web: www.siimage.com www.panellink.com
Silicon Image, Inc.
Subject Change without Notice
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