transmitter uses PanelLink Digital technology support displays ranging

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

transmitter uses PanelLink Digital technology support displays ranging

Datasheet Thumbnail

Top Searches for this datasheet

PanelLink® Digital Transmitter
transmitter uses PanelLink Digital technology support displays ranging from UXGA resolutions (25-165 MHz). transmitter supports true color panels bit/pixel, 16.7M colors) pixels/clock mode, also features inter-pair skew tolerance full input clock cycle. advanced on-chip jitter filter also added extend tolerance clock jitter. Since PanelLink products designed scaleable CMOS architecture support future performance requirements while maintaining same logical interface, system designers assured that interface will fixed through number technology performance generations. PanelLink Digital technology simplifies display interface design resolving many system level issues associated with high-speed digital design, providing system designer with digital interface solution that quicker market lower cost.
Features
Scaleable Bandwidth: 25-165 (VGA UXGA) Power: 3.3V core operation High Skew Tolerance: full input clock cycle (6ns MHz) Flexible panel interface: single dual pixel 24-bits Cable Distance Support: over with twisted-pair, fiber-optics ready Compliant with (DVI backwards compatible with VESA® DFP)
Diagram
RESERVED RESERVED RESERVED DIFFERENTIAL SIGNAL AGND AGND AGND AGND DIO21 DIO22 DIO23 AVCC AVCC AVCC TXC+ TX2+ TX1+ TX0+ TXCTX2TX1TX0ODD 8-bits EXT_SWING
Functional Block Diagram
CONFIG. PINS
EXT_SWING DIE[23:0] DIO[23:0] HSYNC VSYNC DATA Data Capture Logic DATA CTL2 CTL3 EDGE PIXS Encoder Tx2Encoder Tx1Tx1+ DATA HSYNC VSYNC Swing Control Tx0+ Tx0-
DIO20 DIO19 DIO18 DIO17 DIO16 DIO15 DIO14 DIO13 DIO12 DIO11 DIO10 DIO9 DIO8 IVCC DIO7
Encoder
PIXS EDGE
RESERVED RESERVED RESERVED RESERVED PGND1 PVCC1 IVCC DIE0 DIE1 EVEN 8-bits BLUE DIE2 DIE3 DIE4 DIE5 DIE6 DIE7 DIE8 DIE9 DIE10 DIE11 DIE12 DIE13 EVEN 8-bits GREEN
CTL1 CTL2 CTL3
Tx2+
8-bits GREEN
(Top View)
IDCK
Jitter Filter
TxC+ TxC-
8-bits BLUE
DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0
DIE23
DIE22
DIE21
DIE20
DIE19
DIE18
DIE17
DIE16
DIE15
VSYNC
PGND2
HSYNC
CONTROLS
Revision
INPUT CLOCK
RESERVED
PVCC2
EVEN 8-bits
DIE14
IDCK
IVCC
IVCC
CTL3
CTL2
CTL1
Subject Change without Notice
Silicon Image, Inc. Absolute Maximum Conditions
SiI-DS-0008-D
Note: Permanent device damage occur absolute maximum conditions exceeded. Functional operation should restricted conditions described under Normal Operating Conditions. Symbol Parameter Units Supply Voltage 3.3V -0.3 Input Voltage -0.3 VCC+ Output Voltage -0.3 VCC+ Ambient Temperature (with power applied) TSTG Storage Temperature Package Power Dissipation
Normal Operating Conditions
Symbol VCCN Parameter Supply Voltage Supply Voltage Noise Ambient Temperature (with power applied) 3.00 Units mVP-P
Digital Specifications
Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage VCINL Input Clamp Voltage1 -18mA VCIPL Input Clamp Voltage1 18mA VCONL Output Clamp Voltage1 -18mA VCOPL Output Clamp Voltage1 18mA Input Leakage Current Note:
-0.8 IVCC -0.8 OVCC
Units
Guaranteed design. Voltage undershoot overshoot cannot exceed absolute maximum conditions pulse greater than third clock cycle.
Specifications
Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions Differential Voltage RLOAD Single ended peak peak amplitude REXT_SWING REXT_SWING VDOH Differential High-level Output Voltage1 IDOS Differential Output Short Circuit Current1 VOUT Power-down Current2 ICCT Transmitter Supply Current IDCK= MHz, 1-pixel/clock mode, (IDCK= MHz, 1-pixel/clock mode) REXT_SWING 510, IVCC VCC, Typical Pattern3 IDCK= MHz, 1-pixel/clock mode, (IDCK= MHz, 1-pixel/clock mode) REXT_SWING 510, IVCC VCC, Worst Case Pattern4 Note: Guaranteed design. Assumes inputs transmitter toggling. Typical Pattern contains gray scale area, checkerboard area, text. Black white checkerboard pattern, each checker pixel wide. AVCC Units
Revision
Subject Change without Notice
Silicon Image, Inc. Specifications
SiI-DS-0008-D
Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions TCIP IDCK Period, Pixel/Clock FCIP IDCK Frequency, Pixel/Clock TCIP IDCK Period, Pixels/Clock FCIP IDCK Frequency, Pixels/Clock TCIH IDCK High Time 165MHz TCIL IDCK Time 165MHz TIJIT Worst Case IDCK Clock Jitter2,3 TSIDF Data, VSYNC, HSYNC, CTL[3:1] EDGE Setup Time IDCK falling edge THIDF Data, VSYNC, HSYNC, CTL[3:1] EDGE Hold Time from IDCK falling edge TSIDR Data, VSYNC, HSYNC, CTL[3:1] EDGE Setup Time IDCK rising edge THIDR Data, VSYNC, HSYNC, CTL[3:1] EDGE Hold Time from IDCK rising edge TDDF VSYNC, HSYNC, CTL[3:1] Delay from falling edge1 TDDR VSYNC, HSYNC, CTL[3:1] Delay rising edge1 THDE high time1 TLDE time1 SLHT Small Swing Low-to-High RLOAD Transition Time REXT_SWING SHLT Small Swing High-to-Low RLOAD Transition Time REXT_SWING Notes: Guaranteed design. Jitter estimated triggering digital scope rising input clock rising edge input clock after trigger. Actual jitter tolerance higher depending frequency jitter.
6.06 12.3 12.5 TCIP TCIP
Units
8191TCIP 128TCIP
measuring peak peak time spread
Timing Diagrams
Figure Clock Cycle/High/Low Times
SLHT
SHLT
Figure Small Swing Transition Times
Revision
Subject Change without Notice
Silicon Image, Inc. Input Timing
SiI-DS-0008-D
IDCK+/IDCKT SIDF D[23:0], HSYNC,VSYNC, CTL[3:1]
HIDF
SIDR HIDR
Figure Input Data Setup/Hold Times IDCK
TDDF
TDDR VSYNC, HSYNC, CTL[3:1]
VSYNC, HSYNC, CTL[3:1]
Figure VSYNC, HSYNC, CTL[3:1] Delay Times from
Figure High/Low Times
Input Description
Name DIE23DIE0 Diagram Type Description Even Input Data[23:0] corresponds 24-bit pixel data 1-pixel/clock input mode first 24-bit pixel data 2-pixels/clock mode. Input data synchronized input data clock (IDCK). Data latched rising falling edge IDCK depending whether EDGE high low, respectively. Refer DSTN Signal Mapping application notes (SiI/AN-0008-A SiI/AN-0007-A, respectively) which tabulate relationship between input data transmitter output data from receiver. Input Data[23:0] corresponds second 24-bit pixel data 2-pixels/clock mode. 1-pixel/clock mode, these inputs don't care. Recommendation them lower power consumption. Input data synchronized input data clock (IDCK). Data latched rising falling edge IDCK depending whether EDGE high low, respectively. Refer DSTN Signal Mapping application notes (SiIAN-0008-A SiIAN-0007-A, respectively) which tabulate relationship between input data transmitter output data from receiver. Input Data Clock. Input data control signals valid either falling rising edge IDCK selected EDGE pin. Input Data Enable. This signal qualifies active data area. always required transmitter must high during active display time during blanking time. Horizontal Sync input control signal. Vertical Sync input control signal. General input control signal General input control signal General input control signal
DIO23 DIO0
Diagram
IDCK HSYNC VSYNC CTL1 CTL2 CTL3
Revision
Subject Change without Notice
Silicon Image, Inc.
SiI-DS-0008-D
Configuration Description
Name EDGE Type Description Data/Control Latching Edge. level indicates that input signals (DIE/DIO[23:0], HSYNC, VSYNC, CTL[3:1]) latched falling edge IDCK, while high level (3.3V) indicates that input signals latched rising edge IDCK. Pixel Select. level indicates pixel 24-bits) clock mode using DIE[23:0]. high level (3.3V) indicates pixels 48-bits) clock mode using DIE[23:0] first pixel DIO[23:0] second pixel.
PIXS
Power Management Description
Name Type Description Power Down (active low). high level (3.3V) indicates normal operation level (GND) indicates power down mode. During power down mode, data (DIE/DIO[23:0]), data enable (DE), clock (IDCK) control signals (HSYNC, VSYNC, CTL[3:1]), input buffers disabled, output buffers tri-stated, internal circuitry powered down.
Differential Signal Data Description
Name TX0+ TX0TX1+ TX1TX2+ TX2TXC+ TXCEXT_SWING Type Analog Analog Analog Analog Analog Analog Analog Analog Analog Description TMDS Voltage Differential Signal output data pairs.
TMDS Voltage Differential Signal output data pairs. Voltage Swing Adjust. resistor should this AVCC. amplitude voltage swing determined this resistance. remote display applications, recommended. notebook computers, recommended.
Reserved Description
Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Type Description Reserved future use. Must tied HIGH normal operation. Reserved future use. Must tied normal operation. Reserved future use. Must tied HIGH normal operation. Reserved future use. Must tied HIGH normal operation. Reserved future use. Must tied HIGH normal operation. Reserved future use. Must tied HIGH normal operation. Reserved future use. Must tied HIGH normal operation. Reserved future use. Must tied HIGH normal operation.
Power Ground Description
Name IVCC AVCC AGND PVCC1 PVCC2 PGND1 8,30,56,88 7,31,57,67,79,89 17,66,81,98 36,38,44 33,37,41,47 Type Power Ground Power Power Ground Power Power Ground Description Digital Core VCC, must 3.3V. Digital GND. Input VCC, must 3.3V. Analog VCC, must 3.3V. Analog GND. Analog VCC, must 3.3V. Analog VCC, must 3.3V. Analog GND. PGND1 should connected GROUND plane. They plane. Analog GND. PGND1 should connected GROUND plane. They plane.
directly connected PGND2 before being should connected individually GROUND directly connected PGND2 before being should connected individually GROUND
PGND2
Ground
Application Information
obtain most updated Application Notes other useful information your design application, please visit Silicon Image site www.siimage.com, contact your local Silicon Image sales office.
Revision
Subject Change without Notice
Silicon Image, Inc.
SiI-DS-0008-D
Package Dimensions 100-pin TQFP Package Dimensions JEDEC Code MS-026
Lead Length 1.00mm
Lead Width 0.20mm
100-pin Plastic TQFP
Lead Pitch 0.50mm
Body Size 14.00mm
3DQHO/LQN
Device Date Code Rev. SiI160 CT100 LNNNNN.NLLL XXYY X.XX
Package Height 1.20mm max.
Clearance 0.15mm max. 12.00mm Body Size 14.00mm Footprint 16.00mm
Body Thickness 1.05 max.
Ordering Information: Part Number: SiI160CT100 Copyright Notice
This manual copyrighted Silicon Image, Inc. reproduce, transform other format, send/transmit part this documentation without express written permission Silicon Image, Inc.
Trademark Acknowledgment Silicon Image, Silicon Image logo, PanelLink PanelLink Digital logo trademarks registered trademarks Silicon Image, Inc. other trademarks property their respective holders. Disclaimer
This document provides technical information user. Silicon Image, Inc. reserves right modify information this document necessary. customer should make sure that they have most recent data sheet version. Silicon Image, Inc. holds responsibility errors that appear this document. Customers should take appropriate action ensure their products does infringe upon patents. Silicon Image, Inc. respects valid patent rights third parties does infringe upon assist others infringe upon such rights. 2000 Silicon Image, Inc. 7/00 SiI-DS-0008-D
Silicon Image, Inc. 1060 Arques Avenue Sunnyvale, 94086
Tel: Fax: E-Mail: Web:
408-616-4000 408-830-9530 salessupport@siimage.com www.siimage.com www.panellink.com
Revision
Subject Change without Notice
Footprint 16.00mm
12.00mm

transmitter uses PanelLink Digital technology support displays ranging

Top Searches for this datasheet

Other recent searches