201C Intelligent Panel Controller (IPC) uses PanelLink Digital technol

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201C Intelligent Panel Controller (IPC) uses PanelLink Digital technol

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201C Intelligent Panel Controller PanelLink Digital
201C Intelligent Panel Controller (IPC) uses PanelLink Digital technology support displays ranging from (25-68 MHz), which ideal notebook desktop monitor applications. With flexible single dual pixel interface selectable output drive, 201C supports true color panels bit/pixel, 16.7M colors) pixels/clock mode. 201C highly programmable support multiple column drivers optimize display quality. PanelLink also features inter-pair skew tolerance full input clock cycle highly jitter tolerant design. PanelLink Digital technology simplifies design resolving many system level issues associated with high-speed digital design, providing system designer with digital interface solution that quicker market lower cost.
Features
Scaleable Bandwidth: 25-68 (VGA XGA) Power: 3.3V core operation power-down mode High Skew Tolerance: full input clock cycle (15ns MHz) Highly programmable: supports multiple column drivers Sync Detect: Plug Display "Hot Plugging" Cable Distance Support: over with twisted-pair, fiberoptics ready Compliant with (DVI backwards compatible with VESA® DFP)
201C Diagram
EXT_RES Reserved Reserved AVCC AGND PGND PVCC RXC+ AGND AVCC OVCC RX0+ RX2+ CK_B
RXC-
RX1+
RX0-
RX1-
RX2-
SCALE_IN ROFF_T(2) ROFF_T(1) ROFF_T(0) ROE_T(1) ROE_T(0) CV_P CONV OGND SCDT /POL CDATA0 OVCC Reserved CDATA1 CDATA2 CDATA3 CDATA4 CDATA5 CDATA6 CDATA7 Reserved CDATA8 PL_T CDATA9
CLT2 CIN2 CLT1 CDIR CDATA47 CDATA46 CDATA45 CDATA44 CDATA43 CDATA42 CDATA41 CDATA40 DINV OGND CDATA39 CDATA38 CDATA37 CDATA36 CDATA35 CDATA34 PIX_O CDATA33 CD_E CDATA32 CDATA31
SiI201C
TQFP
CDATA10
CDATA15
CDATA23
CDATA11
CDATA14
CDATA18
CDATA20
CDATA21
CK_T CDATA16 CK_D CDATA17
CDATA13
CDATA22
OGND CK_P CDATA25
CDATA26
CDATA27
CDATA28
CDATA12
CDATA19
CV_W CDATA24
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CDATA29
CDATA30
OVCC
Silicon Image, Inc. Functional Block Diagram
HSYNC
201C
SiI/DS-0005-C
SCDT Detect
PanelLink Interface
SCALE_IN HSYNC VSYNC
CONV CDTA 24/48 /POL CTL1/CDIR CTL2/CIN2
PanelLink Technology
VSYNC HSYNC IDTA
IDTA
Periphery Controller
CONV CDIR CDTA 24/48
SCDT
Column Control
CV_W CK_D CD_E CK_P CK_B CV_P CK_T
Timing
ROE_T SCALE_IN ROFF_T PIX_O
Polarity
Power Control
PL_T
DINV
201C consists four major blocks: Functional PanelLink Interface, Sync Detection Column Interface. PanelLink Interface: 201C accepts PanelLink interface swing, differential input signals. pair contains pixel clock, other three pairs serialized encoded red, green blue channels. Each color channels also contain encoded control signals. PanelLink technology de-serializes decodes input data recover original panel interface, labeled block diagram. This interface color pixel clock interface bits pixel, recovered input clock ICK. Column Interface(CIN, CCK, CONV, CDTA): column interface block programmed that column drive outputs match desired column drivers. programming pins CK_P, CK_B, CK_D, CK_T, CV_W, CV_P, PL_T DINV wide variety column drivers addressed. Interface(RIN, RCK, ROE): driving signals output from this block. While signals require programmability, their timing with respect column drive signals critical, varies with panel size processing parameters. Sufficient time must allowed select signals fully switched before column driver's analog outputs allowed change. This time TOFF, over wide range values through ROFF_T[2:0] programming input bits. driver chosen output enable, width output enable pulse using ROE_T[1:0]. Sync Detect: This block monitors state HSYNC. HSYNC becomes inactive output signal SCDT will low. This signal used control driver backlight supplies enabling panel protection power savings.
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Silicon Image, Inc. Absolute Maximum Conditions
201C
SiI/DS-0005-C
Note: Permanent device damage occur absolute maximum conditions exceeded. Functional operation should restricted conditions described under Normal Operating Conditions
Symbol
TSTG
Parameter
Supply Voltage Input Voltage Output Voltage Ambient Temperature (with power applied) Storage Temperature Package Power Dissipation
-0.3 -0.3 -0.3
Units
Normal Operating Conditions Symbol Parameter
VCCN Note:
Units
mVP-P
Supply Voltage Supply Voltage Noise Ambient Temperature (with power applied)
Guaranteed design.
Digital Specifications
Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage VCINL Input Clamp Voltage1 -18mA VCIPL Input Clamp Voltage1 18mA VCONL Output Clamp Voltage1 -18mA VCOPL Output Clamp Voltage1 18mA Input Leakage Current Note:
-0.8 IVCC -0.8 OVCC
Units
Guaranteed design.
Specifications
Under normal operating conditions unless otherwise specified. drive strength values, when ST=0, shown brackets. Symbol Parameter Conditions Units (ST=0) Output High Drive (CCK) VOUT 10.5 (ST=1) 16.5 (ST=0) Output Drive (CCK) VOUT -8.5 -15.4 (ST=1) (ST=0) Output High Drive (All Others) VOUT (ST=1) (ST=0) Output Drive (All Others) VOUT -5.6 (ST=1) Differential Input Voltage Single Ended 1000 Amplitude Power-down Current1 IPDL ICCR Output leakage current ground high impedance mode (PD, LOW) Supply Current 3.3V Output pixel clock mode.2 DLCK CLOAD 10pF REXT_SWING Typical Pattern3 DCLK CLOAD 10pF REXT_SWING Worst Case Pattern4
Notes:
transmitter must power-down mode, powered off, disconnected current under this maximum. worst case power consumption. Typical Pattern contains gray scale area, checkerboard area, text. Black white checkerboard pattern, each checker pixel wide.
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Silicon Image, Inc. Specifications
201C
SiI/DS-0005-C
Under normal operating conditions unless otherwise specified. drive strength values, when ST=0, shown brackets. Symbol Parameter Conditions TDPS Intra-Pair Differential Input Skew TCCS Channel Channel Differential Input Skew TIJIT Worst Case Differential Input Clock Jitter tolerance1,2 DLHT Low-to-High Transition Time: Data Controls ST=1 [ST=0] 10pF [5pF] [1.9] [1.4] DHLT High-to-Low Transition Time: Data Controls ST=1 [ST=0] 10pF [5pF] [1.6] [1.2] TSOF Data/Control Setup Time CCK: ST=1 [ST=0] MHz, Pixel Clock, PIXS 10pF [5pF] [5.8] CK_T ST=1 [ST=0] [2.1] 10pF [5pF] CK_T THOF Data/Control Hold Time ST=1 [ST=0] MHz, Pixel Clock, PIXS 10pF [5pF] [4.5] CK_T ST=1 [ST=0] [9.0] 10pF [5pF] CK_T RCIP Cycle Time pixel/clock) 14.7 FCIP Frequency pixel/clock) RCIP Cycle Time pixels/clock) 29.4 FCIP Frequency pixels/clock) RCIH High Time ST=1 [ST=0] MHz, Pixel Clock, PIXS 10pF [5pF] [4.9] RCIL Time ST=1 [ST=0] MHz, Pixel Clock, PIXS 10pF [5pF] [6.7] THSC Link disabled (HSYNC inactive) SCDT TFSC Link enabled (HSYNC active) SCDT high TPDL Delay from high impedance outputs Notes:
Units
Jitter estimated triggering digital scope rising input clock, measuring peak peak time spread rising edge input clock after trigger. Actual jitter tolerance higher depending frequency jitter. Output clock duty cycle independent differential input clock duty cycle IDCK duty cycle. setup hold timing data controls measured relative rising edge.
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201C
SiI/DS-0005-C
Data Mapping
Name CDATA0 CDATA1 CDATA2 CDATA3 CDATA4 CDATA5 CDATA6 CDATA7 CDATA8 CDATA9 CDATA10 CDATA11 CDATA12 CDATA13 CDATA14 CDATA15 CDATA16 CDATA17 CDATA18 CDATA19 CDATA20 CDATA21 CDATA22 CDATA23 CDATA24 CDATA25 CDATA26 CDATA27 CDATA28 CDATA29 CDATA30 CDATA31 CDATA32 CDATA33 CDATA34 CDATA35 CDATA36 CDATA37 CDATA38 CDATA39 CDATA40 CDATA41 CDATA42 CDATA43 CDATA44 CDATA45 CDATA46 CDATA47 18-bpp 1-pixel/clock 24-bpp 1-pixel/clock 36-bit 2-pixel/clock 48-bit 2-pixel/clock B0/E B1/E B2/E B3/E B4/E B5/E B6/E B7/E G0/E G1/E G2/E G3/E G4/E G5/E G6/E G7/E R0/E R1/E R2/E R5/E R4/E R5/E R6/E R7/E B0/O B1/O B2/O B3/O B4/O B5/O B6/O B7/O G0/O G1/O G2/O G3/O G4/O G5/O G6/O G7/O R0/O R1/O R2/O R3/O R4/O R5/O R6/O R7/O
B0/E B1/E B2/E B3/E B4/E B5/E
G0/E G1/E G2/E G3/E G4/E G5/E
R0/E R1/E R2/E R5/E R4/E R5/E
B0/O B1/O B2/O B3/O B4/O B5/O
G0/O G1/O G2/O G3/O G4/O G5/O
R0/O R1/O R2/O R3/O R4/O R5/O
Legend
Channel, GREEN Channel, BLUE Channel. EVEN (first) pixel data (P0, etc.) (second) pixel data (P1, etc.)
Assumptions PanelLink connected Bits mapped MSB:LSB. Tx0/Rx0 transmits BLUE data. Tx1/Rx1 transmits GREEN data. Tx2/Rx2 transmits data
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201C
SiI/DS-0005-C
Input Timing
Vertical Input Timing TVFP
VSYNC1
TVBP
HSYNC1
TVBLANK
Invalid data
Clock Timing Detail
TDES TDEH
L[VR-2] L[VR-1] L[0] L[1]
Last Line data First Line data DCLK
1/FC
Horizontal Input Timing THFP
HSYNC
THBP
IDTA
THCS THCH
HSYNC
THBLANK
IDTA[24]
P[HR-2]
P[HR-1]
Invalid
P[0]
P[1]
P[2]
P[3]
Last pixel line
First pixel line
Figure Input Timing Diagram
Signal DCLK
VSYNC
HSYNC
IDATA
Parameter Pixel clock frequency time High Time Pulse width Vertical front porch Vertical back porch Pulse width Horizontal front porch Horizontal back porch IDATA setup time IDATA hold time HSYNC setup time HSYNC hold time setup time hold time
Symbol 1/TC TVFP TVBP THFP THBP THCS THCH TDES TDEH
Unit HSYNC HSYNC HSYNC DCLK DCLK DCLK
Note
Table Input Timing Table
Notes:
HSYNC VSYNC either polarity, their polarities independent each other. Actual times will decoding logic. assumed that input data latched falling edge ICK. Actual times will decoding logic. assumed that HSYNC latched falling edge ICK.
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201C
SiI/DS-0005-C
Output Timing
Timing Overview
Frame Start/End Timing Overview
VSYNC HSYNC CONV IDTA[23:0] [VR-2] [VR-1] Last Line Data INVALID DATA First Line Data
Figure General timing diagram frame start
SiI201 10pF (5pF)
Figure Digital output transition time
Figure 4:Receiver Clock Cycle/High/Low Times
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201C
SiI/DS-0005-C
DIFF=0V TCCS DIFF=0V
Figure 5:Channel-to-Channel Skew Timing
CDATA
Figure Output Data Setup/Hold Times ODCK
CDATA, RCK, CCK, RIN, CIN,
Figure Output Signals Disabled Timing from Active
SCDT
SCDT
Figure SCDT Timing from Inactive/Active
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Silicon Image, Inc.
201C
SiI/DS-0005-C
CCK/CIN/CDTA Timing
CCK/CIN/CDATA Timing
CK_B CK_P CK_D CK_B CK_P CK_B CK_P CK_D CK_B CK_P [24] CDAT [48] INVALID DATA [0,1] [2,3] [4,5] INVALID DATA asserted cycle before first valid data load pixel/clock output mode. PIX_O pixel/clock output mode. PIX_O
First pixel(s) line "i".
Figure CCK/CIN/CDTA Timing Diagram
Notes: blanked (controlled) clock mode, there four extra load clock cycles data load period. These provide "dummy" load cycles column drivers that require internal pipelines emptied proper operation.
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Silicon Image, Inc.
201C
SiI/DS-0005-C
CONV/POL Timing
CONV/POL Timing
HSYNC ICLK CV_P CONV CV_P
Figure CONV/POL Timing Diagram
Signal CONV
Parameter CONV start time CONV pulse width start time
Symbol
Value 4*TSYNC TSYNC TSYNC TCD+TCW+4*TSYNC
Program CV_W CV_W PL_T PL_T
Note
Table CONV/POL Timing Table
Notes: time TSYNC varies according setting SCALE_IN input. SCALE_IN=0, TSYNC SCALE_IN=1, TSYNC 2*TC
Some column drivers that support on-chip inversion schemes require wide conversion pulse. setting input CV_W HIGH state, conversion pulses greater than width obtained. output signal used control polarity switching. Programming input PL_T sets polarity signal switch before after conversion pulse, shown above.
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201C
SiI/DS-0005-C
Polarity Inversion Timing
Polarity Inversion Timing
VSYNC HSYNC Even Frame Frame Last Line First Line
Figure Polarity Inversion Timing Diagram
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201C
SiI/DS-0005-C
CONV Timing
CONV Timing
HSYNC
CONV TOFF
Column
Figure CONV Timing Diagram
Signal
Parameter clock pulse width. time. TOFF approximately time between when next selected when column data allowed change.
Symbol TOFF
Value 255* TSYNC 64*TSYNC 80*TSYNC 96*TSYNC 112*TSYNC 128*TSYNC 176*TSYNC 240*TSYNC Reserved
blank time.
TSYNC TSYNC 112* TSYNC 128* TSYNC
Program ROFF_T ROE_T
Note
Table CONV Table
Notes: time TSYNC varies according setting SCALE_IN input. SCALE_IN=0, TSYNC SCALE_IN=1, TSYNC 2*TC
TOFF time from when next selected when column changes (CONV). Input signal ROFF_T[2:0] used program delay.
pulse width ROE. most drivers when HIGH output select signals LOW. width this blank period controlled with ROE_T[1:0].
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Silicon Image, Inc.
201C
SiI/DS-0005-C
Mode
When (W48) HIGH, mode asserted data path output. With asserted, 201C outputs pixels clock cycle. this mode, some programming pins (CK_P, DINV, PIX_O, CK_D, CK_T, CV_W, CD_E) longer accessible because they used output extra bits data (also Configuration Description table page 16). internal state these programming pins mode shown table below.
Name PIX_0 CK_D CK_T CV_W
Description Column Shift Register Start Output Drive Strength Output Pixel Select Dual Edge Clocking Column Clock Timing Conversion Pulse Width
State During Mode PIX_0 CK_D CK_T CV_W
Description State pulse always output clock cycle before first data load, even when low. Output drive strength high pixels output clock Dual edge clocking Clock data setup hold timings symmetrical Conversion pulse width narrow
Table Programming Values During Mode
mode, programming CV_P (CONV Pulse Polarity) selects Clock Inversion mode latch data rising falling clock edge) Data Inversion mode. table below describes CV_P configures these modes. CONV Pulse Polarity Setting CV_P CONV positive polarity NEC/TI mode Data Latching Edge Data Inversion Mode
Output data latched rising clock edge
Output data inverted
CV_P CONV negative polarity Output data latched falling clock edge Output data inverted Vivid mode Note: mode, CV_P selects NEC/TI mode. CV_P selects Vivid mode.
Table CONV Pulse Polarity Configuration Clock Data Inversion
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Silicon Image, Inc. Output Description Name Type CDTA47 CDTA46 CDTA45 CDTA44 CDTA43 CDTA42 CDTA411,2 CDTA401,2 CDTA39 CDTA38 CDTA37 CDTA36 CDTA35 CDTA34 CDTA331,2 CDTA321,2 CDTA31 CDTA30 CDTA29 CDTA28 CDTA27 CDTA26 CDTA251,2 CDTA241,2 CDTA23 CDTA22 CDTA21 CDTA20 CDTA19 CDTA18 CDTA171,2 CDTA161,2 CDTA15 CDTA14 CDTA13 CDTA12 CDTA11 CDTA10 CDTA91,2 CDTA81 CDTA7 CDTA6 CDTA5 CDTA4 CDTA3 CDTA2 CDTA11 CDTA01,2
201C
SiI/DS-0005-C
Description Output Data/Programming pins 47-0. Output data synchronized with output data clock (CCK). "Data Mapping" table pixel data mapped 24/36/48 mode. Notes: Only available data output HIGH. This data shared with programming pin, programming accessible when LOW.
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201C
SiI/DS-0005-C
Output Description (continued) Name Type Description Column driver load clock. Valid column driver data (CDTA) loaded this clock into column drivers. This clock programmable. Column shift register start bit. CD_E low, this signal starts loading column shift registers. mirroring enabled (CD_E=1), will output column shift register start when CTL1=0, will tri-stated when CTL1 CTL1/CIN2. CONV Column transfer signal. This signal used transfer data column driver storage registers driver's analog outputs. clock. Each rising edge shifts shift register bit. shift register start bit. Provides input shift register start vertical scan. Output enable drivers. most drivers, when outputs enabled, when high outputs held low. polarity control signal. This signal controls polarity switching circuits that minimize bias across liquid crystal. /POL Inverted control signal. This only accessible when LOW. CTL1/CDIR General output control signal mirroring enabled (CD_E=1), CTL1 dynamically selects direction column driver shift register alternately sending shift register output between outputs CIN2. CTL1 output then used direction input column drivers. W48=1 mode, VSYNC signal comes this pin. CTL2/CIN2 General output control signal mirroring enabled (CD_E=1) CIN2 will output column driver start when CTL1=1, will tri-stated when CTL1=0.
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Silicon Image, Inc. Configuration Description
Name Type Description
201C
SiI/DS-0005-C
ROFF_T[2] ROFF_T[1] ROFF_T[0] ROE_T[1] ROE_T[0] PL_T
Timing. Selects time interval between clock column output transitions. Output Enable Pulse. Selects time that output blanked. Polarity Timing. polarity toggled before CONV signal asserted. high polarity toggled after CONV pulse. This only accessible when LOW. When HIGH, this internally LOW. Output data inversion. When this tied output data (CDTA) bits inverted. When tied HIGH output data inverted. This only accessible when LOW. When HIGH, this internally HIGH. Output drive strength. When this tied sets data clock outputs 201C drive strength. When tied high, outputs maximum drive strength. This only accessible when LOW. When HIGH, this internally HIGH. Output Pixel Select option. level indicates that output data pixel (24-bits) clock high level indicates pixels (36/48-bits) clock. This only accessible when LOW. When HIGH, this internally HIGH. Select output mode. When this data output mode. this mode many programming pins accessible. When this HIGH data path output. this mode programming pins that were previously accessible their default state. "Section 3.6: Mode." Output Clock Polarity. CK_P output clock latches data negative edge, CK_P output data latched positive edge. This only accessible when LOW. When HIGH, this internally LOW. Output Clock Blank enable. high output clock blanked between valid data loads. Dual Edge Clocking. When this signal HIGH column clock latches column data both clock edges, halving frequency column clock. This only accessible when LOW. When HIGH, this internally LOW. Column Clock Timing. When this signal output setup hold time nearly symmetric. When HIGH, minimum hold time long. This only accessible when LOW. When HIGH, this internally LOW. Conversion Pulse Width. CONV pulse minimum width, high conversion pulse maximum width. This only accessible when LOW. When HIGH, this internally LOW. Conversion Pulse Polarity. conversion pulse active high, high conversion pulse active low. Enable Software Mirroring. low, software switching disabled. high direction column driver loading according state CTL1 SiI100 transmitter. This only accessible when LOW. When HIGH this internally LOW. Timing Scale. SCALE_IN low, preset timing registers scaled. SCALE_IN high timing registers scaled factor two.
DINV
PIX_O
CK_P
CK_B CK_D
CK_T
CV_W
CV_P CD_E
SCALE_IN
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201C
SiI/DS-0005-C
Power Management Description Name Type Description SCDT Sync Detect. Output high HSYNC active. HSYNC signal detected then SCDT driven low. SCDT externally connected PD/O pin. this configuration, data (CDTA[47:0]), general output control signals, column outputs driven when SCDT low. Power Down mode (active low). high level indicates normal operation level indicates power down mode. During power down mode, data (CDTA[47:0]), general output control signals, column outputs driven low. internal clock also stopped analog logic powered down. This effective during both normal operation test modes. Output driver Power Down mode (active low). high level indicates normal operation level indicates output driver power down mode. During power down mode, data (CDTA[47:0]), general output control signals, column outputs driven low. operation SCDT signal verified, PD/O externally connected SCDT. this configuration, data (CDATA[47:0]), general output control signals, column outputs driven when SCDT low. Differential Signal Data Description
Name Type Description
RX0+ RX0RX1+ RX1RX2+ RX2RXC+ RXCEXT_RES
Analo
voltage swing differential input data pairs.
Analo Analo
voltage swing differential input clock pair. Impedance Matching Control. Resistor value should times characteristic impedance cable. common case transmission line, external resistor must connected between AVCC this pin.
Reserved Description
Name Type Description
RESERVED RESERVED RESERVED
This should left unconnected. connected, must connect HIGH. This should left unconnected when LOW. connected, must connect LOW. This signal must tied high (3.3V) normal operation. This should left unconnected.
RESERVED
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Silicon Image, Inc. Power Ground Description
Name Type Description
201C
SiI/DS-0005-C
AVCC AVCC AGND AGND PVCC PGND OVCC OVCC OVCC OGND OGND OGND
Power Ground Power Ground Power
Receiver Analog VCC. Receiver Analog GND. Analog VCC. Analog GND. Core VCC. This supplies power input buffers core digital logic must
Ground
Digital
Power
Ground
Output VCC. This OVCC supplies power output buffers input protection devices. This must output signals output signals Output GND. This OGND output buffers input protection devices. This OGND separated from digital isolating noisy output from clean core digital GND.
Application Information obtain most updated Application Notes other useful information your design application, please visit Silicon Image site www.siimage.com, contact your local Silicon Image sales office.
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Silicon Image, Inc. Package Dimensions
100-pin TQFP Package Dimensions
Lead Length 1.00mm
201C
SiI/DS-0005-C
100-pin Plastic TQFP
Lead Width 0.22mm
Lead Pitch 0.50mm
Body Size 14.00mm
Device Date Code-wf# Rev. Country Origin back side
SiINNNCTNNN LNNNNN.NLLL XXYY-XX X.XX
Package Height 1.00mm max.
Clearance 0.15mm max. Body Size 14.00mm Footprint 16.00mm
Body Thickness 1.00mm
Copyright Notice
This manual copyrighted Silicon Image, Inc. reproduce, transform other format, send/transmit part this documentation without express written permission Silicon Image, Inc.
Trademark Acknowledgment
Silicon Image, Silicon Image logo, PanelLink, PanelLink Digital logo trademarks registered trademarks Silicon Image, Inc. other trademarks properties their respective owners.
Disclaimer
This document provides technical information user. Silicon Image, Inc. reserves right modify information this document necessary. customer should make sure that they have most recent data sheet version. Silicon Image, Inc. holds responsibility errors that appear this document. Customers should take appropriate action ensure their products does infringe upon patents. Silicon Image, Inc. respects valid patent rights third parties does infringe upon assist others infringe upon such rights.
1999 Silicon Image, Inc. 3/99 Si,/DS-0005-B
Silicon Image, Inc. 1060 Arques Ave. Sunnyvale, 94086
Tel: 408-616-4000 Fax: 408-830-9530 E-Mail: salessupport@siimage.com Web: www.siimage.com www.panellink.com
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Footprint 16.00mm
PanelLink

201C Intelligent Panel Controller (IPC) uses PanelLink Digital technol

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