uses PanelLink Digital technology support displays ranging from High R

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uses PanelLink Digital technology support displays ranging from High R

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PanelLink Digital Receiver
uses PanelLink Digital technology support displays ranging from High Refresh (25-86 MHz), which ideal desktop monitor applications. With flexible single dual pixel interface selectable output drive, receiver supports true color panels bit/pixel, 16.7M colors) pixel/clock mode bit/pixel pixel/clock mode). PanelLink also features inter-pair skew tolerance full input clock cycle highly jitter tolerant design. Since PanelLink products designed scaleable CMOS architecture support future performance requirements while maintaining same logical interface, system designers assured that interface will fixed through number technology performance generations. PanelLink Digital technology simplifies design resolving many system level issues associated with high-speed digital design, providing system designer with digital interface solution that quicker market lower cost.
Features
Scaleable Bandwidth: 25-86 (VGA High Refresh XGA) Power: 3.3V core operation power-down mode High Skew Tolerance: full input clock cycle (15ns MHz) Pin-compatible with SiI101 Sync Detect: Plug Display "Hot Plugging" Cable Distance Support: over with twisted-pair, fiberoptics ready Compliant with (DVI backwards compatible with VESA® DFP)
SiI141 Diagram
Functional Block Diagram
PIXS
24-bit Input Data 1-pixel/clock mode
8-bit Channel Data 1-pixel/clock 8-bit Channel Data 1-pixel/clock 8-bit Channel Data 1-pixel/clock
OCK_INV EXT_RES Termination Control 24/36
18-bit Even Data 2-pixel/clock mode
6-bit Channel Data 2-pixel/clock ODCK 6-bit Even Channel Data 2-pixel/clock 6-bit Even Channel Data 2-pixel/clock OGND OVCC
RX2+
6-bit Even Channel Data 2-pixel/clock
RX2-
DATA RECOVERY
CLT3 CLT2
Q[35:0/23:0] ODCK HSYNC
18-bit Data 2-pixel/clock mode
OGND 6-bit Channel Data 2-pixel/clock OVCC 6-bit Channel Data 2-pixel/clock
RX1+ RX1-
DATA RECOVERY
INTERCHANNEL SYNC.
PANEL INTERCLT1 FACE DECODER PLL_SYNC LOGIC
VSYNC
SCDT
OVCC CONTROL VSYNC OGND HSYNC CTL3 CTL2 CTL1 SCDT PIXS OGND RESERVED GENERAL PURPOSE CONTROL
RX0+ RX0DATA RECOVERY
VSYNC HSYNC
CLT1 CLT2 CLT3
SiI141
80-Pin TQFP
(Top View)
RXC+ RXCPLL
RESERVED
DIFFERENTIAL SIGNAL
OCK_INV
AGND
AGND
EXT_RES
AVCC
AVCC
PGND
RXC+
PVCC
RX2+
RX1+
RX0+
RXC-
RX2-
RX1-
RX0-
MISC.
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Absolute Maximum Conditions
Note:
SiI141
SiI/DS-0004-D
Permanent device damage occur absolute maximum conditions exceeded. Functional operation should restricted conditions described under Normal Operating Conditions. Symbol Parameter Units Supply Voltage 3.3V -0.3 Input Voltage -0.3 VCC+ Output Voltage -0.3 VCC+ Ambient Temperature (with power applied) TSTG Storage Temperature Package Power Dissipation
Normal Operating Conditions
Symbol Parameter Supply Voltage VCCN Supply Voltage Noise Ambient Temperature (with power applied) Note: Guaranteed design. 3.00 Units mVP-P
Digital Specifications
Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage VCINL Input Clamp Voltage -18mA VCIPL Input Clamp Voltage 18mA VCONL Output Clamp Voltage -18mA VCOPL Output Clamp Voltage 18mA Input Leakage Current Note: Guaranteed design. -0.8 IVCC -0.8 OVCC Units
Specifications
Under normal operating conditions unless otherwise specified. drive strength values, when ST=0, shown brackets. Symbol Parameter Conditions Units IOHD Output High Drive VOUT ST=1 10.3 17.6 Data Controls ST=0 2.51 5.15 IOLD Output Drive VOUT ST=1 -5.5 -8.3 -11.2 Data Controls ST=0 -2.8 -4.2 -5.6 IOHC ODCK High Drive VOUT ST=1 10.1 20.6 35.1 ST=0 10.3 17.6 IOLC ODCK Drive VOUT ST=1 -11.1 -16.7 -22.4 ST=0 -5.5 -8.3 -11.2 Differential Input Voltage 1000 Single Ended Amplitude Power-down Current IPDL Output leakage current ground high impedance mode (PD, LOW) ICCR Receiver Supply Current CLOAD 10pF DCLK=86MHz, 1-pixel/clock mode REXT_SWING Typical Pattern CLOAD 10pF DCLK=86MHz, 1-pixel/clock mode REXT_SWING Worst Case Pattern Notes: transmitter must power-down mode, powered off, disconnected current under this maximum. worst case power consumption. Typical Pattern contains gray scale area, checkerboard area, text. Black white checkerboard pattern, each checker pixel wide.
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Specifications
SiI141
SiI/DS-0004-D
Under normal operating conditions unless otherwise specified. drive strength values, when ST=0, given below. Symbol Parameter Conditions TDPS Intra-Pair Differential Input Skew pixel clock TCCS Channel Channel Differential Input Skew pixel clock TIJIT Worst Case Differential Input Clock Jitter tolerance MHz, Pixel Clock MHz, Pixel Clock DLHT Low-to-High Transition Time: Data Controls 10pF, ST=1 5pF, ST=0 ODCK 10pF, ST=1 5pF, ST=0 DHLT High-to-Low Transition Time: Data Controls 10pF, ST=1 5pF, ST=0 ODCK 10pF, ST=1 5pF, ST=0 TSOF Data/Control Setup Time ODCK falling (OCK_INV=0): 10pF, ST=1 MHz, Pixel Clock, PIXS 5pF, ST=0 MHz, Pixel Clock, PIXS 10pF, ST=1 5pF, ST=0 THOF Data/Control Hold Time ODCK falling (OCK_INV=0): 10pF, ST=1 MHz, Pixel Clock, PIXS 5pF, ST=0 MHz, Pixel Clock, PIXS 10pF, ST=1 5pF, ST=0 RCIP ODCK Cycle Time pixel/clock) 11.6 FCIP ODCK Frequency pixel/clock) RCIP ODCK Cycle Time pixels/clock) 23.3 FCIP ODCK Frequency pixels/clock) RCIH ODCK High Time 10pF, ST=1 MHz, Pixel Clock, PIXS 5pF, ST=0 MHz, Pixel Clock, PIXS 10pF, ST=1 5pF, ST=0 RCIL ODCK Time 10pF, ST=1 MHz, Pixel Clock, PIXS 5pF, ST=0 MHz, Pixel Clock, PIXS 10pF, ST=1 5pF, ST=0 THSC Link disabled inactive) SCDT Link disabled power down) SCDT TFSC Link enabled active) SCDT high TPDL Notes:
Units
Falling edges
Delay from high impedance outputs Jitter defined Specification, Section Jitter Specification. Jitter measured with Clock Recovery Unit Specification, Section Electrical Measurement Procedures. Output clock duty cycle independent differential input clock duty cycle IDCK duty cycle. setup hold timing data controls relative ODCK rising edge (OCK_INV=1) design same falling edge timing. Measured when transmitter powered down (see SiI/AN-0005 "PanelLink Basic Design /Application Guide," Section 2.4).
Timing Diagrams
SiI141 10pF (5pF) DLHT
DHLT
Figure Digital Output Transition Times
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SiI141
SiI/DS-0004-D
RCIP RCIH
RCIL
Figure Receiver Clock Cycle/High/Low Times
VDIFF=0V TCCS VDIFF=0V
Figure Channel-to-Channel Skew Timing
Output Timing
TSOF Q[35:0], VSYNC, HSYNC, CTL[3:1]
ODCK
THOF
Figure Output Data Setup/Hold Times ODCK
Q[35:0],DE, VSYNC,HSYNC, CTL[3:1]
TPDL
Figure Output Signals Disabled Timing from Active
THSC
SCDT
TFSC
SCDT
Figure SCDT Timing from Inactive/Active
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Output Description
Name SiI141 Diagram Type
SiI141
SiI/DS-0004-D
ODCK
HSYNC VSYNC CTL1 CTL2 CTL3
Description Output Data [35:0]. Output data synchronized with output data clock (ODCK). When PIXS Q35-Q24 Q23-Q0 output 24-bit/pixel data. When PIXS high Q17-Q0 output even numbered pixels (pixel etc.) Q35-Q18 output numbered pixels (pixel etc.). Refer Signal Mapping (SiI/AN-0008) DSTN Signal Mapping (SiI/AN-0007) application notes which tabulate relationship between input data transmitter output data from receiver. level will output drivers into high impedance (tri-state) mode. weak internal pull-down device brings each output ground. Output Data Clock. level will output drivers into high impedance (tri-state) mode. weak internal pull-down device brings each output ground. Output Data Enable. level will output drivers into high impedance (tri-state) mode. weak internal pull-down device brings each output ground. Horizontal Sync output control signal. Vertical Sync output control signal. General output control signal This controlled PDO. General output control signal General output control signal level will output drivers into high impedance (tri-state) mode. weak internal pull-down device brings each output ground.
Configuration Description
Name OCK_INV Type Description ODCK Polarity. level selects normal ODCK output, which enables data latching falling edge. high level (3.3V) selects inverted ODCK output, which enables data latching rising edge. Both conditions color panel support. color 24-bit DSTN panel support, please refer DSTN Signal Mapping (SiI/AN-0008-A) application note. Pixel Select. level indicates that output data pixel 24-bit) clock high level (3.3V) indicates that output data pixels 36-bit) clock. Output Data Format. This controls clock data output format. level indicates that ODCK runs continuously color panel support high level (3.3V) indicates that ODCK stopped (LOW) color 24-bit DSTN panel support when low. Refer Signal Mapping (SiI/AN-0007-A) DSTN Signal Mapping (SiI/AN-0008-A) application notes table DSTN panel support. Output Driver Strength. level indicates drive. high level indicates high drive.
PIXS
Power Management Description
Name SCDT Type Description SyncDetect. high level output when toggling. level output when inactive. Power Down (active low). high level (3.3V) indicates normal operation level indicates power down mode. During power down mode internal circuitry powered down digital same when asserted. (see description). Power Down Output (active low). high level indicates normal operation. level puts output drivers only into high impedance (tri-state) mode. weak internal pull-down device brings each output ground. There internal pull-up resistor that defaults chip normal operation left unconnected. SCDT CTL1 tri-stated this pin.
Differential Signal Data Description
Name RX0+ RX0RX1+ RX1RX2+ RX2RXC+ RXCEXT_RES Type Analog Description TMDS Voltage Differential Signal input data pairs.
Analog Analog
TMDS Voltage Differential Signal input clock pair. Impedance Matching Control. Resistor value should times characteristic impedance cable. common case transmission line, external resistor must connected between AVCC this pin.
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Reserved Description
Name RSVD RSVD Type
SiI141
SiI/DS-0004-D
Description This signal must left unconnected. This must tied high.
Power Ground Description
Name Type Power Description Core VCC, must 3.3V.
Ground
Digital GND.
OVCC
Power
Output VCC, must 3.3V.
OGND
Ground
Output GND.
AVCC AGND PVCC PGND
Power Ground Power Ground
Analog VCC, must 3.3V. Analog GND. VCC, must 3.3V. GND.
Application Information obtain most updated Application Notes other useful information your design application, please visit Silicon Image site www.siimage.com, contact your local Silicon Image sales office.
Ordering Information Part Number: SiI141CT80
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Package Dimensions
80-pin TQFP Package Dimensions
Lead Length 1.00mm
SiI141
SiI/DS-0004-D
80-pin Plastic TQFP
Lead Width 0.22mm
Lead Pitch 0.50mm
Body Size 12.00mm
Device Date Code Rev.
SiI141CT80 LNNNNN.NLLL XXYY X.XX
Package Height 1.0mm max.
Clearance 0.15mm max. Body Size 12.00mm Footprint 14.00mm
Body Thickness 1.0mm
Copyright Notice
This manual copyrighted Silicon Image, Inc. reproduce, transform other format, send/transmit part this documentation without express written permission Silicon Image, Inc.
Trademark Acknowledgment
PanelLink PanelLink Digital logo registered trademarks Silicon Image, Inc. Silicon Image, Silicon Image logo TMDS trademarks Silicon Image, Inc. VESA registered trademark Video Electronics Standards Association. TMDS licensed trademark VESA. other trademarks property their respective holders.
Disclaimer
This document provides technical information user. Silicon Image, Inc. reserves right modify information this document necessary. customer should make sure that they have most recent data sheet version. Silicon Image, Inc. holds responsibility errors that appear this document. Customers should take appropriate action ensure their products does infringe upon patents. Silicon Image, Inc. respects valid patent rights third parties does infringe upon assist others infringe upon such rights.
Ordering Information
Part Number: SiI141CT80
1999 Silicon Image, Inc. 7/99 SiI/DS-0004-D
Silicon Image, Inc. 10131 Bubb Road Cupertino, 95014
Tel: 408-873-3111 Fax: 408-873-0446 E-Mail: salessupport@siimage.com Web: www.siimage.com www.panellink.com
Footprint 14.00mm
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