Field-Programmable Microcontroller Peripherals with Flash Memory Embed
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PSD813FN/FH
Field-Programmable Microcontroller Peripherals with Flash Memory Embedded MicroCells
PSD813FH PSD813FN devices field-programmable microcontroller (MCU) peripherals with Flash memory. These multi-chip modules (MCM) first members complete family in-system-programmable (ISP) peripherals from that enhance embedded microcontroller design. These devices will interface easily with most popular MCUs enable simple two-chip solution that addresses virtually MCUs external needs. Major features provided PSD813FH/FN large Flash memory, concurrent boot memory, battery backed SRAM, programmable I/O, programmable logic, address space expansion, power management, code security, small package size. two-chip solution consisting PSD813FN/FH reduces design manufacturing cost, reduces board space, lowers power consumption, shortens time-to-market while increasing design flexibility. addition, in-system features such concurrent Flash read write capability, dynamically reconfigurable ports, power management increases system performance manufacturing flexibility. innovative "microcontroller-macrocells", called MicroCellsTM, bring inexpensive programmable logic MCU-based embedded system designs. Because MicroCells directly connected address/data bus, their programmable logic tightly coupled software with hardware overhead. MCU's ability communicate directly with MicroCells flip-flop level makes PSD813FN/FH devices ideal popular functions such counters, serial channels, mailboxes. When compared industry standard CPLD implementation, this architecture save CPLD product term macrocell resources. PSD813FN/FH devices first WSI's Flash PSD8XXF product family. Starting with PSD813FN/FH, pin-for-pin upgrade path exists future lower cost monolithic PSD8XXF devices that will incorporate expanded Flash-based programmable logic, Flash EEPROM memory types, larger SRAM, serial using industry standard JTAG protocol.
Features
5-volt only Flash Programmable Peripheral Microcontroller-based
Applications
Solves Problems In-System Flash Erase Programming
Concurrently Operating Main Memory Boot Memory Resolves Microcontroller Decoding Issues During Flash Update
separate non-volatile memory arrays.
Both Mbit (128 Kbytes) Flash memory Kbits Kbytes) Separate Boot EPROM memory available. Boot memory allows continuous operation while Flash memory being written erased. Flash memory divided into eight Kbyte sectors that mapped different address spaces. Access time which includes address latching DPLD decoding.
Embedded On-Chip Erase Program Algorithms Flash Memory.
Automatically accommodates on-chip events writing erasing Flash memory. Flash memory byte-programmable erased sector sector entire chip. embedded algorithms indicate completion program erase cycles using popular methods: data polling toggling. PSD813FN/FH algorithms compatible with standard JEDEC single-power-supply Flash command set.
Return Main Menu
PSD813FN/FH
Features
(cont.)
write inhibit Flash Memory. Guaranteed Minimum 10,000 Erase/Write Cycles. simple, programmable interface 8-bit microcontrollers using either multiplexed
non-multiplexed busses. interface logic directly decodes microcontroller control signals. Supports popular microcontrollers.
Three Flexible Sections
used internal address decoding, used external device address decoding, used general-purpose design resource. general-purpose used efficiently implement variety logic functions commonly associated with MCUs such state machines, address decoders, address generators, serial channels, multiprocessor mailboxes, shift registers. general-purpose also supports 12-Output MicroCells 23-Input MicroCells. PSD813FN/FH dedicates seven Output eight Input MicroCells Flash memory usage SRAM standby voltage control. Although seven Output MicroCells dedicated, internal product term allocator redistributes unused product terms needed remaining MicroCells.
Internal 4Kbit SRAM. SRAM retains data power lost automatically
switching external standby power source.
Nineteen individually configurable Port Pins. Ports used
microcontroller I/Os, I/Os, latched microcontroller address outputs special function I/Os.
programmable Power Management Unit (PMU) supports separate, low-power
modes allowing operations with little 25µA VCC). device automatically detect lack microcontroller activity into power down mode.
Page Logic
Page Logic connected ZPLDs enables address space expansion microcontrollers with limited address space capability. pages available.
Security
security prevents reading configuration, ZPLD, EPROM Boot array, Flash memory contents. This inhibits copying device programmer.
Development Tools
Supported PSDsoft MS-Windows® compatible development tools. Includes PSDabel design entry method, efficient Fitter, Address Translator (see Figure
Packaging consists plastic chip carrier.
Please refer revision block this document updated information.
PSD813FN/FH
PSD813FN/FH devices consist several major functional blocks. Figure shows architecture PSD813FN/FH device. functions each block described briefly following sections. Many blocks perform multiple functions, user configurable.
PSD813FN/FH Architectural Overview
PLDs
device contains three blocks each optimized different function shown Table functional partitioning PLDs reduces power consumption, optimizes cost/performance ease design entry. Decode (DPLD) used decode generate chip selects PSD813FN/FH internal memory, registers, peripheral mode. External Chip Select (ECSPLD) optimized generate chip selects devices external PSD813FN/FH. General Purpose (GPLD) implement user defined logic functions. DPLD ECSPLD have combinatorial outputs while GPLD Output MicroCells. Seven Port MicroCells dedicated Flash memory control. PSD813FN/FH also Input MicroCells that configured inputs PLD. PLDs receive their inputs from Input bus.
Ports
PSD813FN/FH pins divided among three ports. Each individually configured provide many functions. Ports configured standard ports, I/O, latched address outputs microcontrollers using multiplexed address/data busses.
Table Name
Decode External Chip Select General
Abbreviation
DPLD ECSPLD GPLD
Inputs
Outputs
Product Terms
PSD813FN/FH Architectural Overview
(cont.)
AD0-AD15
SRAM
DECODE PERIPHERAL SELECTS
INPUT
PORTS
INPUT
ADDRESS 8-BIT DATA /CONTROL EPROM
PAGE FOUR BLOCKS BATTERY BACK-UP
KBit EPROM
PSD813FN/FH
EMBEDDED ALGORITHM FLASH SECTORS COMMAND REGISTER
VSTDBY INCLUDING CMISER FEATURES (PC2)
DECODE
ADDRESS/DATA
BITS BATTERY BACK
PROGRAMMABLE PORT
PA0-PA7
Figure PSD813FN/FH Block Diagram
EXTERNAL
EXTERNAL CHIP SELECTS
CONTROL CHIP SELECT ALLOCATOR
CONTROL INTERFACE
PROGRAMMABLE PORT
PB0-PB7
DIRECT MICROCELLS ACCESS FROM DATA
GENERAL
ALLOC.
CLKIN
OUTPUT MICROCELLS
MICROCELL ALLOCATOR
PROGRAMMABLE PORT
PD0-PD2
SECURITY FEATURE
NIBBLE
INPUT MICROCELLS (PORT A,B,C)
PROGRAMMABLE PORT
PC0-PC1 PC3-PC7
DIRECT MICROCELL OUTPUT DATA OUTPUT MICROCELL FEEDBACK INPUT MICROCELL INPUT PORTS
(FLASH RDF, WRF, A14F, A16F A18F)
*Port dedicated Flash memory
VSTDBY.
PSD813FN/FH
PSD813FN/FH Architectural Overview
(cont.)
Microcontroller Interface
PSD813FN/FH easily interfaces with most popular eight sixteen-bit microcontrollers with either multiplexed non-multiplexed address/data busses. PSD813FH multiplexed applications PSD813FN non-multiplexed applications. PSD813FN/FH operate with 16-bit MCUs configured 8-bit external data path mode. device configured respond microcontroller control signals which also used inputs PLDs.
Memory
PSD813FN/FH contains Mbit Flash memory, Kbit Boot EPROM Kbit SRAM. EPROM space Flash memory space divided into four eight equally sized blocks, respectively. Each block located different address space defined user. access time either memory includes address latching DPLD decoding. Flash memory implemented using Mbit (29040) device configured Mbit memory. commands 29040 applicable operating Mbit Flash memory. Kbit SRAM used scratch memory extension microcontroller SRAM. SRAM data retained event system power down, provided backup battery connected Vstby (PC2). Switching from supply standby power occurs automatically when drops below Vstby voltage.
Page Register
four-bit Page Register expands address range microcontroller sixteen times. paged address used part address space access external memory peripherals internal EPROM, SRAM I/O.
Power Management Unit
Power Management Unit (PMU) PSD813FN/FH enables user control power consumption selected functional blocks based system requirements. includes Automatic Power Down unit (APD) that will turn device functions microcontroller inactivity modes: Power Down mode Sleep mode. Other power saving features, such CMiser PMU, allow EPROM/SRAM operate slower rate conserve power.
PSD813FN/FH
PSD813FN/FH devices supported Windows-based PSDsoft Development System. PSDsoft design flow shown Figure design entry done using PSDabel, which creates minimized logic implementation, provides logic simulation PLDs. PSD813FN/FH Interface Port configuration entered PSDconfiguration. PSDcompiler, comprised fitter address translator, generates object file from PSDabel, PSDconfiguration code files. object file then down loaded programmer (MagicPro III, Data I/O, other third party programmer device programming).
Development System
Figure PSDsoft Development Tools
PSDabel
DESCRIPTION GENERATE ABEL FILE DESIGN TEMPLATE
PSDconfiguration
CONFIGURE INTERFACE
PSDcompiler
FITTER FITTING ADDRESS TRANSLATOR EPROM MAPPING PROGRAM CODE FILE
THIRD PARTY PROGRAMMERS .OBJ FILE
PSDprogrammer
Magic Pro® PROGRAMMER CHIP PROGRAMMING
PSD813FN/FH Devices Table PSD813FN/FH Product Matrix
PSD813FN/FH unique devices. part classifications based mode. features each part listed Table
ZPLD DPLD GPLD ECSPLD Part
PSD813FH PSD813FN
x8/MUX x8/Non-MUX
Inputs
Registered Microcells
Flash Memory Pins
1024 1024
SRAM
Boot EPROM
NOTE: Power Management Unit.
PSD813FN/FH
following table describes names functions PSD813FN/FH. Pins that have multiple names and/or functions defined configuration.
Table PSD813FN/FH Descriptions
Name
ADIO0-7
30-37
Type
Function Description
Address/Data Port, interface Microcontroller Input pins multiplexed order address/data byte. latches address A0-7 input PLDs. drives data only read active internal functional blocks selected. Address Port, interface Microcontroller Address A8-15 inputs. Write Input with multiple configurations. Depending interface selected, this active write input read/write pin, write cycle Control signal (CNTL0) input Read Data Strobe Input with multiple configurations. Depending interface selected, this active read input clock input. During write cycle, high During read cycle, high high Data Strobe, active Control signal (CNTL1) input Read other Control input with multiple configurations. Depending interface selected, this PSEN Program Select enable, active code fetch cycle Control signal (CNTL2) input general input Active input. Resets Ports, MicroCells some Configuration Registers. Must active power Port This port configurable multiple functions: standard output input port External chip select (ECSPLD) output, input GPLD Latched address outputs (see Table Data Port (D0-3) non-multiplexed configuration Peripheral mode
A8-15 CNTL0 (WR, R_W)
39-46
CNTL1 (RD,
CNTL2 (PSEN)
Reset
PSD813FN/FH
Table PSD813FN/FH Descriptions
(cont.)
Name
Type
Function Description
Port This port configurable CMOS multiple functions: standard output input port Open GPLD MicroCell (McellAB) output input Drain Latched address outputs (see Table Data Port non-multiplexed configuration Peripheral mode Port This port configurable multiple functions: standard output input port External chip select (ECSPLD) output, input GPLD Latched address outputs (see Table
Port This port configurable multiple CMOS functions: standard output input port Open GPLD MicroCell (McellAB) output input Drain Latched address outputs (see Table Flash Write Flash Read Flash Address Flash Address Flash Address Flash Address Flash Select Port PC2. Dedicated SRAM Standby Voltage Input. should grounded Vstby required. Port configured input latches addresses ADIO0 pins GPLD input ECSPLD output Port configured GPLD input External chip select (ECSPLD) output CLKIN clock input clock input GPLD MicroCells, power down counter GPLD Array
(WRF) (RDF) (A14F) (A16F) (A17F) (A18F) (CFS) (Vstby)
(ALE)
(CLKIN)
*These pins reserved internal Flash memory control should used outputs.
PSD813FN/FH
Table PSD813FN/FH Descriptions
(cont.)
Name
(CSI)
Type
Function Description
Port configured GPLD input External (ECSPLD) output input When low, enables EPROM/SRAM. When high, EPROM/SRAM disabled conserve power Power pins
Ground pins
Table Port Latched Address Output Assignments* Microcontroller
8-Bit Multiplexed 8-bit Non-Multiplexed
Applicable
Port (3:0)
Address [3:0]
Port (7:4)
Address [7:4]
Port (3:0)
Address [3:0]
Port (7:4)
Address [7:4]
Address [3:0]
Address [7:4]
Refer Port Section enable Latched Address Output function.
PSD813FN/FH
Table shows offset address PSD813FN/FH registers relative CSIOP base address. CSIOP space bytes address that allocated user internal PSD813FN/FH registers.
PSD813FN/FH Register Description Address Offset
Table Register Address Offset Register Name
Data Control Data
Port Port Port Port Other*
Description
Reads Port input, input mode Selects mode between Address Stores data output Port pins, output mode Configures Port input output Configures Port between CMOS, Open Drain Slew rate Reads Input MicroCell Reads status output enable Port driver Read reads output MicroCells (McellC, McellAB) Write loads Microcell Flip-Flops
Direction Drive
Input MicroCell Enable
Output MicroCell
PMMR0 PMMR1 Page *Other registers that part ports.
Power Management Register Power Management Register Page Register 8031/PIO Configuration Register
PSD813FN/FH
PSD813FN/FH consists five major functional blocks:
PSD813FN/FH Functional Blocks
Block Interface Ports Memory Block Power Management Unit
functions each block described following sections. Many blocks perform multiple functions, user configurable.
PLDs
PLDs bring programmable logic functionality PSD813FN/FH. After specifying logic PLDs using PSDabel tool PSDsoft suite, logic configuration programmed into device available when power applied. PLDs (DPLD, ECSPLD GPLD) consist array. GPLD architecture includes Output MicroCells addition array. There Input MicroCells that configured inputs PLD. Figure shows organization PLDs. array used form product terms specified using PSDabel tool PSDsoft development system. When inputs used term true, output active. GPLD Input consists signals shown Table Both true complement value inputs available array. DPLD ECSPLD Input Busses consists fewer inputs subset inputs.
Table GPLD Inputs Input Source
Address Control Signals Reset Power Down Ports Inputs (Input MicroCells) Port Inputs Page Register Port MicroCell Feedback Port MicroCell Feedback
Input Name
[15:0] CNTL [2:0] [7:0], [7:0] [7:3], [1:0] [2:0] [3:0] MCELLAB.FB [7:4] MCELLC.FB [7:0]
Number Signals
PLDs
(cont.)
INPUT
PORTS
DECODE
EPROM SELECTS (CSBOOT FLASH BLOCK SELECTS SRAM SELECT (RS0) CSIOP SELECT (CSIOP) PERIPHERAL SELECTS (PSEL 0-1)
PSD813FN/FH
Figure Block Diagram
EXTERNAL
CHIP SELECT ALLOCATOR EXTERNAL CHIP SELECTS PORT DIRECT MICRO CELL ACCESS FROM DATA
GENERAL
NIBBLE ALLOC.
OUTPUT MICROCELL
MICROCELL ALLOCATOR MCELL PORT MCELL PORT
INPUT MICROCELL (PORT A,B,C)
DIRECT MICROCELL ACCESS FROM DATA OUTPUT MICROCELL FEEDBACK, INPUT MICROCELL INPUT PORTS PORT INPUTS
PSD813FN/FH
Each three PLDs unique characteristics suited applications. They described following sections.
PLDs
(cont.)
Decode
Decode (DPLD), shown Figure used select internal PSD813FN/FH functions: Flash blocks, EPROM blocks, SRAM, Registers (CSIOP) Port Peripheral Mode. select signals active high have product term. CSIOP select line PSD813FN/FH internal registers that occupies bytes memory space. second level decoder selects register based address inputs A[7-0]. Each Flash memory sector chip select. Kbyte Flash memory partitioned into eight Kbyte blocks, each with decoded select line (FS0-FS7). Kbyte boot memory partitioned into four Kbyte blocks, each with decoded select line (CSBOOT0-CSBOOT7). PSEL used inputs Port control port's Peripheral mode operation. Usually PSEL defined term address inputs. This mode explained Port section.
Table DPLD Inputs Input Source
Address Ports Port Page Register Control Signal Reset
Input Name
A[15:0] [7:0], [7:0] [7:3], [1:0] [3:0] CNTL1 (Read)
Number Bits
PLDs
(cont.)
CSBOOT BOOT EPROM BLOCK SELECTS CSBOOT (INPUTS) (23) FCS0
PSD813FN/FH
Figure DPLD Logic Array
PORTS (PORT A,B,C)
PGR0 -PGR3
FLASH BLOCK SELECTS (16)
A[15:0]
READ
FCS7
CNTL1
RESET
CSIOP PSEL0 SELECT DECODER SELECT PERIPHERAL MODE SELECT PSEL1
PSD813FN/FH
PLDs
(cont.)
External Chip Select
External Chip Select (ECSPLD) provides means select external devices. output buffer ECSPLD configured operate high slew rate writing corresponding Drive Register. slew rate measurement rise fall times output. higher slew rate means faster output response while lower slew rate slower response. Refer Table Section setting Drive Register. Faster transitions more likely cause line reflections system noise than slower rates. Adjusting slew rate allows trade-off between greater speed noise sensitivity. selection should based performance requirements system noise characteristics. corresponding bits Drive Register (for normal speed) (for fast drive). default value zero. ECSPLD inputs shown Table outputs combinatorial, either polarity, have product term each shown Figure
Table ECSPLD Inputs Input Source
Address Control Signals Power Down Signal Page Register
Input Name
A[15:0] CNTL[2:0] PDN* PGR[3:0]
Number Bits
*APD output. When high, PSD813FN/FH power down mode
seven ECSPLD outputs driven device through Ports shown Table MicroCell Allocator. Port selection specified PSDabel file assigned PSDcompiler.
Table ECSPLD Output Port Assignments ECSPLD Output
ECS0 ECS1 ECS2 ECS3 ECS4 ECS5 ECS6
Port Assignments
PA0, PA1, PA2, PA3, PD0* PD1* PD2*
*Port output enable (.oe) product terms ECS4-6 outputs.
PSD813FN/FH
PLDs
(cont.)
Figure ECSPLD Logic Array
ECS0 (INPUTS) 15:0] (16) POLARITY ECS1 PGR[ 3:0] POLARITY
CNTRL 2:0] READ/WRITE CONTROL SIGNALS OUTPUT ECS6
POLARITY
General
General (GPLD) used implement system logic such loadable counters, system mailboxes handshaking protocols. addition, GPLD implement random logic state machine functions. GPLD Output Input MicroCells (see Figure MicroCells configured using PSDsoft development system. Like other PLDs, GPLD array which generate product terms, maximum nine product terms each twelve MicroCells. Input Output MicroCells connected PSD813FN/FH internal data directly accessed microcontroller. This enables software load data into Output MicroCells read data from both Input Output MicroCells with overhead visible user. This feature allows efficient implementation system logic eliminates need connect data logic array required most standard macrocell architectures. Pins also driven outputs directly using Mode (see page 32). user drives pins with Mode, underlying output MicroCell used embedded nodes.
PLDs
(cont.)
PRODUCT TERMS FROM OTHER MICRO CELLS
ADDRESS DATA CONTROL OTHER PORTS
GPLD OUTPUT MICROCELL PORTS
LATCHED ADDRESS DATA PRESET PRODUCT TERM ALLOCATOR LOAD DATA WRITE CONTROL
INPUT
PRODUCT TERMS MICRO CELL
Figure GPLD Port
GPLD OUTPUT
ARRAY
GPLD OUTPUT COMB. SELECT INPUT D/T/JK SELECT CLOCK GLOBAL CLOCK SELECT
POLARITY SELECT
CLOCK SELECT CLEAR
MICRO CELL PORT ALLOCATOR (MCELL ONLY)
INPUT
OUTPUT ENABLE (OE) MICRO CELL FEEDBACK PORT INPUT
INPUT MICROCELLS
INPUT LATCH GATE/CLOCK
PSD813FN/FH
PSD813FN/FH
PLDs
(cont.)
Output MicroCell
Eight Output MicroCells connected Port pins (except PC2) named McellC0-7. remaining four MicroCells connected Port Port named McellAB4-7. McellAB output assigned specific PSDabel, MicroCell Allocator will assign either Port Table shows MicroCells Port assignment. Seven output MicroCells dedicated controlling Flash memory this multi-chip module.
Table Output MicroCell Port Data Assignments Native Product Terms
Output Port MicroCell Assignment
McellC0 McellC1 McellC2 McellC3 McellC4 McellC5 McellC6 McellC7 McellAB4 McellAB5 McellAB6 McellAB7 Port Port
Borrowed Product Terms
Data Loading Reading PSD8XXF 8-Bit Mode Assignment
Port Port Port Port Port Port Port Port Port
A14F A16F A17F A18F
**Internal node only. **General purpose use.
Product Term Allocator
MicroCells have same cell architecture except McellC0-McellC7 have four native product terms McellAB4-McellAB7 have three native product terms. GPLD also Product Term Allocator with which PSDcompiler automatically borrow product terms from MicroCell another. McellC borrow five product terms from other MicroCells total nine product terms. McellAB three native product terms borrow product terms. Borrowing allows MicroCell outputs needing more product terms unused product terms others transparent user. architecture Output MicroCells, shown Figure consists native product terms borrowed product terms from other MicroCells. polarity product term input controlled gate. MicroCell implement either sequential logic, using Flip-Flop element, combinatorial functions. multiplexor selects combinatorial sequential logic MicroCell output. multiplexor output drive Port also feedback path array inputs.
Micro Cell Flip-Flop Type
Flip-Flop MicroCell configured Toggle, type using PSDabel PSDsoft. flip-flop Clock, Preset Clear inputs driven from product term array. Alternatively, device clock input (CLKIN) used flip-flop. Preset Clear active high inputs; Flip-Flop clocked rising edge clock input.
PSD813FN/FH
PLDs
(cont.)
Loading Reading Micro Cells
GPLD MicroCells occupy memory location address space defined CSIOP (refer section). Flip-Flops each MicroCells loaded from data microcontroller write cycle MicroCell (see Port section MicroCell Addresses). data that associates with MicroCell will load Flip-Flop, data will load Flip-Flop. loading cycle takes priority over other Flip-Flop inputs that include Preset, Clear clock. Table data bits that connected MicroCells. ability load flip-flops read them back useful such applications loadable counters, shift registers, mailboxes handshaking protocols.
Table MicroCell Flip-Flop Loading
Normal Flip-Flop Function
NOTE: when writes MicroCell address
Output Enable
MicroCell connected PSD813FN/FH output. output enable each Port output driver controlled single product term (.oe) from array ORed with Direction Register output. Upon power output enable (.oe) equation defined declared output PSDsoft, enabled. MicroCell output declared internal node Port output PSDabel file, then Port used other functions (such mode). internal node feedback routed input array.
Input MicroCell
Input MicroCell shown Figure used latch, register pass incoming Port signals prior driving them onto Input bus. outputs these MicroCells also read microcontroller through internal Data Bus. GPLD Input MicroCells, each Ports (except PC2). Input MicroCells individually configurable. enable/clock latch flip-flop driven multiplexor whose inputs product term from GPLD array address strobe (ALE). Each product term output used latch/clock four Input MicroCells. Port inputs [3:0] controlled product term [7:4] controlled another one. Input MicroCell configurations specified equations written PSDabel. Outputs MicroCells read microcontroller "Input MicroCell" buffer. Port section read MicroCells. Input MicroCells latch higher address bits (A31 A16). latched addresses routed inputs. Input Micro-Cell particularly useful handshaking communication applications where processors wish pass data between each other through commonly accessible storage. Figure shows typical configuration where Master writes Port Data Register that read Slave activation "Slave-Read" output enable product term. Slave write Port Input MicroCells activating "Slave- product term. Master then read Input MicroCells. "Slave-Read" "Slave-Wr" signals product terms that derived from Slave inputs Slave_CS.
PLDs
(cont.)
PSD813FN/FH
PSD813FN/FH
SLAVE SLAVE READ PORT DATA REGISTER GPLD 7:0] PORT
SLAVE
MCU-RD
MASTER 7:0]
MCU-WR
SLAVE PORT INPUT MICRO CELL
Figure Handshaking Communication Using Input MicroCells
PSD813FN/FH
"No-glue Logic" PSD813FN/FH Microcontroller Interface directly connected most popular microcontrollers their control signals. Some these microcontrollers with their types control signals shown Table interface type specified using PSDsoft tools.
Interface
Table Microcontroller Busses Control Signals
8031 68330 80198 68HC11 80C251*** Neuron 3150
Data
CNTL0
CNTL1
CNTL2
PSEN
PD0**
ADIO0
PSEN
***Not used CNTL2 configured GPLD input. Other used pins (CNTL2, PD0) configured ***for other functions. ***ALE/AS input optional microcontrollers with non-multiplexed bus. ***8051 compatible mode only.
Table shows names PSD813FN/FH interface control pins their functions. control pins have multiple functions configured interface many microcontrollers. Depending microcontroller, some control input pins required used GPLD input other functions. Specific examples interfaces different microcontrollers provided following sections. microcontrollers that have more than address lines, Port pins used additional address inputs
PSD813FN/FH
Interface
(cont.)
PSD813FH Interface Multiplexed
Figure shows example system using microcontroller with multiplexed PSD813FH. ADIO port PSD813FH connected directly microcontroller address/data bus. multiplexed only byte (eight-bit data) both bytes (sixteen-bit data). latches address lines internally; latched addresses brought Port PSD813FH drives ADIO data only when internal resources accessed input active.
Figure
Example Typical 8-Bit Multiplexed Interface
(OPTIONAL)
PORT
PORT
(OPTIONAL)
PSD813FH
(CNTRL1) (CNTRL2)
(CNTRL0)
PORT
(PD0)
7:0]
15:8]
PORT RESET
ADIO PORT
MICRO CONTROLLER
PSD813FN/FH
Interface
(cont.)
PSD813FN Interface Non-Multiplexed
Figure shows example system using microcontroller with non-multiplexed PSD813FN. address connected ADIO Port, data connected Port (D[7:0]). data Ports tri-state mode when PSD813FN accessed microcontroller. Should system address exceed sixteen bits, Port used additional address inputs.
Figure
Example Typical Non-Multiplexed Interface, 8-Bit Data
PORT
7:0]
PORT
(OPTIONAL)
23:16]
PSD813FN
(CNTRL2)
(CNTRL0)
(CNTRL1)
PORT
(PD0)
ADIO PORT
15:0]
7:0]
PORT RESET
MICRO CONTROLLER
PSD813FN/FH
Interface
(cont.)
Microcontroller Interface Examples
Figures show examples basic connections between PSD813FN/FH some popular microcontrollers. PSD813FN/FH control input pins labeled microcontroller function which they configured. interface specified using PSDsoft tools. should grounded Vstby used.
80C31
Figure shows interface 80C31 which 8-bit multiplexed address/data bus. lower address byte multiplexed with data bus. microcontroller signals used accessing internal SRAM Ports while PSEN signal used read EPROM. input (Port PD0) latches address. Refer Memory Section additional 80C31 operating modes.
68HC11
Figure shows interface 68HC11 where PSD813FH configured 8-bit multiplexed mode with settings. ECSPLD generate READ signals external board devices. CNTL2 used used input.
80C251
Intel 80C251 microcontroller features user-configurable interface with possible configurations shown Table
Table 80C251 Configurations Configuration 80C251 Read/Write Pins
PSEN PSEN only
Connecting PSD813FN/FH Pins
CNTL0 CNTL1 CNTL2 CNTL0 CNTL1
Page Mode
Non-Page Mode, 80C31 compatible [7:0] multiplex with [7:0} Non-Page Mode [7:0] multiplex with [7:0}
Configuration 80C31 compatible. interface PSD813FH identical that shown Figure There only read input (PSEN) connected CNTL1 PSD813FH. connection allows larger address input PSD813FH.
(cont.)
Interface
7:0]
80C31
EA/VP RESET INT0 INT1 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN ALE/P PSEN ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7
PSD813FH
RESET
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
CNTL0 (WR) CNTL1(RD) CNTL2 (PSEN) PD0-ALE
Figure Interfacing PSD813FH with 80C31
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
RSTIN
(Vstby) RESET
RESET
PSD813FN/FH
**If used, must grounded. **Reserved internal Flash memory control.
(cont.)
PSD813FN/FH
Interface
AD[7:0] AD[7:0]
PSD813FH 68HC11
RESET XIRQ MODB CNTL0 CNTL1(E) CNTL PD0-AS RSTIN ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7
RESET
Figure Interfacing PSD813FH with 68HC11
MODA
(Vstby)
**If used, must grounded. **Reserved internal Flash memory control.
RESET
PSD813FN/FH
There four programmable ports: Ports bits, Port seven bits Port three bits. ports configured function different modes operation. Each port individually configurable allowing single port perform multiple functions. configuration defined either using PSDsoft tools microcontroller writing on-chip registers.
Ports
General Port Architecture
general architecture Port shown Figure Individual Port diagrams shown Figures will discussed section below. PSD813FN/FH configured non-multiplexed mode, Port and/or Port connected data available general purpose ports. shown Figure port pins contain output multiplexer whose selects driven configuration defined PSDabel Control Registers. Inputs multiplexer include following: Output data from Data Register output mode Latched address outputs GPLD MicroCell output ECSPLD external chip select output ECSPLD external chip select output
above inputs also connected Port Data Buffer (PDB) feedback Internal Data that read microcontroller. three-state buffer operating like multiplexer that allows only source read time. also inputs from Direction Register, Control Register direct port input (Data Port pin's tri-state output driver enable controlled input gate whose inputs come from GPLD array Enable product term (.oe) Direction Register. enable product term array output defined, then Direction Register sole control buffer. Refer Tables direction port configured.
Table Port Direction Control, Output Enable P.T. Defined Direction Register Port Mode
Input Output
Table Port Direction Control, Output Enable P.T. Defined Direction Register Output Enable P.T.* Port Mode
*Port does have output enable P.T. register contents altered microcontroller. feedback path allows microcontroller check contents registers. Ports have embedded Input MicroCells which configured latch, register direct input GPLD. latch register clocked address strobe product term from GPLD array. output from Input MicroCell drives input read microcontroller. Refer Input MicroCell description section. Port additional logic (not shown Figure that enables operate Peripheral mode when Register set. Input Output Output Output
INTERNAL DATA
DATA REG. DATA LATCHED ADDRESS OUTPUT PORT READ DATA OUTPUT SELECT
(cont.)
Ports
PSD813FN/FH
MUXED ADDRESS/DATA
MICRO CELL OUTPUTS
Figure General Port Architecture
EXT.CS
CONTROL REG. REG. ENABLE
ENABLE PRODUCT TERM (.OE) INPUT MICRO CELL
GPLD INPUT
PSD813FN/FH
Ports
(cont.)
Port Operating Modes
Ports have several modes operation shown Table Some modes selected using PSDabel tool programmed into device using Non-Volatile Memory (NVM) that active when power applied cannot altered unless device reprogrammed. mode defined PSDsoft, then other modes microcontroller writing Port configuration registers Run-Time. I/O, Data Port Address Input modes configurations. other modes initiated microcontroller. modes selected, port altered dynamically between Address modes writing Control Register. Each eight-bit Control Register store "1", setting respective port I/O, "0", setting Address Out. Direction Register output enable product term determine input output. Table summarizes operating modes ports. functions available every port. Table shows where different modes configured.
Table Port Operating Modes Port Mode
McellAB Outputs McellC Outputs ECSPLD Outputs ZPLD Inputs Address Address Data Port Open Drain Slew Rate Peripheral
Port
PA7- (PA7 (PA3
Port
(A7-
Port
Port
Configured Run-Time
(PB7 (PB3
Reserved Flash Memory Control Plus VSTBY
PSD813FN/FH
Ports
(cont.)
Port Operating Modes (cont.) Table Port Operating Mode Settings Defined PSDabel
Declare pins only
Mode
Control Direction Defined Register Register Register PSDconfiguration Setting Setting Setting
output, input (Note (Note (Note
Data Port (Port A,B) Address (Port A,B) Address (Port A,B,C)
Logic equations Declare pins only Logic equation Input MicroCells
Specify type
Peripheral Logic equations (Port (PSEL0 Applicable
NOTE direction Port pins controlled Direction Register ORed with individual output enable product term (.oe) from GPLD array.
Mode
mode uses port input GPLD Input MicroCell, and/or output from GPLD, ECSPLD. Port assignments shown Tables output tri-stated with control signal defined product term (.oe) from PLD, setting zero Direction Register. Direction Register must defined input pin. mode specified PSDabel declaring port pins, then writing equation assigning port.
Mode
Mode microcontroller uses PSD813FN/FH ports expand ports. ports PSD813FN/FH mapped into microcontroller address space. addresses ports listed Table port will into mode writing zero corresponding Control Register. direction changed writing Direction Register port where makes output input. output enable product term also change direction (see Table 15). When configured output, content Data Register drives pins. input mode, microcontroller reads port input through Data buffer Ports have Control Register mode default pins that configured I/O.
Address Mode
microcontrollers with multiplexed address/data bus, ports Address mode drive latched addresses external devices. Address [7:0] always assigned Port Table address output assignments Ports Direction Register Control Register must port pins using Address mode. non-multiplexed mode, address[7:0] available Port Address Mode.
PSD813FN/FH
Ports
(cont.)
Port Operating Modes (cont.) Address Mode
microcontrollers that have more than address lines, higher addresses connected Port address input latched Input MicroCell ALE. input that included DPLD equations Flash, Boot, EPROM considered address input.
Data Port Mode
Port used data port microcontroller with non-multiplexed address/data bus. Data Port connected data microcontroller. general functions disabled Port port configured Data Port. Figure
Peripheral Mode
Only Port supports Peripheral mode whereby Port serves tri-stateable bi-directional data buffer microcontroller's data bus. Peripheral mode enabled setting Register "1". Figure shows that when Peripheral mode enabled either PSEL0 PSEL1 from DPLD active, Port acts bi-directional buffer microcontroller D[7:0] data bus. buffer tri-stated when PSEL active. Peripheral mode used interface with external peripherals. PSDabel write equations that contain keyboards PSEL0 PSEL1.
Open Drain/Slew Rate Mode
Ports (pins PA7-4) (pins PB7-4) (except PC2) configured open drain instead CMOS outputs. Open Drain configuration useful sinking large currents operate LEDs, example. Open Drain mode enabled writing corresponding Drive Register. Port (PA3-0), Port (PB3-0) Port configured ECSPLD outputs that have high slew rate. high slew rate enabled writing corresponding Drive Register.
Figure Port Peripheral Mode
PSEL0
PSEL1 DATA
REGISTER
PSD813FN/FH
Ports
(cont.)
Port Registers
Each port registers used configuration (PCR, Port Configuration Registers) data transfers (PDR, Port Data Registers). contents registers accessed microcontroller through normal read/write cycles addresses given Table address registers comprised that CSIOP output from DPLD plus address offset listed tables. pins port individually configurable each register controls respective pin. example, register refers port. three Port Configuration Registers, shown Table used setting port configuration. Each register zero power
Table Port Configuration Registers Register Name
Control Direction Drive*
Port
A,B,C,D A,B,C,D
Access
Write/Read Write/Read Write/Read
*Note: Table Drive Register definition.
Control Register
Control Register sets Port Port sets Port Address mode. default mode I/O.
Direction Register
Controls direction data flow Ports. configures port output, input. configuration read from Direction Register. default mode input. shown Figure direction data flow Port pins also controlled output enable (.oe) product term from GPLD array. product term active, Direction Register sole control direction. example configuration port with three least significant bits output remainder input shown Table Port register only three least significant bits active.
Table Port Direction Assignment Example
PSD813FN/FH
Ports
(cont.)
Port Registers (cont.) Drive Register
Drive Register configures driver Open Drain, case ECSPLD outputs, sets operate high slew rate. external pull-up resistor required when slew rate mode. Ports register sets different functions lower higher nibbles. four upper bits corresponding bits CMOS ("0") Open Drain ("1") driver. four lower bits used slew rate control. slew rate measurement rise fall times output. higher slew rate means faster output response while lower slew rate slower, lower slope, response. operates high slew rate when corresponding Drive Register "1". Table shows Drive Registers Port which Open Drain Slew Rate configuration.
Table Drive Register Assignment
Drive Register Port Port Port Port Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Slew Rate Slew Rate Open Drain Slew Rate Slew Rate Slew Rate Slew Rate Slew Rate Open Drain Slew Rate Slew Rate Slew Rate Open Drain Slew Rate
NOTE: Applicable, should "0".
*Port pins dedicated Flash memory control this multi-chip module product.
PSD813FN/FH
Ports
(cont.)
Port Data Registers
Port Data Registers, shown Table used microcontroller write read data from ports. Table shows register name, ports having each register type microcontroller access each register. registers described below.
Table Port Data Registers Register Name
Data Data Output MicroCell Input MicroCell Enable
Port
A,B,C,D A,B,C,D A,B,C A,B,C A,B,C
Access
Read input Write/Read Feedback Read outputs MicroCells Write loading MicroCells Flip-Flop Read outputs Input MicroCells Read output enable control port driver
Data
Port pins connected directly Data buffer. input mode, input read through Data buffer. always read state Port using this method, regardless what driving pin.
Data Register
Stores output data written output mode. contents Register driven pins Direction Register product term "1". contents register also read back microcontroller.
Output MicroCell
GPLD Output MicroCells occupy location microcontroller's address space. microcontroller read output MicroCells. Writing MicroCell loads data MicroCell Flip-Flops. Refer section more detail.
Input MicroCell
Input MicroCells used latch store external inputs. outputs Input MicroCells routed input also read microcontroller. Refer section detail description.
Enable
Enable buffer allows microcontroller read outputs "OR" gate that enable input port output driver. indicates driver output mode, indicates driver tri-state input mode.
PSD813FN/FH
Ports
(cont.)
Port Data Registers (cont.) Register Address Offset
base address Registers defined CSIOP equation that occupies bytes address space defined user PSDsoft. lower address byte A[7:0], address offset, selects register. Table shows address offset MCUs except those Motorola microcontrollers with 16-bit data bus. example, when CSIOP defined occupy address range 1000h 10FFh PSDabel, address Port Control Register then 1002h.
Table Register Address Offset (relative CSIOP) Register Name
Data Control Data Direction Drive Input MicroCell Enable Output MicroCell
Port
Port
Port
Port
Port Functionality Structure
Port have similar functionality structure shown Figure ports configured perform more following functions: Mode GPLD Output MicroCells McellAB[7:4] connected Port PA[7:4} Port PB[7:4]. ECSPLD Output External chip select output connected either Port PA[3:0] Port PB[3:0]. Latched Address output Provide latched address output Table Address Additional high address inputs using Input MicroCells. Open Drain/Slew Rate pins PA[3:0] PB[3:0] configured Open Drain Mode pins PA[7:4] PB[7:4] configured fast slew rate Data Port Port D[7:0} non-multiplexed Peripheral Mode Port only
Table Port Latched Address Output Assignments Microcontroller
8-Bit Multiplexed (PSD813FH) 8-Bit Non-Multiplexed (PSD813FN)
Applicable.
Port (3:0)
Address (3:0)
Port (7:4)
Address (7:4)
Port (3:0)
Address (3:0)
Port (7:4)
Address (7:4)
Address (3:0)
Address (7:4)
INTERNAL DATA
DATA REG. DATA ADDRESS OUTPUT ADDRESS 7:0] A[15:8] PORT MCELL 7:4] ECS[3:0] READ DATA CONTROL REG. REG. ENABLE PRODUCT TERM (.OE) INPUT MICRO CELL ENABLE OUTPUT SELECT
(cont.)
Ports
Figure Port Structure
PSD813FN/FH
GPLD -INPUT
PSD813FN/FH
Ports
(cont.)
Port Functionality Structure
Port pins configured mode Flash memory controls (except PC2). other Port functions disabled (multi-chip module only). Vstby A14F A16F A17F A18F Flash Memory Write Signal Flash Memory Read Signal SRAM Vstby Flash Address Flash Address Flash Address Flash Address Flash Chip Select
Port dedicated Vstby SRAM battery backup used other functions.
Port Functionality Structure
Port only three pins, does support Address mode, Control Register required. Port configured perform more following functions: Mode ECSPLD Output External chip select output Input direct input PLD, Input MicroCells Slew rate pins fast slew rate Port pins configured PSDsoft input pins other dedicated functions: ALE, address strobe input CLKIN, clock input MicroCells Flip-Flops counter CSI, active chip select input. high input will disable EPROM/SRAM.
INTERNAL DATA
DATA REG. DATA PORT OUTPUT MCELL 7:0] READ (ALL PORT PINS DEDICATED FLASH MEMORY CONTROL MULTI-CHIP MODULE) OUTPUT SELECT DATA
(cont.)
Ports
Figure Port Structure
PSD813FN/FH
ENABLE
REG. ENABLE PRODUCT TERM (.OE) INPUT MICRO CELL
GPLD- INPUT
(cont.)
Ports
DATA REG. DATA PORT OUTPUT ECS[ 6:4] READ
Figure Port Structure
DATA
INTERNAL DATA
OUTPUT SELECT
REG. GPLD INPUT
PSD813FN/FH
PSD813FN/FH
PSD813FN/FH multi-chip module that includes PSD6XX megabit Flash memory configured operate device. PSD813FN/FH includes Kbytes Boot EPROM; Flash provides Kbytes Flash memory. Boot EPROM used system boot storing Flash memory programming algorithm. Flash erase programming algorithms compatible SGS-Thomson Embedded Erase Programming AlgorithmTM. Flash memory erased programmed while microcontroller executing code from Boot EPROM. Chip selects memory blocks come from DPLD GPLD decoding logic defined user PSDsoft software. Figure shows organization Memory Block.
Memory Block
Boot EPROM
chip selects (CSBOOT0-3) Boot EPROM generated from DPLD address decoder. CSBOOT0-3 defined Kbyte boundaries should overlap Flash memory address space.
Flash Memory
Flash that used this Mbit Flash device only Mbit will addressed. Address lines inactive during Flash reads. This leaves address lines A16, A17, page through eight Kbyte sectors Flash memory. Each Kbyte sector Flash addressed address lines A0-A13. This Flash paging simplified configuration DPLD GPLD. FS0-7 chip selects each block that defined DPLD Kbyte boundaries. designer custom configure Flash addressing schemes equations developed PSDsoft. internal Page register very effective this application. Figure Table NOTE: Unlike Flash reads, whenever embedded Flash algorithms exercised (write, erase, etc), address line Flash enabled configured HDL) pass commands from Flash die. Address line Flash permanently grounded. Seven pins MicroCells PSD6XX reserved generation Flash memory control signals. address lines A14F, A16F, A17F, A18F, chip select generated based FS0-7 inputs GPLD. Refer Appendix operation programming algorithm Flash memory.
SRAM
SRAM Kbits memory, organized SRAM enabled chip select signal from DPLD. SRAM battery back-up (STBY) mode. This back-up mode automatically invoked when voltage drops under Vstdby voltage. Vstdby voltage connected only SRAM cannot lower than volts.
Memory Select
Boot EPROM, Flash memory, SRAM chip select equations defined ABEL file terms address other DPLD inputs. memory space Flash chip select (FS0-7) should larger than Flash block selecting. Boot EPROM block should larger than Kbytes. following rules govern PSD813F memory selects/space defined:
Flash blocks address space cannot overlap among blocks. Flash blocks address space cannot overlap Boot EPROM, SRAM
address space.
SRAM internal address space cannot overlap. SRAM internal space overlap Boot EPROM space, with priority given
SRAM I/O. portion Boot EPROM which overlapped cannot accessed.
PSD813FN/FH
Memory Block
(cont.)
Figure PSD813FN/FH Memory Block
ADDRESS
A[14:0
CSBOOT A[15:0 PGR[3:0 DPLD CSIOP
BOOT EPROM
SRAM A[13:0 A[15:0 PGR[3:0 PSEN RESET GPLD A15F A14F A16F A17F A18F
DATA
FLASH D[7:0 MEMORY
Table Flash Memory Control Signals Signal Name
A14F A16F A17F A18F
Pin/Macrocell
Function
Write input Read input Flash memory input Flash memory input Flash memory input Flash memory input Flash memory select
Example Equations Based 8031
(!rd !psen); A14F PGR3 A16F FCS1 FCS3 FCS5 FCS7; A17F FCS2 FCS3 FCS6 FCS7; A18F FCS4 FCS5 FCS6 FCS7; !CSF FCS0 FCS1 FCS2 FCS3 FCS4 FCS5 FCS6 FCS7;
PSD813FN/FH
Memory Blocks
(cont.)
Memory Select 8031 Microcontrollers
8031 family microcontrollers have separate address space program memory (enabled PSEN) data memory (enabled RD). Normally, Boot EPROM would program address space SRAM would data address space. PSD813FN/FH allows Boot EPROM SRAM address space reside program space, data space both. This flexibility enables several system designs. example, user desires execute program that resides SRAM, SRAM would have occupy program address space (enabled PSEN). Likewise, user devote block Boot EPROM contain data lookup tables, requiring Boot EPROM occupy data address space (enabled RD). internal Boot EPROM SRAM each have their output enable. Combinations PSEN drive these output enables determined bits Run-Time register (see Table 25). schematic representation seen Figure action register shown. There four modes operation that selected Run-Time shown Table these modes assume there overlapping address assignments blocks Boot EPROM SRAM. These blocks memory reside same program data space, share physical addresses within 64K. Example Boot EPROM block SRAM cannot both start address 0000. Example Boot EPROM block program space Boot EPROM block data space cannot both start address 8000).
Separate Space Mode
Program memory space separate from data memory space. This default state ties Boot EPROM output enable PSEN only, ties SRAM output enable only.
Combined Program Space Mode
This mode allows SRAM reside program space enabled PSEN well RD).
Combined Data Space Mode
This mode allows Boot EPROM reside data space enabled well PSEN).
Combined Space Mode
This mode allows both Boot EPROM SRAM reside either program space data space (either memory accessed PSEN RD).
Table Register RD_EN
PSEN_EN
Run-Time Mode
Separate Space Mode (default reset) Combined Program Space Mode Combined Data Space Mode Combined Space Mode
NOTE: Bits used. described Peripheral mode section.
PSD813FN/FH
Memory Blocks
(cont.)
Memory Select 8031 Microcontrollers (cont.)
Mixed Mode another mode operation that Run-Time from device programming file that PSDsoft creates. This mode deals with overlapping Boot EPROM addresses such when Boot EPROM blocks start address 8000, program space other data space.
Mixed Mode
This mode allows individual Boot EPROM blocks with overlapping addresses configured either program space data space. CSBOOTx chip select equations overlapping blocks must qualified with 8031 input. active will select Boot EPROM blocks data space disable blocks program space. automatically PSDsoft keyword used CSBOOTx equation. This equivalent setting register, only there from system power-up. Here some example CSBOOTx equations: CSBOOT0 address ^h8000 address ^h1FFF "resides program space CSBOOT1 address ^h8000 address ^h1FFF !RD; "resides data space There reasons this mode. First, this mode must used Boot EPROM addresses overlap each other reside different spaces. Second, this mode used Boot EPROM block addresses overlap desired have more Boot EPROM blocks reside data space designer wants this configuration from power (not Run-Time). IMPORTANT: Boot EPROM blocks that reside data space, access time calculated from valid data valid. designer must ensure that EPROM access time sufficient system, else register without overlapping addresses.
PSD813FN/FH
Memory Blocks
(cont.)
Figure 8031 Memory Modes Separate Space Mode
CSBOOT DPLD
BOOT EPROM
SRAM
PSEN
Figure 80C31 Memory Mode Combined Space Mode
DPLD
CSBOOT
BOOT EPROM
SRAM
PSEN
PSD813FN/FH
PSD813FN/FH offers number configurable power savings options. designer choose wide array options that range from excellent power savings with performance loss maximum power savings expense slight performance loss. These power saving functions designed occur automatically background most Run-Time. Note that these features only apply PSD6XX portion this Multi-Chip Module. monolithic PSD8XXF members will apply these power reduction features sections well.
Power Management Unit
Automatic Power Down (APD) Mode
logic puts PSD813FN/FH into power savings mode monitoring activity address strobe (ALE/AS). unit down-counter that reset active state ALE/AS. Figure This counter clocked external free running clock signal that routed CLKIN (Port D-PD1). counter will reach terminal count after transitions CLKIN. ALE/AS active cycles CLKIN, counter will reach terminal count force Power Down Mode enabled. will come Power Down mode immediately after first active pulse ALE/AS with performance penalty. During Power Down mode, Boot EPROM, SRAM, interface disabled. GPLD ECSPLD sections operate normal during Power Down mode. Table shows effects Power Down mode I/O.
Table Power Down Effect Ports Port Function
Address Data Port Peripheral
Level
Change Change Undefined Hi-Z Tri-State Hi-Z Tri-State
functions enabled Run-Time using Power Management Mode Registers PMMR0 PMMR1 shown Table Figure shows typical flow mode setup. Power Down mode also achieved deasserting input described later.
Sleep Mode
Sleep Mode extension Power Down mode which provides maximum power savings expense small performance loss. Sleep mode enabled, Sleep mode will occur when Power Down mode occurs exit when Power Down mode exits. Sleep mode, GPLD ECSPLD still monitor inputs respond them, however, GPLD ECSPLD propagation delays extended PD4. When Sleep mode exited, GPLD ECSPLD will continue have extended delay "wake-up" period PD5. Also, first access Boot EPROM SRAM that occurs while coming sleep mode will incur extended access time LVDV1. After that, EPROM SRAM access times will normal. Sleep mode enabled Run-Time using Power Management Mode Register PMMR1 shown Table Figure also shows typical flow mode setup.
PSD813FN/FH
Power Management Unit
(cont.)
CMiser
CMiser function reduces power consumption Boot EPROM SRAM independent logic. When CMiser enabled, lowest level power consumed, however, Boot EPROM SRAM access times will extended additional Characteristics read timing specifications this document more details.
Input
Port configured PSDsoft chip select input CSI. configured such, will invoke Power Down mode described above) when level logical one. When logic zero, functions normally. function independent Run-Time power saving options. Power Down mode activated from CSI, exit from this mode identical Power Down mode activated logic.
Input Clock
configured CLKIN (Port PD1) array Output MicroCells, this clock signal disabled during Power Down mode further reduce power consumption. This feature enabled Run-Time using PMMR0 register shown Table Note that even when clock signal CLKIN blocked this feature, clock signal still active down-counter.
SRAM Standby Mode
SRAM dedicated VSTBY (Port PC2) that connected external battery. When system falls below battery voltage VSTBY pin, will automatically connect VSTBY power source SRAM. SRAM standby current (ISTBY) typically minimum data retention voltage volts. Note: should grounded used VSTBY.
Table Summary PSD813FN/FH Timing Standby Current During Power Down Sleep Mode
Propagation Delay
Normal (Note (Note
Mode
Power Down Sleep
Recovery Time Normal Operation
(Note
Access Time
Access Access
Access Recovery Time Normal Access
tLVDV tLVDV1
NOTES: Power Down does affect operation PLD. Sleep Mode input will have propagation delay PD4. recovery time normal operation after existing Sleep Mode. input during transition will have propagation delay PD5.
PSD813FN/FH
Power Management Unit
(cont.)
Figure Logic Block
PMMR0 POLARITY PMMR0 CLEAR LOGIC
SLEEP-EN PMMR1
SLEEP MODE EPROM SELECT
COUNTER EDGE DETECT POWER DOWN (PD) ZPLD SRAM SELECT
CLKIN
SELECT DISABLE EPROM/SRAM DISABLE INTERFACE
Figure Enable Power Down Flow Chart
RESET
DISABLED
POLARITY PMMR0
NEED SLEEP MODE
ENABLE SLEEP MODE PMMR1
ENABLE PMMR0
ENABLE PMMR0
DISABLE CLOCK PMMR0
DISABLE CLOCK PMMR0
IDLE CLKIN CLOCK PSD813FN/FH POWER DOWN MODE
IDLE CLKIN CLOCK PSD813FN/FH SLEEP MODE
PSD813FN/FH
Power Management Unit
(cont.)
Table Power Management Mode Registers (PMMR0, PMMR1)**
PMMR0
Mcell Array CMiser Enable Polarity high
**Bits used, should **Both PMMR0 PMMR1 register bits clear zero following power
Subsequent reset pulses will clear registers.
power down polarity power down polarity high Automatic Power Down (APD) disabled Automatic Power Down (APD) enabled EPROM/SRAM CMiser EPROM/SRAM CMiser CLKIN input array connected CLKIN input array disconnected CLKIN input MicroCells connected CLKIN input MicroCells disconnected
PMMR1
Sleep Mode Enable *Unused bits should Sleep Mode Disabled Sleep Mode Enabled
Table Counter Operation Enable
Polarity
Level
Pulsing Counting Counting
Counter
Counting (Generates after Clocks) Counting (Generates after Clocks)
PSD813FN/FH
Other Features
Page Register
four-bit Page Register increases addressing capability microcontroller factor contents Register also read microcontroller. outputs Page Register (PGR0-PGR3) inputs included Flash, Boot EPROM, SRAM chip select equations. Figure shows Page Register. four Flip-Flops Register connected internal data microcontroller write read from Page Register. Register operate independent register used general purpose logic page expansion needed.
Figure Page Register
RESET
D0-D3
PGR0 PGR1 PGR2 PGR3 GPLD ECSPLD DPLD RS0, CSBOOT0
PAGE REG.
Reset Input
PSD813FN/FH active reset input which loads internal configurations clear some registers. Figure shows reset timing requirement. active range minimum NLNH duration. After rising edge reset, PSD813FN/FH remains reset state during range. device must reset power-up prior use. IMPORTANT: must reset condition prior concurrent with coming reset. While reset input active, active outputs determined PSDabel equations. chip status during reset power down shown Table
PSD813FN/FH
Other Features
(cont.)
Table Chip Status During Reset Power Down Mode Port Configuration
Output Address Data Port Peripheral Input Active Tri-stated Tri-stated Tri-stated
Reset
Power Down Mode
Unchanged Depends inputs defined Tri-stated Tri-stated
Register
PMMR0 MicroCells Flip-Flop other registers
Reset
Cleared (power reset) Unchanged (warm reset) Unchanged* Cleared
Power Down Mode
Unchanged Unchanged* Unchanged
*The MicroCell Flip-Flop cleared reset input (Power Down) signal, depending
equations that defined PSDabel file.
Security Protection
PSD813FN/FH programmable security which acts duplication barrier. When set, contents Flash Boot EPROM, non-volatile configuration bits, PLDs cannot read device programmers. security through PSDsoft Software embedded compiled output file. security erasable secured windowed part erased re-programmed.
PSD813FN/FH
Absolute Maximum Ratings
Symbol
TSTG
Parameter
Storage Temperature
Condition
CLDCC PLDCC Commercial Industrial Military With Respect With Respect With Respect
Unit
Operating Temperature Voltage Programming Supply Voltage Supply Voltage Protection
>2000
NOTE: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure Absolute Maximum Rating conditions extended periods time affect device reliability.
Operating Range
Range
Commercial
Temperature
+70°C
Tolerance
Recommended Operating Conditions
Symbol
Parameter
Supply Voltage
Condition
Speeds
Unit
PSD813FN/FH
following tables describe AD/DC parameters PSD813FN/FH:
AC/DC Parameters
Electrical Specification Timing Specification
Timing
Combinatorial Timing Synchronous Clock Mode Asynchronous Clock Mode Input MicroCell Timing Microcontroller Timing Read Timing Write Timing Peripheral Mode Timing Power Down Reset Timing
Following some issues concerning parameters presented:
specification Supply Current given different modes operation.
Before calculating total power consumption, determine percentage time that PSD813FN/FH each mode. Also supply power considerably different CMiser "ON".
power component gives PLD, EPROM, SRAM mA/MHz specification. timing specification required time delay when CMiser "ON".
PSD813FN/FH
Versions)
Characteristics
Symbol
VIH1 VIL1 VHYS
Parameter
Supply Voltage High Level Input Voltage Level Input Voltage Reset High Level Input Voltage Reset Level Input Voltage Reset Hysteresis Output Voltage Output High Voltage Except VBATon, CEout SRAM Standby Voltage SRAM Standby Current Idle Current (VSTBY Pin) SRAM Data Retention Voltage Standby Supply Current Power Down Mode Sleep Mode
Conditions
Speeds (Note (Note
-0.5
Unit
0.01 0.15 4.49
0.45
VSBY ISBY IIDLE
VSBY Only VSTBY >VCC (Note >VCC (Note CMiser Selected
-0.1
µA/PT mA/MHz mA/MHz mA/MHz
Input Leakage Current Output Leakage Current Only
EPROM Adder
CMiser EPROM Selected Data Bus) CMiser
(DC) (Note
Operating Supply Current Flash Adder
During Flash Read, During Flash Erase/Write, SRAM Selected SRAM Adder CMiser SRAM Selected Data Bus) CMiser
(AC) EPROM SRAM Flash Adder
NOTES: Reset input hysteresis. VIL1 valid below .2VCC -.1. VIH1 valid above .8VCC. deselected internal active. Sleep mode internal active.
PSD813FN/FH
Versions)
PSD813FN/FH AC/DC Parameters GPLD ECSPLD Timing
GPLD ECSPLD Combinatorial Timing 10%)
Symbol
Parameter
ECSPLD Input ECSPLD Combinatorial Output GPLD Input Pin/Feedback GPLD Combinatorial Output Port GPLD Input Pin/Feedback GPLD Combinatorial Output Port GPLD Input ECSPLD Output Enable
Conditions
(Notes
Aloc
Slew Rate
Unit
(Note (Note (Notes (Notes (Notes (Notes (Notes (Notes MicroCell
GPLD Input GPLD Output Enable GPLD Input ECSPLD Output Disable
ARPW
GPLD Input GPLD Output Disable GPLD Register Clear Preset Delay GPLD Register Clear Preset Pulse Width GPLD Array Delay
NOTES: ECSPLD Input pins A(0:15), PGR(0:3), CNTL(0:2), PDN. ECSPLD Outputs PA(0:3), PB(0:3), PD(0:2). GPLD Inputs A(0:15), PGR(0:3), CNTL(0:2), PA(0:7), PB(0:7), PC(0:7), PD(0:2), ALE, PDN. 25ns propagation delay from RSTin pin. GPLD Outputs PA(4:7), PB(4:7), PC(0:7).
PSD813FN/FH
Versions)
PSD813FN/FH AC/DC Parameters GPLD ECSPLD Timing
GPLD MicroCell Synchronous Clock Mode Timing
Symbol Parameter
Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback CNT) Maximum Frequency Pipelined Data Input Setup Time Input Hold Time Clock High Time Clock Time Clock Output Delay GPLD Array Delay Minimum Clock Period
Conditions
1/(tS tCO) 1/(tS -10) 1/(tCH tCL) (Note (Note Clock Input Clock Input Clock Input MicroCell
25.00 31.25 35.71
Aloc
Slew Rate
Unit
GPLD MicroCell Asynchronous Clock Mode Timing 10%)
Symbol Parameter
Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback CNTA) Maximum Frequency Pipelined Data MINA Input Setup Time Input Hold Time Clock Input High Time Clock Input Time Clock Output Delay GPLD Array Delay Minimum Clock Period
Conditions
1/(tSA tCOA 1/(tSA tCOA-10) 1/(tCH tCL) (Note (Note (Note (Note (Note MicroCell fCNTA
21.74 27.78 35.71
Aloc
Slew Rate
Unit
NOTE: GPLD Inputs A(0:15), PGR(0:3), CNTL(0:2), PA(0:7), PB(0:7), PC(0:7), PD(0:2), ALE, PDN. 25ns propagation delay from RSTin pin.
PSD813FN/FH
Versions)
PSD813FN/FH AC/DC Parameters GPLD ECSPLD Timing
Input MicroCell Timing 10%)
Symbol
Parameter
Input Setup Time Input Hold Time Input High Time Input Time Input Combinatorial Output Delay
Conditions
(Note (Note (Note (Note (Note
Aloc
Unit
NOTES: Inputs from Port relative register/latch clock from PLD. latch timings refer tAVLX tLXAX.
PSD813FN/FH
Microcontroller Interface AC/DC Parameters
Versions)
Explanation Symbols Timing. Example:
AVLX Time from Address Valid Invalid.
Signal Letters
Address Input CEout Output Input Data Input Internal WDOG_ON signal Interrupt Input Input Reset Input Output Port Signal Output Output Data UDS, LDS, IORD, PSEN Inputs Chip Select Input Input Internal Signal Vstby Output Output MicroCell
Signal Behavior
Time Logic Level Logic Level High Valid Longer Valid Logic Level Float Pulse Width
PSD813FN/FH
Microcontroller Interface AC/DC Parameters
Read Timing
Symbol
LVLX AVLX LXAX AVQV SLQV RLQV RHQX RLRH RHQZ EHEL THEH ELTL AVPV
Parameter
Pulse Width Address Setup Time Address Hold Time Address Valid Data Valid Valid Data Valid Data Valid 8/16-Bit Data Valid 8-Bit Bus, 8031 Separate Mode Data Hold Time Pulse Width Data High-Z Pulse Width Setup Time Enable Hold Time After Enable Address Input Valid Address Output Delay
Conditions
CMiser
Unit
(Note (Note (Note
(Note (Note (Note (Note (Note (Note
NOTES:
timing same timing LDS, UDS, PSEN 8031 combined mode) signals. PSEN have same timing 8031 separate mode. input used select internal PSD813FN/FH function. multiplexed mode latched address generated from ADIO delay address output Port.
PSD813FN/FH
Microcontroller Interface AC/DC Parameters
Versions)
Write/Erase/Program Timing 10%)
Symbol
LVLX AVLX LXAX AVWL SLWL DVWH WHDX WLWH WHAX WHPV AVPV WHWH1 WHWH2
Parameter
Pulse Width Address Setup Time Address Hold Time Address Valid Leading Edge Valid Leading Edge Data Setup Time Data Hold Time Pulse Width Trailing Edge Address Invalid Trailing Edge Port Output Valid Address Input Valid Address Output Delay Byte Programming Operation Sector Erase Operation Time
Conditions
(Note (Note (Notes (Note (Note (Note (Note (Note (Note 8-Bit Data Mode (Note Also includes preprogramming time 100% tested
EPROM_CMiser
Unit
NOTE: input used select internal PSD813FN/FH function. multiplexed mode latched address generated from ADIO delay address output Port. timing same timing signals.
PSD813FN/FH
Microcontroller Interface AC/DC Parameters
Port Peripheral Data Mode Read Timing
Symbol
AVQV (PA) SLQV (PA) RLQV (PA) DVQV (PA) QXRH (PA) RLRH (PA) RHQZ (PA)
Parameter
Address Valid Data Valid Valid Data Valid Data Valid Data Valid 8031 Mode Data Data Valid Data Hold Time Pulse Width Data High-Z
Conditions
(Note
Unit
(Notes
(Note (Note (Note
Port Peripheral Data Mode Write Timing
Symbol
WLQV (PA) DVQV (PA) WHQZ (PA)
Parameter
Data Propagation Delay Data Port Data Propagation Delay Invalid Port Tri-state
Conditions
(Note (Note (Note
Unit
NOTES: input used select Port Data Peripheral Mode. Data already stable Port Data stable ADIO pins data Port
PSD813FN/FH
Microcontroller Interface AC/DC Parameters
Power Down Timing
Symbol
LVDV LVDV1 CLWH
Parameter
Access Time from Power Down Access Time from Sleep GPLD ECSPLD Propagation Delay Sleep Mode GPLD ECSPLD Recovery Time After Sleep Mode Maximum Delay from Enable Internal Valid Signal
Conditions
Unit
Using CLKIN Input
(µs)
Reset Timing
Symbol
NLNH
Parameter
RESET Active Time RESET High Operational Device
Conditions
Unit
PSD813FN/FH
Figure Read Timing
tAVLX ALE/AS tLVLX MULTIPLEXED ADDRESS NON-MULTIPLEXED DATA NON-MULTIPLEXED
tLXAX
ADDRESS VALID tAVQV ADDRESS VALID
DATA VALID
DATA VALID tSLQV
tRLQV (PSEN, (LDS, UDS) tRLRH tRHQZ tRHQX
tEHEL tTHEH tELTL
tAVPV ADDRESS
*tAVLX tLXAX required 80C251 Page Mode 80C51XA Burst Mode.
PSD813FN/FH
Figure Write Timing
tAVLX ALE/AS
LXAX
LVLX MULTIPLEXED ADDRESS VALID tAVWL ADDRESS NON-MULTIPLEXED DATA NON-MULTIPLEXED tSLWL tDVWH (DS) WLWH WHDX WHAX ADDRESS VALID DATA VALID DATA VALID
EHEL THEH WLMV tAVPV ADDRESS WHPV STANDARD ELTL
PSD813FN/FH
Figure Peripheral Read Timing
ALE/AS
ADDRESS
DATA VALID
tAVQV (PA) tSLQV (PA) tRLQV (PA) tRLRH (PA) tQXRH (PA) tRHQZ (PA)
tDVQV (PA) DATA PORT
Figure Peripheral Write Timing
ALE/AS
ADDRESS
DATA
tWLQV
(PA)
tWHQZ (PA)
tDVQV (PA) PORT DATA
PSD813FN/FH
Figure Combinatorial Timing
ECSPLD INPUT tPD1 EXTERNAL OUTPUT
GPLD INPUT tPD2 tPD3 GPLD OUTPUT
Figure Synchronous Clock Mode Timing
CLKIN
INPUT
REGISTERED OUTPUT
PSD813FN/FH
Figure Asynchronous Clock Mode Timing (Product-Term Clock)
tCHA
tCLA
CLOCK
INPUT tCOA REGISTERED OUTPUT
Figure Input MicroCell Timing (Product-Term Clock)
CLOCK
INPUT
OUTPUT
PSD813FN/FH
Figure Input Output Disable/Enable
INPUT
INPUT OUTPUT ENABLE/DISABLE
Figure Asynchronous Reset/Preset
tARPW
RESET/PRESET INPUT tARP REGISTER OUTPUT
PSD813FN/FH
Figure Reset Timing
NLNH
tOPR
Figure Switching Waveforms
WAVEFORMS INPUTS OUTPUTS
STEADY INPUT
STEADY OUTPUT
CHANGE FROM CHANGE FROM
WILL CHANGING FROM WILL CHANGING
DON'T CARE
CHANGING, STATE UNKNOWN
OUTPUTS ONLY
CENTER LINE TRI-STATE
PSD813FN/FH
Capacitance
Symbol
COUT CVPP
Parameter
Capacitance (for input pins only) Capacitance (for input/output pins) Capacitance (for WR/VPP R/W/VPP)
Conditions Typical Unit
VOUT
NOTES: These parameters only sampled 100% tested. Typical values 25°C nominal supply voltages.
Figure Testing Input/Output Waveform
3.0V TEST POINT 1.5V
Figure Testing Load Circuit
DEVICE UNDER TEST
2.01
(INCLUDING SCOPE CAPACITANCE)
PSD813FN/FH
PSD813FN/FH Assignments
52-Pin PLDCC
Assignments
52-Pin PLDCC
(CSF) (A18F) (A17F) (A16F) (A14F) (Vstby) (RDF) (WRF)
52-Pin PLDCC
Assignments
52-Pin PLDCC
CNTL0 CNTL2 CNTL1
PSD813FN/FH
PSD813FN/FH Package Information
Figure Drawing 52-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type
CNTL2 CNTL1 CNTL0
(CSF) (A18F) (A17F) (A16F) (A14F) (VSTBY) (RDF) (WRF)
PSD813FN/FH
Figure 37A. Drawing 52-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type
.025 .045
View
View
Family: Plastic Leaded Chip Carrier
Millimeters Symbol
020197R1
Inches Notes
0.165 0.100 0.144 0.013 0.026 0.0097 0.785 0.750 0.690 Reference 0.600 0.785 0.750 0.690 Reference Reference 0.600 0.050 0.795 0.754 0.730 Reference Reference
4.19 2.54 3.66 0.33 0.66 0.246 19.94 19.05 17.53 15.24 19.94 19.05 17.53 15.24 1.27
4.57 2.79 3.86 0.53 0.81 0.261 20.19 19.15 18.54 20.19 19.15 18.54
0.180 0.110 0.152 0.021 0.032 0.0103 0.795 0.754 0.730
Notes
Reference
PSD813FN/FH
Appendix Flash Memory
Description
PSD813FN/FH non-volatile Flash memory that erased electrically sector level, programmed Byte-by-Byte.
Organization
Flash Memory organization 512K bits (only 128K used) with Address lines Data Inputs/Outputs Memory control provided Chip Enable (CSF), Output Enable (RDF) Write Enable (WRF) Inputs. Erase Program performed using embedded algorithms through internal Program/Erase Controller (P/E.C.). Data Output bits provide polling toggle signals during Automatic Program Erase indicate Ready/Busy state internal Program/Erase Controller.
Sectors
Erasure memory sectors. There sectors bytes each memory address space. Erasure each sector takes typically seconds each sector programmed erased over 100,000 cycles. Sector erasure suspended, while data read from other blocks memory, then resumed.
Operations
Five operations performed appropriate cycles: Read Array, Read Electronic Signature, Output Disable, Standby, Write Command Instruction.
Command Interface
Command Bytes written Command Interface (C.I.) latch perform Reading (from Array Electronic Signature), Erasure programming. added data protection, command execution starts after command cycles. first, second, fourth fifth cycles used input code sequence Command Interface. This sequence equal P/E.C. instructions. command itself confirmation applies given third fourth sixth cycles.
Instructions
Seven instructions defined perform Reset, Read Electronic Signature, Auto Program, Sector Auto Erase, Auto Bulk Erase, Sector Erase Suspend Sector Erase Resume. internal Program/Erase Controller (P/E.C.) handles timing verification Program Erase instructions provides Data Polling, Toggle, Status data indicate completion Program Erase Operations. Instructions composed cycles. first cycles input code sequence Command Interface which common P/E.C. instructions (see Table Command Descriptions). third cycle inputs instruction command instruction Command Interface. Subsequent cycles output Signature addressed data Read operations. added data protection, instructions program sector bulk erase require further command inputs. Program instruction, fourth command cycle inputs address data programmed. Erase instruction (sector bulk), fourth fifth cycles input further code sequence before Erase confirm command sixth cycle. Byte programming takes typically 10µs while erase performed typically seconds. Erasure memory sector suspended, order read data from another sector, then resumed. Data Polling, Toggle Error data read time, including during programming erase cycles, monitor progress operation. When power first applied falls below VLKO, command interface reset Read Array.
PSD813FN/FH
Appendix Flash Memory
(cont.)
Table Operations Operation
Read Write Output Disable Standby
NOTE: VIH.
Data Output Data Input Hi-Z Hi-Z
Table Electronic Signature Operation
Manufact. Code Device Code
Addresses
Don't Care Don't Care
0E2h
NOTE: RSIG instruction
Device Operation
Signal Descriptions
Address Inputs
Address inputs memory array latched during write operation. When Low, Electronic Signature Manufacturer code read. When High Low, Device code read. RSIG instruction Table
Data Input/Outputs
data input byte programmed command written C.I. Both latched when Chip Enable Write Enable active. data output from memory Array, Electronic Signature, Data Polling (D7), Toggle (D6), Error (D5) Erase Timer (D3). Outputs valid when Chip Enable Output Enable active. output high impedance when chip deselected outputs disabled.
Chip Enable
Chip Enable activates memory control logic, input buffers, decoders sense amplifiers. High deselects memory reduces power consumption standby level. also used control writing command register memory array, while remains level. Addresses then latched falling edge while data latched rising edge CSF.
Output Enable
Output Enable gates outputs through data buffers during read operation.
Write Enable
This input controls writing Command Register Address Data latches. Addresses latched falling edge WRF, Data Inputs latched rising edge WRF.
Supply Voltage
power supply operations (Read, Program Erase).
Ground
reference voltage measurements.
PSD813FN/FH
Device Operation (cont.)
Table Instructions (Note
Mne. Instr. Cyc.
Addr.(2,0) Data Addr.(2,5) Data Addr.(2,5) Program Data Sector Erase Bulk Erase Erase Suspend Erase Resume Addr.(2,5) Data Addr.(2,5) Data Addr.(2,5) Data Addr.(2,5) Data 0AAh x5555h 0AAh x5555h 0AAh 0B0h x2AAAh x2AAAh 0A0h x5555h x5555h
Cyc.
0F0h x5555h 0AAh x5555h
Cyc. Cyc.
Cyc.
Cyc.
Cyc.
Cyc.
RST(3,8) Reset RSIG(3)
Read Memory Array until write cycle initiated. x2AAAh x2AAAh x5555h x5555h Read Electronic Signature until write cycle initiated. Note Program Address Program Data x2AAAh 0AAh x5555h 0AAh
Read
Read Data polling toggle until Program completes. Sector Additional Address Sector(6) x5555h Note
x2AAAh x2AAAh
Read until Toggle stops, then read data needed from sector(s) being erased then Resume Erase. Read Data Polling Toggle until Erase completes Erase suspended another time.
NOTES: Command interpreted this table will default read array mode. Don't Care. first cycle RST, RSIG instruction followed read operations read memory array, Status Register Electronic Signature codes. number read cycles occur after command cycle. Signature Address bits will output Manufacturer code (20h). Address bits will output Device code (0E2h). Address bits A16, A17, don't care coded address inputs. Optional, additional sectors addresses must entered within 80µs delay after last write entry, timeout status verified through value. When full command entered, read Data Polling Toggle until Erase completed suspended. Read Data Polling Toggle until Erase completes. wait time necessary after Reset command before starting operation.
Table Commands Code
0A0h 0B0h 0F0h
Command
Invalid/Reserved Bulk Erase Confirm Sector Erase Resume/Confirm Set-up Erase Read Electronic Signature Program Erase Suspend Reset
PSD813FN/FH
Device Operation (cont.)
Table Status Register Name Logic Level
Data Polling `-1-0-1-0-1-0-1-' Toggle `-0-0-0-0-0-0-0-' `-1-1-1-1-1-1-1-' Error Erase Time Reserved Reserved Reserved Erase Timeout Period Expired Erase Timeout Period Going P/E.C. Erase operation started. Only possible command entry Erase Suspend (ES). additional sector erased parallel entered P/E.C.
Definition
Erase Complete Erase Going Program Complete Program Going Erase Program Going Program (`0' Complete Erase Program (`1' Complete Program Erase Error Program Erase Going
Note
Indicates P/E.C. status, check during Program Erase, completion before checking bits Program Erase Success.
Successive read output complementary data while Programming Erase operations going remain constant level when P/E.C. operations completed Erase Suspend acknowledged.
This P/E.C. exceeded specified time limits.
NOTE: Logic level High, Low. -0-1-0-0-0-1-1-1-0- represent value successive Read operations.
PSD813FN/FH
Appendix Flash Memory
(cont.)
Device Operation (cont.)
Memory Sectors
sectors Flash Memory shown Figure memory array divided into sectors bytes. Each sector erased separately combination sectors erased simultaneously. Sector Erase operation managed automatically P/E.C. operation suspended order read from another sector, then resumed.
Operations
Operations defined specific cycles signals which allow Memory Read, Command Write, Output Disable, Standby, Read Status Bits, Electronic Signature Read. They shown Tables
Read
Read operations used output contents Memory Array, Status Register Electronic Signature. Both Chip Enable Output Enable must order read output memory. Chip Enable input also provides power control should used device selection. Output Enable should used gate data onto output independent device selection. data read depends previous command written memory (see instructions RSIG, Status Bits).
Write
Write operations used give Instruction Commands memory latch input data programmed. write operation initiated when Chip Enable Write Enable with Output Enable High. Addresses latched falling edge whichever occurs last. Commands Input Data latched rising edge whichever occurs first.
Output Disable
data outputs high impedance when Output Enable High with Write Enable High.
Standby
memory standby when Chip Enable High Program/Erase Controller P/E.C. Idle. power consumption reduced standby level outputs high impedance, independent Output Enable Write Enable inputs.
Automatic Standby
After inactivity when CMOS levels driving addresses, chip automatically enters pseudo standby mode where power consumption reduced CMOS standby value, while outputs still driving bus.
PSD813FN/FH
Appendix Flash Memory
(cont.)
Figure Memory Sector Address Table
ADDRESS Bytes Sector Bytes Sector Bytes Sector Bytes Sector Bytes Sector 7FFFFh 6FFFFh 5FFFFh 4FFFFh 3FFFFh 2FFFFh 1FFFFh 0FFFFh BOTTOM ADDRESS 70000h 60000h 50000h 40000h 30000h 20000h 10000h 00000h
Instructions Commands
Command Interface (C.I.) latches commands written memory. Instructions made from more commands perform Reset, Read Electronic Signature, Sector Erase, Bulk Erase, Program, Sector Erase Suspend Erase Resume. Commands made address data sequences. Addresses latched falling edge data latched rising CSF. instructions require from cycles, first first three which always write operations used initiate command. They followed either further write cycles confirm first command execute command immediately. Command sequencing must followed exactly. invalid combination commands will reset device Read Array. increased number cycles been chosen assure maximum data security. Commands initialized preceding coded cycles which unlock Command Interface. addition, Erase, command confirmation again preceded coded cycles. P/E.C. status indicated during command execution Data Polling detection Toggle Error Erase Timer bits. read attempt during Program Erase command execution will automatically output those four bits. P/E.C. automatically sets bits Other bits (D0, reserved future should masked.
Data Polling
When Programming operations progress, this outputs complement being programmed During Erase operation, outputs `0'. After completion operation, will output last programmed after erasing. Data Polling valid only effective during P/E.C. operation, that after fourth pulse programming after sixth pulse Erase. must performed address being programmed address within sector being erased. byte programmed belongs protected sector command ignored. sectors selected erasure protected, will about then return previous addressed memory data. Figure Data Polling flowchart.
PSD813FN/FH
Appendix Flash Memory
(cont.)
Figure Data Polling Flowchart
START
READ VALID ADDRESS
DATA
READ
DATA FAIL
PASS
Instructions Commands (cont.)
Toggle
When Programming operations progress, successive attempts read will output complementary data. will toggle following toggling either when low. operation completed when successive reads yield same output data. next read will output last programmed after erasing. toggle valid only effective during P/E.C. operations, that after fourth pulse programming after sixth pulse Erase. byte programmed belongs protected sector command will ignored. sectors selected erasure protected, will toggle about then return back Read. Figure Toggle flowchart Figure Toggle waveforms.
PSD813FN/FH
Appendix Flash Memory
(cont.)
Figure Data Toggle Flowchart
START
READ
TOGGLE
READ
TOGGLE FAIL
PASS
Figure Data Toggle Waveforms
A0-A18
VALID
tAVQV tSLQV tRLQV
STOP TOGGLE
VALID
D0-D5, LAST CYCLE PROGRAM ERASE DATA TOGGLE READ CYCLE
IGNORE DATA TOGGLE READ CYCLE
VALID READ CYCLE
PSD813FN/FH
Appendix Flash Memory
(cont.)
Device Operation (cont.)
Instructions Commands (cont.)
Error
This P/E.C. when there failure byte programming, sector erase, bulk erase that results invalid data being programmed memory sector. case error sector erase byte program, sector which error occurred which programmed byte belongs, must discarded. Other sectors still used. Error resets after Reset (RST) instruction. case success, error will during Program Erase valid data after write operation completed.
Erase Time
This P/E.C. when last sector Erase command been entered Command Interface awaiting Erase start. When wait period finished, after returns back `1'.
Coded Cycles
coded cycles unlock Command Interface. They followed command input command confirmation. coded cycles consist writing data 0AAh address 5555h during first cycle data address 2AAAh during second cycle. Addresses latched falling edge while data latched rising edge CSF. coded cycles happen first second cycles command write fourth fifth cycles.
Reset (RST) Instruction
Reset instruction consists write operation giving command 0F0h. optionally preceded coded cycles. After wait state subsequent read operations will read memory array addressed output read byte.
Read Electronic Signature (RSIG) Instruction
This instruction uses coded cycles followed write cycle giving command address 5555h command setup. subsequent read will output manufacturer code device code depending levels A16, A18. manufacturer code, 20h, output when addresses lines Low, device code, 0E2h output when High with Low. Table
Bulk Erase (BE) Instruction
This instruction uses write cycles. Erase Set-up command written address 5555h third cycle after coded cycles. Bulk Erase Confirm command written address 5555h sixth cycle after another coded cycles. second command given erase confirm coded cycles wrong, instruction aborts device reset Read Array. necessary program array with first P/E.C. will automatically this before erasing 0FFh. Read operations after sixth rising edge output status register bits. During execution erase P/E.C. memory accepts only Reset (RST) command. Read Data Polling return `0', then completion. Toggle toggles during erase operation stops when erase completed. After completion Status Register returns there been Erase Failure because erasure been verified even after maximum number erase cycles have been executed.
PSD813FN/FH
Appendix Flash Memory
(cont.)
Device Operation (cont.)
Instructions Commands (cont.)
Sector Erase (SE) Instruction
This instruction uses minimum write cycles. Erase Set-up command written address 5555h third cycle after coded cycles. Sector Erase Confirm command written sixth cycle after another coded cycles. During input second command address within sector erased given latched into memory. Additional Sector Erase confirm commands sector addresses written subsequently erase other sectors parallel, without further coded cycles. erase will start after Erase timeout period about Thus, additional Sector Erase commands must given within this delay. input Sector Erase command will restart timeout period. status internal timer monitored through level Sector Erase Command been given timeout running, `1', timeout expired P/E.C. erasing sector(s). Before during Erase timeout, command different from will abort instruction reset device read array mode. necessary program sector with P/E.C. will this automatically before erasing 0FFh. Read operations after sixth rising edge output status register status bits. During execution erase P/E.C., memory accepts only (Erase Suspend) (Reset) instructions. Data Polling returns while erasure progress when completed. Toggle toggles during erase operation. stops when erase completed. After completion Status Register returns there been Erase Failure because erasure completed even after maximum number erase cycles have been executed. this case, will necessary input Reset (RST) command interface order reset P/E.C.
Program (PG) Instruction
This instruction uses four write cycles. Program command written third cycle after coded cycles. fourth write operation latches Address falling edge Data written rising edge starts P/E.C. During execution program P/E.C. P/E.C., memory will accept instruction. Read operations output status bits after programming started. Memory programming made only writing place Byte.
Erase Suspend (ES) Instruction
Sector Erase operation suspended this instruction which consists writing command 0B0h without specific address code. coded cycles required. allows reading data from another sector while erase progress. Erase suspend accepted only during Sector Erase instruction execution defaults read array mode. Writing this command during Erase timeout will, addition suspending erase, terminate timeout. Toggle stops toggling when P/E.C. suspended. Toggle status must monitored address sector being erased. Toggle will stop toggling between after Erase Suspend (ES) command been written. Flash Memory will then automatically Read Memory Array mode. When erase suspended, Read from sectors being erased will output invalid data, Read from sector being erased valid. During suspension memory will respond only Erase Resume (ER) Reset (RST) instructions. command will definitively abort erasure result invalid data sectors being erased.
PSD813FN/FH
Appendix Flash Memory
(cont.)
Device Operation (cont.)
Instructions Commands (cont.)
Erase Resume (ER) Instruction
Erase Suspend instruction previously executed, erase operation resumed giving command 30h, address, without coded cycles.
Programming
memory programmed byte-byte. program sequence started coded cycles, followed writing Program command (0A0h) Command Interface. This followed writing address data byte memory. Program/Erase Controller automatically starts performs programming after fourth write operation. During programming memory status checked reading status bits which show status P/E.C. determine programming going completed allows check made possible error.
Power
memory Command Interface reset power Read Array. Either must tied during Power-up allow maximum security possibility write command first rising edge WRF. write cycle initiation blocked when below VLKO.
Supply Rails
Normal precautions must taken supply voltage decoupling. Each device system should have rail decoupled with capacitor close pins. trace widths should sufficient carry program erase currents required.
Table Program, Erase Times Program, Erase Endurance Cycles
70°C;
Parameter
Chip Program (Byte) Bulk Erase (Preprogrammed) Bulk Erase Sector Erase (Preprogrammed) Sector Erase Byte Program Program/Erase Cycles (per Sector)
Unit
100,000
1200
cycles
Product Revisions
Product Revisions
Original PSD813FN/FH (10/97)
Revision Reason
Initial release
Data Sheet Changes
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