Data Sheet March 2003 FN4586.2 Advanced Dual Linear Power Control

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Data Sheet March 2003 FN4586.2 Advanced Dual Linear Power Control

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HIP6018B
Data Sheet March 2003 FN4586.2
Advanced Dual Linear Power Control
HIP6018B provides power control protection three output voltages high-performance microprocessor computer applications. integrates controllers, linear regulator linear controller well monitoring protection functions into single package. controller regulates microprocessor core voltage with synchronous-rectified buck converter. linear controller regulates power linear regulator provides power clock driver circuit. HIP6018B includes Intel-compatible, 5-input digital-to-analog converter (DAC) that adjusts core output voltage from 2.1VDC 3.5VDC 0.1V increments from 1.3VDC 2.05VDC 0.05V steps. precision reference voltage-mode control provide static regulation. linear regulator uses internal pass device provide 2.5V ±2.5%. linear controller drives external N-channel MOSFET provide 1.5V ±2.5%. HIP6018B monitors output voltages. single Power Good signal issued when core within ±10% setting other levels above their undervoltage levels. Additional built-in over-voltage protection core output uses lower MOSFET prevent output voltages above 115% setting. overcurrent function monitors output current using voltage drop across upper MOSFET's rDS(ON), eliminating need current sensing resistor.
Features
Provides Regulated Voltages Microprocessor Core, Clock Power Drives N-Channel MOSFETs Operates from +3.3V, +12V Inputs Simple Single-Loop Control Design Voltage-Mode Control Fast Transient Response High-Bandwidth Error Amplifier Full 100% Duty Ratios Excellent Output Voltage Regulation Core Output: Over Temperature Other Outputs: ±2.5% Over Temperature TTL-Compatible 5-Bit Digital-to-Analog Core Output Voltage Selection Wide Range 1.3VDC 3.5VDC 0.1V Steps 2.1VDC 3.5VDC 0.05V Steps 1.3VDC 2.05VDC Power-Good Output Voltage Monitor Microprocessor Core Voltage Protection Against Shorted MOSFET Over-Voltage Over-Current Fault Monitors Does Require Extra Current Sensing Element, Uses MOSFET's rDS(ON) Small Converter Size Constant Frequency Operation 200kHz Free-Running Oscillator; Programmable from 50kHz over 1MHz
Pinout
HIP6018B (SOIC) VIEW
Applications
Full Motherboard Power Regulation Computers
UGATE1 PHASE1 LGATE1 PGND OCSET1 VSEN1 COMP1 DRIVE3 VOUT2
VID4 VID3 VID2 VID1 VID0 PGOOD FAULT VIN2
Low-Voltage Distributed Power Supplies
Ordering Information
PART NUMBER HIP6018BCB TEMP. RANGE (oC) PACKAGE SOIC PKG. M24.3
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2003. Rights Reserved other trademarks mentioned property their respective owners.
Block Diagram
VSEN1
OCSET1
RESET (POR) PGOOD 1.26V 115% INHIBIT 0.3V 200mA LINEAR UNDERVOLTAGE 110% POWER-ON
DRIVE3
SOFTSTART FAULT LOGIC INHIBIT GATE CONTROL DACOUT 11µA ERROR COMP LOWER DRIVE CONVERTER (DAC) UPPER DRIVE OSCILLATOR VID4 VID0 VID2 VID1 VID3 COMP1
VIN2
VOUT2
0.23A
UGATE1 PHASE1
HIP6018B
FIGURE
FAULT
LGATE1 PGND
HIP6018B Simplified Power System Diagram
+5VIN +3.3VIN VOUT2 LINEAR REGULATOR PWM1 CONTROLLER VOUT1
HIP6018B
VOUT3 LINEAR CONTROLLER
FIGURE
Typical Application
+12VIN +5VIN OCSET1 PGOOD VOUT2 2.5V COUT2 VOUT2 UGATE1 PHASE1 LOUT1 VOUT1 1.3V 3.5V POWERGOOD
+3.3VIN
VIN2
LGATE1 VOUT3 1.5V COUT3 VID0 VID1 VID2 VID3 VID4 FAULT COMP1 DRIVE3 PGND
COUT1
HIP6018B
VSEN1
FIGURE
HIP6018B
Absolute Maximum Ratings
Supply Voltage, .+15V PGOOD, FAULT, GATE Voltage 0.3V 0.3V Input, Output Voltage -0.3V
Thermal Information
Thermal Resistance (Typical, Note
(oC/W)
Operating Conditions
Supply Voltage, +12V ±10% Ambient Temperature Range. 70oC Junction Temperature Range 125oC
SOIC Package Maximum Junction Temperature (Plastic Package) 150oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) .300oC (SOIC Lead Tips Only)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted high effective thermal conductivity test board free air. Tech Brief TB379 details.
Electrical Specifications
PARAMETER SUPPLY CURRENT Nominal Supply POWER-ON RESET Rising Threshold Falling Threshold
Recommended Operating Conditions, Unless Otherwise Noted. Refer Figures SYMBOL TEST CONDITIONS UNITS
UGATE1, DRIVE3, LGATE1, VOUT2 Open
VOCSET 4.5V VOCSET 4.5V
2.45
2.55 1.25
10.4 10.2 2.65
Rising VIN2 Under-Voltage Threshold VIN2 Under-Voltage Hysteresis Rising VOCSET1 Threshold OSCILLATOR Free Running Frequency Total Variation Ramp Amplitude REFERENCE DAC(VID0-VID4) Input Voltage DAC(VID0-VID4) Input High Voltage DACOUT Voltage Accuracy Reference Voltage (Pin FB3) LINEAR REGULATOR Regulation Under-Voltage Level Under-Voltage Hysteresis Over-Current Protection Over-Current Protection During Start-Up LINEAR CONTROLLER Regulation Under-Voltage Level Under-Voltage Hysteresis Output Drive Current DRIVE3 Source Current IDRIVE3 VIN2 VOUT3 1.5V VIN2 DRIVE3 0.6V FB3UV VSEN3 DRIVE3, IDRIVE3 20mA Rising FB2UV 10mA IVOUT2 150mA Rising VOSC OPEN 200k Open
VP-P
-1.0 1.240
1.265
+1.0 1.290
-2.5
-2.5
HIP6018B
Electrical Specifications
PARAMETER CONTROLLER ERROR AMPLIFIER Gain Gain-Bandwidth Product Slew Rate CONTROLLER GATE DRIVER Upper Drive Source Upper Drive Sink Lower Drive Source Lower Drive Sink PROTECTION VOUT1 Over-Voltage Trip FAULT Sourcing Current OCSET1 Current Source Soft-Start Current Chip Shutdown Soft-Start Threshold POWER GOOD VOUT1 Upper Threshold VOUT1 Under Voltage VOUT1 Hysteresis (VSEN1 DACOUT) PGOOD Voltage VPGOOD VSEN1 Rising VSEN1 Rising Upper/Lower Threshold IPGOOD -4mA IOVP IOCSET VSEN1 Rising VFAULT VOCSET 4.5VDC IUGATE RUGATE ILGATE RLGATE 12V, VUGATE1 VGATE2) VUGATE1-PHASE1 12V, VLGATE1 VLGATE1 GBWP COMP 10pF V/µs Recommended Operating Conditions, Unless Otherwise Noted. Refer Figures (Continued) SYMBOL TEST CONDITIONS UNITS
Typical Performance Curves
CUGATE1 CLGATE1 CGATE VVCC 12V, 1000 RESISTANCE PULLUP +12V (mA) CGATE 4800pF
CGATE 3600pF CGATE 1500pF
PULLDOWN
CGATE 660pF
SWITCHING FREQUENCY (kHz)
1000
1000
SWITCHING FREQUENCY (kHz)
FIGURE RESISTANCE FREQUENCY
FIGURE BIAS SUPPLY CURRENT FREQUENCY
HIP6018B Functional Description
VSEN1 (Pin
This connected converter's output voltage. PGOOD comparator circuits this signal report output voltage status over voltage protection.
UGATE1 (Pin
Connect UGATE converter's upper MOSFET gate. This provides gate drive upper MOSFET.
PGND (Pin
This power ground connection. converter's lower MOSFET source this pin.
OCSET1 (Pin
Connect resistor (ROCSET) from this drain upper MOSFET. ROCSET, internal 200µA current source (IOCSET), upper MOSFET on-resistance (rDS(ON)) converter over-current (OC) trip point according following equation:
OCSET OCSET PEAK
LGATE1 (Pin
Connect LGATE1 converter's lower MOSFET gate. This provides gate drive lower MOSFET.
(Pin
Provide bias supply this pin. This also provides gate bias charge MOSFETs controlled
over-current trip cycles soft-start function. Sustaining over-current soft-start intervals shuts down controller.
(Pin
This provides oscillator switching frequency adjustment. placing resistor (RT) from this GND, nominal 200kHz switching frequency increased according following equation:
200kHz
(Pin
Connect capacitor from this ground. This capacitor, along with internal 11µA (typically) current source, sets soft-start interval converter. Pulling this with open drain signal will shut down
GND)
VID0, VID1, VID2, VID3, VID4 (Pins
VID0-4 input pins 5-bit DAC. states these five pins program internal voltage reference (DACOUT). level DACOUT sets core converter output voltage. also sets core PGOOD thresholds.
Conversely, connecting pull-up resistor (RT) from this reduces switching frequency according following equation:
200kHz
12V)
COMP1 (Pins
COMP1 available external pins error amplifier. inverting input error amplifier. Similarly, COMP1 error amplifier output. These pins used compensate voltagecontrol feedback loop converter.
FAULT (Pin
This during normal operation, pulled event over-voltage over-current condition.
DRIVE3 (Pin
Connect this gate external MOSFET. This provides drive linear controller's pass transistor.
(Pin
Signal ground voltage levels measured with respect this pin.
(Pin
Connect this resistor divider linear controller output voltage.
PGOOD (Pin
PGOOD open collector output used indicate status output voltages. This pulled when core output within ±10% DACOUT reference voltage other outputs below their under-voltage thresholds. PGOOD output open `11111' code. Table
VOUT2 (Pin
Output linear regulator. Supplies current 230mA.
(Pin
Connect this resistor divider linear regulator output voltage.
PHASE1 (Pin
Connect PHASE converter's upper MOSFET source. This used monitor voltage drop across upper MOSFET over-current protection.
VIN2 (Pin
This supplies power internal regulator. Connect this suitable 3.3V source. Additionally, this used monitor 3.3V supply. following startup cycle, voltage drops below 2.55V (typically), chip shuts down. soft-start cycle
HIP6018B
initiated upon return 3.3V supply above undervoltage threshold. until each output reaches sufficient voltage transfer control input reference clamp. consider 2.0V output (VOUT1) Figure this time occurs During interval between error amplifier reference ramps final value converter regulates output voltage proportional voltage. input clamp voltage exceeds reference voltage output voltage regulation.
Description
Operation
HIP6018B monitors precisely controls output voltage levels (Refer Figures designed microprocessor computer applications with 3.3V power, bias input from power supply. controller, linear controller, linear regulator. controller designed regulate microprocessor core voltage (VOUT1) driving MOSFETs synchronous-rectified buck converter configuration. core voltage regulated level programmed 5-bit digital-to-analog converter (DAC). integrated linear regulator supplies 2.5V clock power (VOUT2). linear controller drives external MOSFET (Q3) supply power (VOUT3).
PGOOD (2V/DIV) SOFT-START (1V/DIV)
Initialization
HIP6018B automatically initializes upon receipt input power. Special sequencing input supplies necessary. Power-On Reset (POR) function continually monitors input supply voltages. monitors bias voltage (+12VIN) pin, input voltage (+5VIN) OCSET1 pin, 3.3V input VIN2 pin. normal level OCSET1 equal +5VIN less fixed voltage drop (see over-current protection). function initiates soft-start operation after three input supply voltages exceed their thresholds.
VOUT2 2.5V) VOUT1 (DAC OUTPUT VOLTAGES (0.5V/DIV) VOUT3 1.5V)
TIME
Soft-Start
function initiates soft-start sequence. Initially, voltage rapidly increases approximately (this minimizes soft-start interval). Then internal 11µA current source charges external capacitor (CSS) error amplifier reference input (+terminal) output (COMP1 pin) clamped level proportional voltage. voltage slews from output clamp generates PHASE pulses increasing width that charge output capacitor(s). After this initial stage, reference input clamp slows output voltage rate-of-rise provides smooth transition final voltage. Additionally both linear regulator's reference inputs clamped voltage proportional voltage. This method provides rapid controlled output voltage rise. Figure shows soft-start sequence typical application. voltage rapidly increases approximately error amplifier output voltage reach valley oscillator's triangle wave. oscillator's triangular waveform compared clamped error amplifier output voltage. voltage increases, pulse-width PHASE increases. interval increasing pulse-width continues
FIGURE SOFT-START INTERVAL
remaining outputs also programmed follow voltage. Each linear output (VOUT2 VOUT3) initially follows ramp similar that output. When each output reaches sufficient voltage input reference clamp slows rate output voltage rise. PGOOD signal toggles `high' when output voltage levels have exceeded their under-voltage levels. Soft-Start Interval section under Applications Guidelines procedure determine soft-start interval.
Fault Protection
three outputs monitored protected against extreme overload. sustained overload linear regulator output over-voltage output disables converters drives FAULT VCC. Figure shows simplified schematic fault logic. over-voltage detected VSEN1 immediately sets fault latch. sequence three over-current fault signals also sets fault latch. comparator indicates when fully charged signal), such that under-voltage event either linear output (FB2 FB3) ignored until after softstart interval Figure startup, this allows VOUT2
HIP6018B
OVER CURRENT LATCH 0.15V COUNTER FAULT LATCH FAULT INHIBIT
soft-start voltage continues increasing before discharging. counter increments soft-start cycle repeats trips over-current comparator. voltage increases counter increments This sets fault latch disable converter. fault reported FAULT pin.
FAULT/RT
COUNT OVERLOAD APPLIED
FAULT REPORTED
FIGURE FAULT LOGIC SIMPLIFIED SCHEMATIC
VOUT3 slew over increased time intervals, without generating fault. Cycling bias input voltage (+12VIN pin) then resets counter fault latch.
Over-Voltage Protection
During operation, short upper MOSFET (Q1) causes VOUT1 increase. When output exceeds over-voltage threshold 115% (typical) DACOUT, over-voltage comparator trips fault latch turns required order regulate VOUT1 1.15 DACOUT. This blows input fuse reduces VOUT1. fault latch raises FAULT close potential. separate over-voltage circuit provides protection during initial application power. voltages below power-on reset (and above ~4V), VOUT1 monitored voltages exceeding 1.26V. Should VSEN1 exceed this level, lower MOSFET (Q2) driven needed regulate VOUT1 1.26V.
INDUCTOR CURRENTSOFT-START
COUNT
COUNT
TIME
FIGURE OVER-CURRENT OPERATION
Over-Current Protection
outputs protected against excessive over-currents. controller uses upper MOSFET's onresistance, rDS(ON) monitor current protection against shorted outputs. linear regulator monitors current integrated power device signals overcurrent condition currents excess 230mA. Additionally, both linear regulator linear controller monitor under-voltage protect against excessive currents. Figures illustrate over-current protection with overload OUT1. overload applied current increases through output inductor (LOUT1). time OVER-CURRENT1 comparator trips when voltage across rDS(ON)) exceeds level programmed ROCSET. This inhibits outputs, discharges soft-start capacitor (CSS) with 11µA current sink, increments counter.CSS recharges initiates soft-start cycle with error amplifiers clamped soft-start. With OUT1 still overloaded, inductor current increases trip overcurrent comparator. Again, this inhibits outputs,
linear regulator operates same PWM1 over-current faults. Additionally, linear regulator linear controller monitor feedback pins undervoltage. Should excessive currents cause fall below linear under-voltage threshold, signal sets over-current latch fully charged. Blanking signal during charge interval allows linear outputs build above under-voltage threshold during normal start-up. Cycling bias input power then resets counter fault latch. Resistor ROCSET1 programs over-current trip level converter. shown Figure internal 200µA current sink develops voltage across ROCSET (VSET) that referenced VIN. DRIVE signal enables over-current comparator (OVER-CURRENT1). When voltage across upper MOSFET (VDS(ON)) exceeds VSET, over-current comparator trips over-current latch. Both VSET referenced small capacitor across ROCSET helps VOCSET track variations MOSFET switching. over-current function will trip peak inductor current (IPEAK) determined
OCSET OCSET PEAK
HIP6018B
OVER-CURRENT TRIP: VSET rDS(ON) IOCSET ROCSET) OCSET IOCSET 200µA DRIVE UGATE PHASE GATE CONTROL LGATE PGND VPHASE VOCSET VSET ROCSET VSET
TABLE VOUT1 VOLTAGE PROGRAM NAME NOMINAL OUT1 VOLTAGE DACOUT 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 INHIBIT
VID4
VID3
VID2
VID1
VID0
OVERCURRENT1 HIP6018B
FIGURE OVER-CURRENT DETECTION
trip point varies with MOSFET's temperature. avoid over-current tripping normal operating load range, determine ROCSET resistor from equation above with: maximum rDS(ON) highest junction temperature. minimum IOCSET from specification table. Determine IPEAK IPEAK IOUT(MAX) where output inductor ripple current. equation output inductor ripple current section under component guidelines titled `Output Inductor Selection'.
OUT1 Voltage Program
output voltage converter programmed discrete levels between 1.3VDC 3.5VDC This output designed supply microprocessor core voltage. voltage identification (VID) pins program internal voltage reference (DACOUT) through TTL-compatible 5-bit digital-to-analog converter. level DACOUT also sets PGOOD thresholds. Table specifies DACOUT voltage different combinations connections pins. pins left open logic input, because they internally pulled 10µA (typically) current source. Changing inputs during operation recommended. sudden change resulting reference voltage could toggle PGOOD signal exercise over-voltage protection. `11111' combination resulting INHIBIT disables open-collector PGOOD pin.
NOTE: connected VSS, open connected through pull-up resistors.
HIP6018B Application Guidelines
Soft-Start Interval
Initially, soft-start function clamps error amplifier's output converter. After output voltage increases approximately value, reference input error amplifier clamped voltage proportional voltage. Both linear outputs follow similar start-up sequence. resulting output voltage sequence shown Figure soft-start function controls output voltage rate rise limit current surge start-up. soft-start interval programmed soft-start capacitor, CSS. Programming faster soft-start interval increases peak surge current. peak surge current occurs during initial output voltage rise value. critical small signal components include by-pass capacitor soft-start capacitor, CSS. Locate these components close their connecting pins control Minimize leakage current paths from node because internal current source only 11µA.
+5VIN +3.3VIN +12V CVCC VIN2 OCSET1 VOUT3 LOAD GATE3UGATE1 PHASE1 LOAD HIP6018B VOUT2 LGATE1 PGND VOUT2 LOAD COUT2 COUT1 COCSET1 ROCSET1 LOUT1 VOUT1
Shutdown
output does switch until soft-start voltage (VSS) exceeds oscillator's valley voltage. Additionally, reference each linear's amplifier clamped soft-start voltage. Holding with open drain collector signal turns three regulators. codes resulting INHIBIT shown Table also shuts down
ISLAND POWER PLANE LAYER ISLAND CIRCUIT PLANE LAYER CONNECTION GROUND PLANE
FIGURE PRINTED CIRCUIT BOARD POWER PLANES ISLANDS
Layout Considerations
MOSFETs switch very fast efficiently. speed with which current transitions from device another causes voltage spikes across interconnecting impedances parasitic circuit elements. voltage spikes degrade efficiency, radiate noise into circuit, lead device over-voltage stress. Careful component layout printed circuit design minimizes voltage spikes converter. Consider, example, turn-off transition upper MOSFET. Prior turn-off, upper MOSFET carrying full load current. During turn-off, current stops flowing upper MOSFET picked lower MOSFET (and/or parallel Schottky diode). inductance switched current path generates large voltage spike during switching interval. Careful component selection, tight layout critical components, short, wide circuit traces minimize magnitude voltage spikes. Contact Intersil evaluation board drawings component placement printed circuit board. There sets critical components DC-DC converter using HIP6018B controller. power components most critical because they switch large amounts energy. critical small signal components connect sensitive nodes supply critical by-passing current. power components should placed first. Locate input capacitors close power switches. Minimize length connections between input capacitors power switches. Locate output inductor output capacitors between MOSFETs load. Locate controller close MOSFETs.
multi-layer printed circuit board recommended. Figure shows connections critical components converter. Note that capacitors COUT could each represent numerous physical capacitors. Dedicate solid layer ground plane make critical component ground connections with vias this layer. Dedicate another solid layer power plane break this plane into smaller islands common voltage levels. power plane should support input power output power nodes. copper filled polygons bottom circuit layers phase nodes. remaining printed circuit layers small signal wiring. wiring traces from control MOSFET gate source should sized carry currents. traces OUT2 need only sized 0.2A. Locate COUT2 close HIP6018B
Controller Feedback Compensation
Both controllers voltage-mode control output regulation. This section highlights design consideration voltage-mode controller. Apply methods considerations both controllers. Figure highlights voltage-mode control loop synchronous-rectified buck converter. output voltage regulated reference voltage level. reference voltage level output voltage controller. error amplifier output (VE/A) compared with oscillator (OSC) triangular wave provide pulse-width modulated wave with amplitude PHASE node. wave smoothed output filter CO).
HIP6018B
COMP DRIVER DRIVER PHASE (PARASITIC) VE/A VOUT
Compensation Break Frequency Equations
VOSC
ERROR
REFERENCE
DETAILED FEEDBACK COMPENSATION COMP VOUT
Figure shows asymptotic plot DC-DC converter's gain frequency. actual modulator gain peak high factor output filter FLC, which shown Figure Using above guidelines should yield compensation gain similar curve plotted. open loop error amplifier gain bounds compensation gain. Check compensation gain with capabilities error amplifier. closed loop gain constructed log-log graph Figure adding modulator gain compensation gain dB). This equivalent multiplying modulator transfer function compensation transfer function plotting gain.
GAIN (dB) FESR 100K 20LOG (R2/R1) MODULATOR GAIN OPEN LOOP ERROR GAIN
HIP6018B
REFERENCE
FIGURE VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN
modulator transfer function small-signal transfer function VOUT/VE/A. This function dominated gain output filter, with double pole break frequency zero FESR. gain modulator simply input voltage, VIN, divided peak-to-peak oscillator voltage, VOSC
20LOG (VIN/VOSC) COMPENSATION GAIN CLOSED LOOP GAIN
Modulator Break Frequency Equations
FREQUENCY (Hz)
FIGURE ASYMPTOTIC BODE PLOT CONVERTER GAIN
compensation network consists error amplifier internal HIP6018B impedance networks ZFB. goal compensation network provide closed loop transfer function with acceptable crossing frequency (f0dB) adequate phase margin. Phase margin difference between closed loop phase f0dB degrees. equations below relate compensation network's poles, zeros gain components Figure these guidelines locating poles zeros compensation network: Pick Gain (R2/R1) desired converter bandwidth Place Zero Below Filter's Double Pole (~75% FLC) Place Zero Filter's Double Pole Place Pole Zero Place Pole Half Switching Frequency Check Gain against Error Amplifier's Open-Loop Gain Estimate Phase Margin Repeat Necessary
compensation gain uses external impedance networks provide stable, high bandwidth loop. stable control loop gain crossing with -20dB/decade slope phase margin greater than degrees. Include worst case component variations when determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
output capacitors each output have unique requirements. general output capacitors should selected meet dynamic regulation requirements. Additionally, converters require output capacitor filter current ripple. linear regulator internally compensated requires output capacitor that meets stability requirements. load transient microprocessor core requires high quality capacitors supply high slew rate (di/dt) current demands.
HIP6018B
Output Capacitors
Modern microprocessors produce transient load rates above 10A/ns. High frequency capacitors initially supply transient slow current load rate seen bulk capacitors. bulk filter capacitor values generally determined (effective series resistance) (effective series inductance) parameters rather than actual capacitance. High frequency decoupling capacitors should placed close power pins load physically possible. careful inductance circuit board wiring that could cancel usefulness these inductance components. Consult with manufacturer load specific decoupling requirements. only specialized low-ESR capacitors intended switching regulator applications bulk capacitors. bulk capacitor's determines output ripple voltage initial voltage drop after high slew-rate transient. aluminum electrolytic capacitor's value related case size with lower available larger case sizes. However, equivalent series inductance these capacitors increases with case size reduce usefulness capacitor high slew-rate transient loading. Unfortunately, specified parameter. Work with your capacitor supplier measure capacitor's impedance with frequency select suitable components. most cases, multiple electrolytic capacitors small case size perform better than single large case capacitor. given transient load magnitude, output voltage transient response output capacitor characteristics approximated following equation:
TRAN TRAN TRAN
CAPACITANCE (µF) 1000
ATIO
FIGURE COUT2 OUTPUT CAPACITOR
Increasing value inductance reduces ripple current voltage. However, large inductance values reduce converter's response time load transient. parameters limiting converter's response load transient time required change inductor current. Given sufficiently fast control loop design, HIP6018B will provide either 100% duty cycle response load transient. response time time interval required slew inductor current from initial current value post-transient current level. During this interval difference between inductor current transient current level must supplied output capacitors. Minimizing response time minimize output capacitance required. response time transient different application load removal load. following equations give approximate response time interval application removal transient load:
TRAN RISE TRAN FALL
Linear Output Capacitors
output capacitors linear regulator linear controller provide dynamic load current. linear controller uses dominant pole compensation integrated error amplifier insensitive output capacitor selection. Capacitor, COUT3 should selected transient load regulation. output capacitor linear regulator provides loop stability. linear regulator (OUT2) requires output capacitor characteristic shown Figure upper line plots phase margin with 150mA load lower line phase margin limit with 10mA load. Select COUT2 capacitor with characteristic between limits.
where: ITRAN transient load current step, tRISE response time application load, tFALL response time removal load. With input source, worst case response time either application removal load, dependent upon output voltage setting. sure check both these equations minimum maximum output levels worst case response time.
Input Capacitor Selection
important parameters bulk input capacitor voltage rating current rating. reliable operation, select bulk capacitor with voltage current ratings above maximum input voltage largest current required circuit. capacitor voltage rating should least 1.25 times greater than maximum input voltage voltage rating times conservative guideline.
Output Inductor Selection
converter requires output inductor. output inductor selected meet output voltage ripple requirements sets converter's response time load transient. inductor value determines converter's ripple current ripple voltage function ripple current. ripple voltage current approximated following equations:
HIP6018B
input bypass capacitors control voltage overshoot across MOSFETs. ceramic capacitance high frequency decoupling bulk capacitors supply current. Small ceramic capacitors should placed very close upper MOSFET suppress voltage induced parasitic circuit impedances. through hole design, several electrolytic capacitors (Panasonic series Nichicon series Sanyo MVGX equivalent) needed. surface mount designs, solid tantalum capacitors used, caution must exercised with regard capacitor surge current rating. These capacitors must capable handling surge-current power-up. series available from AVX, 593D series from Sprague both surge current tested. applied upper MOSFET different than lower MOSFET. Figure shows gate drive where upper gateto-source voltage approximately less input supply. main power +12VDC bias, gate-to-source voltage lower gate drive voltage +12VDC. logic-level MOSFET good choice logic-level MOSFET used absolute gate-to-source voltage rating exceeds maximum voltage applied
LESS +12V
HIP6018B
UGATE PHASE NOTE: NOTE:
MOSFET Selection/Considerations
HIP6018B requires N-Channel power MOSFETs. MOSFETs used synchronous-rectified buck topology converter. linear controller drives MOSFET pass transistor. These should selected based upon rDS(ON) gate supply requirements, thermal management requirements.
LGATE PGND
FIGURE OUTPUT GATE DRIVERS
PWM1 MOSFET Selection Considerations
high-current applications, MOSFET power dissipation, package selection heatsink dominant design factors. power dissipation includes loss components; conduction loss switching loss. These losses distributed between upper lower MOSFETs according duty factor (see equations below). conduction loss only component power dissipation lower MOSFET. Only upper MOSFET switching losses, since lower device turns into near zero voltage. equations below assume linear voltage-current transitions model power loss reverse-recovery lower MOSFET's body diode. gate-charge losses proportional switching frequency (FS) dissipated HIP6018B, thus contributing MOSFETs' temperature rise. However, large gate charge increases switching interval, which increases upper MOSFET switching losses. Ensure that both MOSFETs within their maximum junction temperature high ambient temperature calculating temperature rise according package thermal resistance specifications. separate heatsink necessary depending upon MOSFET power, package type, ambient temperature flow.
UPPER LOWER
Rectifier clamp that catches negative inductor voltage swing during dead time between turn lower MOSFET turn upper MOSFET. diode must Schottky type prevent lossy parasitic MOSFET body diode from conducting. acceptable omit diode body diode lower MOSFET clamp negative inductor swing, efficiency might drop percent result. diode's rated reverse breakdown voltage must greater than twice maximum input voltage.
Linear Controller MOSFET Selection
main criteria selection transistor linear regulator package selection efficient removal heat. power dissipated linear regulator
LINEAR
Select package heatsink that maintains junction temperature below maximum rating while operating highest expected ambient temperature. Additionally, selecting bipolar transistor, insure gain (hfe) minimum operating temperature given collector-to-emitter voltage sufficiently high deliver worst-case steady state current required output, when transistor driven with minimum guaranteed DRIVE3 output current. example, operating junction temperature, 3.3V input, 1.5V output (VCE 1.8V) NPN's gain should satisfy following equation:
steady state DRIVE3
rDS(ON) different previous equations even type device used both. This because gate drive
HIP6018B HIP6018B DC-DC Converter Application Circuit
Figure shows application circuit power supply microprocessor computer system. power supply provides microprocessor core voltage (VOUT1), voltage (VOUT3) clock generator voltage (VOUT2) from +3.3VDC, +5VDC +12VDC. detailed information
+12VIN +5VIN
circuit, including Bill-of-Materials circuit board description, Application Note AN9805. Also Intersil's page (http://www.intersil.com) Intersil AnswerFAX (321-724-7800) document 99805 latest information.
C1-7 6x1000µF VIN2 OCSET1 1.1K POWERGOOD 1000µF PGOOD 1000pF
+3.3VIN
UGATE1 PHASE1
HUF76143
3.5µH
VOUT1 (1.3 3.5V)
RFD3055 VOUT3 (1.5V) C43-46 4x1000µF 270µF 1.87K
DRIVE3
HIP6018B
LGATE1 PGND VSEN1
HUF76143
C24-36 7x1000µF 4.99K 0.68µF
VOUT2
2.21K COMP1 10pF 732K
VOUT2 (2.5V)
2200pF 160K VID0 VID1 VID2 VID3 VID4 FAULT 0.039µF
VID0 VID1 VID2 VID3 VID4
FIGURE APPLICATION CIRCUIT
HIP6018B Small Outline Plastic Packages (SOIC)
INDEX AREA SEATING PLANE 0.25(0.010)
M24.3 (JEDEC MS-013-AD ISSUE
LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 2.35 0.10 0.33 0.23 15.20 7.40 2.65 0.30 0.51 0.32 15.60 7.60 NOTES Rev. 12/93
0.0926 0.0040 0.013 0.0091 0.5985 0.2914
0.1043 0.0118 0.020 0.0125 0.6141 0.2992
0.10(0.004)
0.05 0.394 0.010 0.016 0.419 0.029 0.050
1.27 10.00 0.25 0.40 10.65 0.75 1.27
0.25(0.010)
NOTES: Symbols defined Series Symbol List" Section Publication Number Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.25mm (0.010 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. lead width "B", measured 0.36mm (0.014 inch) greater above seating plane, shall exceed maximum value 0.61mm (0.024 inch) Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact.
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Data Sheet March 2003 FN4586.2 Advanced Dual Linear Power Control

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