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ST62 ST63 FAMILIES
8-BIT MICROCONTROLLERS EPROM PROGRAMMING SPECIFICATION
This document ST62/63 OTP/EPROM microcontrollers programming specification. should give informations about serial test EPROM programming involved people have implement programming algorithm. further details about device characteristics, please refer technical manual data book family.
Rev.
October 1998
This preliminary information product development undergoing evaluation. Details subject change without notice.
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Table Contents
INTRODUCTION TECHNICAL OVERVIEW EPROM MEMORY DESCRIPTION
2.1.1 EPROM management 2.1.2 Reserved areas
ELECTRICAL CHARACTERISTIC
2.2.1 Absolute maximum ratings 2.2.2 Characteristics during programming
SERIAL TEST MODE AFFECTED PINS SERIAL TEST MODE RECOMMENDED INPUT LEVELS SERIAL TEST MODES RECOMMENDED TIMING VALUES SERIAL TEST MODE SIGNALS POLARITIES TESTMODE CYCLES RESET PHASE SYNCHRONIZATION PHASE REGISTERS INITIALIZATION COMMANDS USED TEST MODE
3.9.1 adr, 3.9.2
3.10REGISTER INITIALIZATION WITH INSTRUCTION 3.11PROGRAMMING WITH INSTRUCTION EPROM HANDLING EPROM PROGRAMMING OVERVIEW
4.1.1 ST63 EPROM Programming
EPROM PROGRAMMING SEQUENCE EPROM VERIFYING PROCEDURE
EPROM BLANK CHECK PROCEDURE
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Table Contents
EEPROM HANDLING EEPROM DESCRIPTION EEPROM WRITING SERIAL MODE EEPROM VERIFYING PROCEDURE OPTION BYTE HANDLING OPTION BYTE DESCRIPTION OPTION BYTE MODES READ OPTION BYTE MEMORY CELLS PROGRAM OPTION BYTE (TEST MODE) ST63 EPROM OPTION BYTE PROGRAMMING READ-OUT PROTECTION HARDWARE PROTECTION SOFTWARE PROTECTION APPENDIX APPENDIX ENVIRONMENT
Working environment Equipment Working station
APPENDIX LIST EXISTING DEVICES
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ST62 ST63 FAMILIES TECHNICAL OVERVIEW
TECHNICAL OVERVIEW
programming on-chip EPROM done using Data Window mechanism addressing memory cells. This done serial testmode offered microcontroller family (normally used testing devices factory). this mode, program independent existing ROM/EPROM content forced from outside into microcontroller executed similar customer program. Each instruction sequentially into device dedicated input line. device uses dedicated line output content Program Counter, some registers. These results have used control serial data flow instructions effects. synchronizing device with these instructions, clock driven test/programming equipment. EPROM MEMORY DESCRIPTION 2.1.1 EPROM management EPROM memory mapped inside program space ST6. addressed 12-bit Program Counter Register core directly address Kbytes program space. Nevertheless, program space extended addition Kbytes banks Program Page Register (PRPR) family data sheets further details programming, EPROM defined Data EPROM. This implies Data Window (DRWR) access EPROM. DRWR register addressed like location Data Space address C9h. This register used move 64-byte read-only data window (from address address Data Space) down EPROM memory steps bytes. effective address byte obtained concatenation Least Significant Bits data space address content DRWR register Most Significant Bits address) Using this address mode, content PRPR register more effect. Example: following sequence will read data byte stored EPROM byte address A19h write accumulator. DRWR, Content DRWR Data Space address Basic address window offset inside window.
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ST62 ST63 FAMILIES TECHNICAL OVERVIEW
DRWR (6:0)
DATA SPACE ADDRESS (5:0)
2.1.2 Reserved areas STMicroelectronics testing purposes, some memory areas reserved inside devices. These areas match exactly mapping version given below: Table EPROM/OTP Mapping
Memory Page Page Device Address 0000h 007Fh 0080h 07FFh 0800h 0F9Fh Page (Static Page) 0FA0h 0FEFh 0FF0h OFF7h 0FF8h 0FFBh 0FFCh 0FFFh Page Page 1000h 100Fh 1010h 17FFh 1800h 180Fh 1810h 1FFFh Description Reserved User User Reserved User Reserved User Reserved User Reserved User
ELECTRICAL CHARACTERISTIC Input output voltages normal functions pins follow data sheet device. 2.2.1 Absolute maximum ratings Voltage 7.0V Voltage 13.5V 2.2.2 Characteristics during programming characteristics which given below, operating temperature 25°C.
NAME 12.5 Min. 4.75 5.25 13.5 Unit
means Programming current
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ST62 ST63 FAMILIES SERIAL TEST MODE
SERIAL TEST MODE
order check devices production line, some special test modes have been implemented inside chips. They allow special checks onto EPROM cells like margin checks, gate drain stress, most particularly programming EPROM cells. this mode device behaviour entirely controlled external equipment therefore assumed this document that such tool available user/reader. This special tool must able handle relevant signals used testmode also provide power supplies chip. AFFECTED PINS SERIAL TEST MODE Some pins devices have special functions when used serial test mode: TM/VPP SDOP TROMIN OSCIN OSCOUT general test mode Programming power supply serial output serial input test mode select oscillator input oscillator output power ground (common VPP/TM)
enter serial test mode, certain voltage levels have applied these pins during reset phase device:
TM/VPP 0.5V. forced high during reset phase only could used later test program according normal function needed.
After reset phase, commands data have forced TROMIN serial synchronized with clock input ST6. other pins left floating. SDOP identical with pin, recommended program related data direction register normally output mode. test mode pins normally multiplexed with other input, output pins. each device type, this multiplexing hardwired affected customer ROM/ EPROM content.
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ST62 ST63 FAMILIES SERIAL TEST MODE
assignments test mode pins available ST62 EPROM devices shown below: Table ST62XX Assignments
DEVICES VPP/SDOP TROMIN OSCIN OSCOUT RESET
62T00C T01C T03C E01C 62T08C T09C T10C T20C E20C 62E18C T18C 62T15C T25C E25C 62T28C E28C 62T30B E30B 62T32B E32B 62T35B E35B 62T40B E40B 62T42B E42B 62T45B E45B 62T46B E46B 62T53B T60B T63B E60B T53C T60C T63C E60C 62T52B T62B E62B T52C T62C E62C 62T55B T65B E65B T55C T65C E65C 62T80B E80B 62T85B /E85B
these devices, these pins must connected VDD. assignments testmode pins available ST63 EPROM devices shown below: Table ST63XX Assignments
DEVICES 63E85/E87/63E76/E78 63E69 63E73 63E156 63E70H (PDIP 63E70J (PSDIP VPP/SDOP TROMIN OSCIN OSCOUT RESET
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ST62 ST63 FAMILIES SERIAL TEST MODE
RECOMMENDED INPUT LEVELS SERIAL TEST MODES test mode pins VPP/TM, TROMIN oscillator input signal must have input levels shown below, also case their normal function levels specified with different voltage values. Table Input levels serial test mode
VPP/TM2 TROMIN INPUT LOGIC LEVEL 0.7VDD 0.7VDD 0.7VDD 0.7VDD 0.4V 0.5V 0.5V 0.4V 0.5V 0.4V 0.5V
Input output voltages normal function pins, data sheet device. Above values valid temperatures range from +15°C +35°C. RECOMMENDED TIMING VALUES SERIAL TEST MODE test mode pins TROMIN oscillator input signal must follow recommended timings shown hereafter: Figure Recommended timing values serial test mode
XT1_START XT1_STOP
OSCIN TROM_START TROMIN SDOP STB_WIDTH
STROBE STB_START Cycle
VR02126C
Warning: TROMIN signal must mandatory change after rising edge clock signal.
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ST62 ST63 FAMILIES SERIAL TEST MODE
Table Timing values serial test mode frequencies 8MHz 4MHz
8MHz Cycle XT1_START XT1_STOP TROM_START STB_START STB_WIDTH
SIGNALS POLARITIES Depending device different signals used serial test mode have different polarities. They active '0'. ST62E2X/3X/4X/8X devices polarities following: OSCIN OSCOUT SDOP TROMIN active level active level active level active level active level
ST62E5XB/ E6XB devices, some signals have different polarity, that SDOP TROMIN active level active level
ST62E5XC/ E6XC devices, some signals have different polarity, that SDOP TROMIN active level active level
ST63EXX devices, some signals have different polarity, that SDOP TROMIN active level active level
Important note: operand code data TROMIN have inverted regarding values mentioned inside this documentation.
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ST62 ST63 FAMILIES SERIAL TEST MODE
TESTMODE CYCLES Each instruction consists ST62xx machine cycles. Each these machine cycles consists clock pulses T13:
During opcode, address data forced TROMIN, during MSB. During state maintained TROMIN reset
Figure Machine cycle
ST62 CORE CYCLE
CLOCK
TROMIN VR02126B
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ST62 ST63 FAMILIES SERIAL TEST MODE
RESET PHASE serial test mode activated reset phase device, depending voltage levels applied VPP/pins during this phase. During whole reset phase (RESET active ST6):
forced high. VPP/must TROMIN kept low.
RESET must kept during least achieve proper reset ST6. avoid race conditions, rising edge Reset signal must occur during phase clock input. soon logic level RESET '1', internal build-up counter will start. finish reset phase, necessary apply 2048 clock pulses clocks pulses first internal cycle called From this point, commands data have forced TROMIN serial synchronized with clock input. SDOP used watch program counter, serial data flow registers. Figure Reset phase timing
CLOCK
RESET
VPP/
VR02126
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ST62 ST63 FAMILIES SERIAL TEST MODE
SYNCHRONIZATION PHASE Once reset phase completed, necessary check device synchronized, meaning that reset phase been properly executed internal circuitry. synchronization check, operation used just after first internal cycle Opcode this operation therefore sufficient keep TROMIN level like during reset phase. operation uses machine cycles called CYC1 CYC5. long TROMIN tied low, will repeat CYC1/CYC5 sequence. After Reset, Program Counter FFEh. Each operation will increase Program Counter one. value shifted SDOP pin, LSBit first, starting with therefore checked used synchronization. During CYC5, current complete value shifted bits during T12), last signification. table summarizing RESET extended SYNCHRONIZATION phase given below:
high high RESET pos.edge high CLOCK (OSCIN) some pulses high
TROMIN
SDOP
CYCLE
WHAT
Start-up Phase CYCI CYC1 CYC5 CYC1 CYC5 CYC1 CYC5 CYC1 CYC5 CYC1 check synchronization check synchronization check synchronization check synchronization FFFh
Pulses
Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses
REGISTERS INITIALIZATION Watchdog Register must initialized after synchronization phase order guarantee proper operation device. Watchdog Register programmed order inactive. hardware watchdog, necessary refresh regularly. This done same time DRWR changed every scope bytes program. mandatory with devices, recommended avoid possible problems with devices having hardware watchdog.
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ST62 ST63 FAMILIES SERIAL TEST MODE
COMMANDS USED TEST MODE Table below shows some commands useful programming device allowed serial test mode. assumed, that command well known. Table most important commands serial test
COMMAND adr, adr, CYCLE1 CYCLE2 n.e. n.e. n.e. CYCLE3 CYCLE4 CYCLE5
n.e.
don't care existent this command
opcodes, addresses data shifted TROMIN first last. Other commands, data sheet. Important note:All input TROMIN inverted polarity negative! 3.9.1 adr, This command writes 8-bit data into data space address adr. used initialization registers programming EPROM bytes. Depending use, data forced TROMIN different times. command consists bytes (opcode, destination address, operand) executed four machine cycles. During first cycle (CYC1), opcode (ODh, 8bit) loaded into microprocessor TROMIN second cycle (CYC3) address (8bit).
When using this command register initialization, third cycle (CYC4) works only internally, input TROMIN required. fourth cycle (CYC5), data forced serially TROMIN pad. pulse this cycle, data stored register. When using this command programming, data programmed forced TROMIN during third cycle (CYC4). fourth cycle (CYC5), TROMIN kept low.
3.9.2 This command reads content data space register accumulator used reading out, verifying blank checking EPROM content. command consists bytes execution needs four machine cycles again. first cycle, opcode (1Fh, 8bit) driven TROMIN, second cycle address (8bit). remaining cycles, needs more inputs from outside. During last cycle, data space register content shifted SDOP read.
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ST62 ST63 FAMILIES SERIAL TEST MODE
3.10 REGISTER INITIALIZATION WITH INSTRUCTION After initialization, Data Window Register (DRWR) loaded first. normal address this register (write only register) 0C9h. Programming done scopes bytes (40h 7Fh). scopes (blocks) will selected content DRWR. number scopes depends from EPROM size! (00h-1Fh) 2k-EPROM (00h-3Fh) 4k-EPROM (00h-7Fh) 8k-EPROM Important notes:
bytes every scope data space address 40h-7Fh. DRWR must loaded with instruction. opcodes, addresses data must shifted serially TROMIN LSBit first MSBit last. instruction consists four machine cycles. Each this cycle consists clock pulses T13. forcing opcodes, addresses data takes always place from during state MSBit maintained TROMIN. shifting data SDOP always starts LSBit. Polarity SDOP taken into account.
Machine cycles description Machine Cycle (CYC1) During first eight OSCIN pulses CYC1, opcode (0Dh) shifted into TROMIN pin, same time, result previous operation shifted SDOP. During final five OSCIN cycles TROMIN kept low. Machine Cycle (CYC3) During first eight OSCIN pulses machine cycle CYC3, address Data Window Register shifted into TROMIN. During same time, least significant eight bits shifted out, value must greater than from preceding machine cycle. This should used verify that process still synchronized. During final five OSCIN cycles, TROMIN kept low. Machine Cycle (CYC4) During next thirteen OSCIN pulses, TROMIN pulled VIL. most cases, useful data shifted SDOP pin.
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ST62 ST63 FAMILIES SERIAL TEST MODE
Machine Cycle (CYC5) During first eight OSCIN pulses machine cycle CYC5, content Data Window Register shifted into TROMIN. (This scope number). Latest now, programming voltage must applied PP/pin. During last five pulses TROMIN pulled low. Table below summarizes these actions: Table Initialization phase
CYCLE CYC1 CYC3 CYC4 CYC5 TROMIN Register address (0C9h DRWR) Don't care Data written into register (Scope number DRWR) Data (register contents readable registers only) INFORMATION SDOP Result previous operation first LSBits program counter (PC) Synchronization check used USED
3.11 PROGRAMMING WITH INSTRUCTION After initialization Data Window Register with scope number, bytes pointed DRWR programmed using load immediate instruction (LDI). Important notes:
aware that actual programming done during CYC4 clock that phase this clock must extended time 12.5 Volts. necessary write bytes EPROM memory particular order. instruction normally used programming, however instruction which access address range 40h-7Fh while Volts will initiate programming cycle. Take care that instructions other than produce unexpected results.
Machine cycle description Machine Cycle During first eight OSCIN pulses CYC1, opcode (0Dh) shifted into TROMIN pin. During final five OSCIN pulses TROMIN kept level. data shifted SDOP delayed instruction. There limit established number write attempts, data been correctly retained after fifth attempt, programming should abandoned error reported.
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ST62 ST63 FAMILIES SERIAL TEST MODE
Machine Cycle During first eight OSCIN cycles machine cycle address (pointer Data ROM) shifted into TROMIN pin, same time order eight bits shifted SDOP pin. address shifted SDOP used verify that processor properly synchronized. expected value process should abandoned restarted. During final five OSCIN cycles TROMIN kept level. Machine Cycle During next eight OSCIN cycles, data programmed shifted into TROMIN pin. same time, contents Data byte shifted SDOP pin. erased part being programmed then byte should equal 00h, not, programming should normally suspended. part might erased with longer exposure Ultraviolet flux discarded, appreciated. During final five OSCIN cycles TROMIN kept level. useful data shifted from SDOP during these OSCIN cycles. Machine Cycle During this cycle TROMIN signal kept current value (MSBit previous cycle) effect. useful data shifted from SDOP during these OSCIN cycles. After programming first bytes Data Window Register loaded with next scope value then next bytes programmed. voltage VPP/pin kept (12.5/13 Volts) programming time even during initialization Data Window Register. Table below summarizes these actions: Table EPROM byte programming
CYCLE CYC1 CYC3 CYC4 CYC5 TROMIN Data (40h first) Data program into EPROM cell Don't care INFORMATION SDOP Result previous operation first LSBits Content EPROM cell before programming Synchronization check Blank check USED
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ST62 ST63 FAMILIES EPROM HANDLING
EPROM HANDLING
EPROM PROGRAMMING OVERVIEW complete sequence programming device split different phases: Reset phase This performs entry serial mode test. Synchronization phase This checks device synchronization.
Registers initialization This guarantees proper reset conditions device. DRWR initialization 3.10 This sets data window first scope bytes. Programming bytes inside current data window. This actual programming sequence. Notes:
3.11
program entire device, DRWR must programmed with consecutive values once bytes, pointed window, have been programmed. Each defective byte rewrite times before aborting programming sequence. recommended apply security programming count after successful programming EPROM byte. This will enforce cell margin.
simplify flow chart below, describes algorithm apply programming entire device. example given Kbytes device. This concerns only main part sequence: EPROM programming. Data Window Register first initialized with basic address first scope bytes EPROM. example device Kbytes device, means that EPROM located from 800h FFFh, first window located address 20h. Then these bytes programmed after others. fact inside this flow chart, represented possible retry programming byte programmed times before declared defective) security programming count. Once whole window been programmed, DRWR reprogrammed with next one. This outer loop repeated till EPROM space.
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ST62 ST63 FAMILIES EPROM HANDLING
Figure Programming Flowchart
STARTUP
SYNCHRO.
DRWR
ADDRESS EPROM BYTE INSIDE DATA WINDOW
PROG. BYTE
PROGRAM NEXT BYTE (TOTAL 40h)
DRWR DRWR KBYTES EPROM: NUMBER INNER LOOPS NUMBER OUTER LOOPS
DRWR
VR02126A
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ST62 ST63 FAMILIES EPROM HANDLING
4.1.1 ST63 EPROM Programming programming EPROM done same other members family. With Data Window Register (C8h), able reach addresses (4000h). extension memory done with additional register CAh. EPROM PROGRAMMING SEQUENCE following table gives complete programming sequence devices. must adapted programming SDOP output. This location depends device type. following sequence example used ST62E20 where SDOP port that Data Direction Register address 0C5h value program 80h. symbol inside this table means that value read real signification.
RESET CLOCK (OSCIN) some pulses high Pulses Pulses Pulses TROMIN SDOP CYCLE WHAT Start-up Phase high high pos. edge high CYCI CYC1 Synchronization Pulses Pulse Pulses Pulses Pulses Pulses Pulses Pulses Pulses 0D8h FFFh CYC5 CYC5 Watchdog Register CYC1 CYC1 CYC3 CYC3 CYC4 CYC5 CYC5 Restart value Check writing result instruction into TROMIN restart watchdog Check LSBits shift watchdog register address Check synchronization FFFh Build counter First internal cycle
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ST62 ST63 FAMILIES EPROM HANDLING
RESET
CLOCK (OSCIN)
TROMIN SDOP
CYCLE
WHAT Data Window Register
Pulses Pulses Pulses Pulses Pulses Pulses
(DRWR) address (C9h) (DRWR) (DRWR) content content
instruction into TROMIN (LSB first) CYC1 first Data Window Register, normally zero CYC1 Check Synchr. SDOP. Shift address CYC3 Data ROM. Window Register into TROMIN CYC3 CYC4 CYC5 Check function TROMIN SDOP internal shift register Apply initial content DRWR (normally zero) TROMIN verify SDOP CYC5 Switch 12.5V Programming First Byte Shift opcode instruction into TROMIN. Program first EPROM byte bytes block Check synchr. SDOP CYC3 Shift address first Data EPROM byte into TROMIN (normally 40). first. CYC3 (00) CYC4 CYC4 Blank check SDOP. Shift data programmed. Extend phase pulse about msec EPROM byte writing. Check whether shifting into TROMIN done correctly. verify: check shift register only. Switch -0.5V
(00) 12.5V Pulses
(00)
Pulses Pulses Pulses Pulses Pulses Pulses
window address (EDAT)
CYC1 CYC1
Pulses -0.5V Pulses
EDAT
CYC5 CYC5
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ST62 ST63 FAMILIES EPROM HANDLING
RESET
CLOCK (OSCIN) Pulses Pulses Pulses Pulses Pulses Pulses
TROMIN SDOP
CYCLE
WHAT Verifying First Byte
window address
CYC1 CYC1 CYC3 CYC3
Shift opcode instruction Shift address first Data byte into TROMIN (normally 40h)
EDAT
CYC4 CYC5 CYC5 Retrieve EPROM content SDOP. read value compared with programmed before same location Switch 12.5V Programming Second Byte Shift opcode instruction into TROMIN. Program first EPROM byte bytes block
12.5V
Pulses
Pulses Pulses Pulses Pulses Pulses Pulses
window address (EDAT)
CYC1 CYC1
Check synchr. SDOP CYC3 Shift address first Data EPROM byte into TROMIN (normally 40). first. CYC3 Blank check SDOP. Shift data programmed. Extend phase pulse about msec EPROM byte writing. Check whether shifting into TROMIN done correctly. verify: check shift register only.
(00)
CYC4 CYC4
Pulses Pulses
EDAT
CYC5 CYC5
After each bytes block bank register value.
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ST62 ST63 FAMILIES EPROM HANDLING
EPROM VERIFYING PROCEDURE Once entire EPROM space programming completed, necessary perform verify entire space order quite sure correct programming. complete sequence verifying device similar programming least first phases: Reset phase This performs entry serial mode test. Synchronization phase This checks device synchronization.
Registers initialization This guarantees proper reset conditions device. DRWR initialization 3.10 This sets data window first scope bytes. difference with programming concerns points described below:
voltage maintained 0.5V during operation. access EPROM content done with instruction 3.9.2 instead instruction. During last cycle this instruction, EPROM byte content will shifted out, LSBit first, therefore checked with programmed value.
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ST62 ST63 FAMILIES EPROM HANDLING
table below describes complete sequence verifying device.
high high CLOCK TROMIN (OSCIN) some pulses pos.edge high high Pulses Pulses Pulses RESET SDOP CYCLE WHAT Start-up Phase Build counter First internal cycle Synchronization Check synchronization FFFh
CYCI CYC1
Pulses Pulse LIKE PROGRAMMING SEQUENCE Pulses Pulses Pulses Pulses Pulses Pulses
(DRWR) address
FFFh
CYC5 CYC5
REGISTER Initialization Watchdog Register Data Window Register instruction into TROMIN Check Synchr. SDOP Shift address Data Window Register into TROMIN
CYC1 CYC1 CYC3 CYC3 CYC4 CYC5
(DRWR) (DRWR) content content (00) (00)
Check function TROMIN SDOP internal shift register Apply initial content DRWR (normally zero) TROMIN verify SDOP Verifying First Byte Shift opcode instruction Shift address first Data byte into TROMIN (normally 40h)
Pulses Pulses Pulses Pulses Pulses Pulses
window address
CYC5 CYC1 CYC1 CYC3 CYC3 CYC4 Retrieve EPROM content SDOP. read value compared with programmed before same location
Pulses
EDAT
CYC5
Pulses CYC5 verification correct, continue with next byte inside window. After each bytes, bank register value.
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ST62 ST63 FAMILIES EEPROM HANDLING
EPROM BLANK CHECK PROCEDURE perform blank check entire device, same procedure verifying EPROM used. only difference consists EPROM content comparison that must done against blank value device. Important notes:
blank value byte 00h. Blank checking must done with equal DD-0.5V Volts.
EEPROM HANDLING
EEPROM DESCRIPTION EEPROM family addressed using banks bytes located between addresses 3Fh. selection bank made programming Data Bank Register (DRBR) located inside data space. This register used select desired bytes EEPROM bank Data Space. number bank loaded DRBR instruction point selected location bank (from addresses 3Fh). this register only must time, otherwise more pages enabled parallel, producing errors. devices data sheet further information DRBR EEPROM controlled EEPROM Control Register (EECTL). Only bits this register have used EEPROM writing: (Enable) This MUST order write EEPROM location. (Busy) This automatically internal EEPROM logic when write operation going. polled order detect completion operation.
writing byte made simply executing load instruction, after verifying that other write operation progress (using EECTL). hardware mechanism prevents make double programming attempt program's responsibility avoid this situation. NOTE: Depending devices, registers addresses EEPROM bytes count different. Please, refer device data sheet them.
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ST62 ST63 FAMILIES EEPROM HANDLING
EEPROM WRITING SERIAL MODE serial mode used program, similar EPROM, EEPROM devices. write operation done like normal mode, that usual program writing inside EEPROM forced serially TROMIN after testmode start synchronization phases. EEPROM writing performed followed: Reset phase This performs entry serial mode test. Synchronization phase This checks device synchronization.
Registers initialization This guarantees proper reset conditions device. EEPROM writing operation validated This enables writing operation EEPROM. DRBR initialization This sets data window first EEPROM bank bytes. EEPROM byte writing This split different steps:
Actual write EEPROM location performed loading EEPROM location with value write, using instruction EEP_ADR, EEP_DAT Polling busy EECTL order detect operation. this done instruction EECTL. During last cycle this instruction, register content will shifted out, LSBit first, therefore busy (bit checked.
These steps have repeated each byte inside selected bank, then DRBR reprogrammed with bank number order select scope bytes. NOTE: there internal charge pump providing high voltage necessary program EEPROM cells, there need apply programming voltage device when accessing EEPROM.
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ST62 ST63 FAMILIES EEPROM HANDLING
table below describes complete sequence writing EEPROM device.
high high RESET pos.edge high CLOCK (OSCIN) some pulses high
TROMIN
SDOP
CYCLE
WHAT Start-up Phase Build counter
Pulses
Pulses Pulses
CYCI CYC1
First internal cycle Synchronization
Pulses Pulse LIKE PROGRAMMING SEQUENCE Pulses Pulses Pulses Pulses Pulses Pulses Pulses
EECTL address
FFFh
CYC5 CYC5
Check synchronization FFFh
REGISTER Initialization Watchdog Register Enable EEPROM Writing CYC1 CYC1 CYC3 CYC3 CYC4 CYC5 CYC5 Data Bank Register Check EECTL writing shift into TROMIN Check synchr. SDOP Enable Shift EECTL address check synchr. SDOP Shift opcode instruction
Pulses Pulses
CYC1 CYC1
Pulses
DRBR
CYC3
Shift address Data Bank Register into TROMIN (normally 40h)
Pulses Pulses Pulses Pulses
content (01)
CYC3 CYC4 Apply initial content DRBR CYC5 (bank number) TROMIN verify SDOP CYC5 Writing First Byte
(DRBR) (DRBR) (01)
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ST62 ST63 FAMILIES EEPROM HANDLING
RESET
CLOCK (OSCIN) Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses
TROMIN EEPROM address EEDAT EECTL address
SDOP
CYCLE CYC1 CYC1
WHAT Shift opcode instruction Program first EEPROM byte Shift address first Data
CYC3 CYC3
EEPROM byte into TROMIN (normally 00h)
EEDAT
CYC4 CYC5 CYC5 Check Busy Byte CYC1 CYC1 CYC3 CYC3 Check LSBits shift EECTL address Shift opcode instruction Shift EEPROM data write
CYC4
Retrieve EECTL content SDOP. busy checked. While this instruction looped.
Pulses
(EECTL) content
CYC5
Pulses
CYC5
When Busy reset, continue with next byte inside current window. After each bytes, Data bank register value.
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ST62 ST63 FAMILIES EEPROM HANDLING
EEPROM VERIFYING PROCEDURE Once entire EEPROM space writing completed, necessary perform verify entire space order quite sure correct writing. complete sequence verifying device similar writing least first phases: Reset phase This performs entry serial test mode. Synchronization phase This checks device synchronization.
Registers initialization This guarantees proper reset conditions device. DRBR initialization This sets data window first EEPROM bank bytes. difference with writing operation concerns points described below:
into EECTL register does need programmed write will performed EEPROM. access EEPROM content done with instruction (-See 3.9.2-) During last cycle this instruction, EPROM byte content will shifted out, LSBit first, therefore checked against written value.
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ST62 ST63 FAMILIES EEPROM HANDLING
table below describes complete sequence verifying device.
high high RESET pos.edge high CLOCK (OSCIN) some pulses high
TROMIN
SDOP
CYCLE
WHAT Start-up Phase Build counter
Pulses
Pulses Pulses
CYCI CYC1
First internal cycle Synchronization
Pulses Pulse LIKE PROGRAMMING SEQUENCE Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses Pulses
DRBR
FFFh
CYC5 CYC5
Check synchronization FFFh
REGISTER Initialization Watchdog Register Data Bank Register CYC1 CYC1 CYC3 CYC3 CYC4 CYC5 CYC5 Verifying First Byte CYC1 CYC1 CYC3 CYC3 EDAT CYC4 CYC5 CYC5 Retrieve EEPROM content SDOP. read value compared with written before same location Shift address first Data EEPROM byte into TROMIN (normally 00h) Shift opcode instruction Apply initial content DRBR (bank number) TROMIN verify SDOP Check synchr. SDOP Shift address Data Bank Register into TROMIN instruction into TROMIN
(DRBR) (DRBR) content EEPROM address
verify correct, continue with next byte inside window. After each bytes, bank register value.
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ST62 ST63 FAMILIES OPTION BYTE HANDLING
OPTION BYTE HANDLING
mask options that selected user devices emulated EPROM devices EPROM code byte that programmable serial test mode. OPTION BYTE DESCRIPTION There exists types Option Byte over family: DYNAMIC STATIC one. static based latch, with EPROM cells permanently read while dynamic consists EPROM cell read reset. static type, these EPROM cells master one, other slave one. value each option -well- defined when EPROM cells programmed while other still erased. programming option byte bits), must program both corresponding addresses this option byte) with complementary content. content master cell agrees value datasheet content slave complement. access each option performed through some lines EPROM matrix. addresses EPADR[0-11] which reach option byte described table below. Table ST62 Option Byte addresses
DEVICES ST62T0X, T1X, ST62E0X, E1X,
ST62T0XC E0XC ST62T1XC E1XC ST62T2XC E2XC
OPTION BYTE
Master Slave
OPTIONS
ADDRESS
Option Byte available* Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master (dynamic type) Master Slave Master Slave Master Slave [0:7] [0:7] [8:15] [8:15] [0:7] [0:7] [8:15] [8:15] [0:7] [0:7] [0:7] [0:7] [0:7] [0:7] [0:7] [8:15] [8:15] [0:7] [0:7] F80h B80h 780h 380h 1700h 700h 1700h 700h B80h 1700h 700h
ST62T28C E28C
ST62T3XB E3XB ST62T4XB E4XB ST62T5XB E5XB ST62T6XB E6XB ST62T5XC E5XC ST62T6XC E6XC
ST62T8XB E8XB
*product termination progress
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ST62 ST63 FAMILIES OPTION BYTE HANDLING
option byte accessed serial mode once Interrupt Option Register (address 0C8h) been set. This (called MDIS) selects special EPROM matrix inside chip where located option byte. only possible this test mode, user mode affected. further information options bytes, data sheet devices. operations (programming, verifying, blank check) performed option byte same procedure same algorithm normal EPROM have used. Only points slightly different:
must programmed with registers initialization phase (instead 00h). access this register must done with 0.5V. programming time (low phase 13th pulse CYC4 actual programming instruction) extended milliseconds.
OPTION BYTE MODES Here after described different option byte modes registers value order access them: Table Option byte modes
MDIS IOR[7] Mode Read Option Byte EPROM cells Program Option Byte EPROM cells
READ OPTION BYTE MEMORY CELLS reading option byte value performed read EPROM matrix byte. Before reading byte, enter matrice disable mode (MDIS=1) setting IOR[7]. Select appropriate Data Window order access correct option byte (refer Table 10). Then, (for ST62E2X), read adr) from Data Window content option byte needed address 0380h 0B80h both option bytes (0780h 0F80h contains complementary values.)
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ST62 ST63 FAMILIES Read-out protection
PROGRAM OPTION BYTE (TEST MODE) programming option byte performed programming matrix EPROM byte. First, apply Volts VPP. Before programming byte, enter matrix disable mode (MDIS=1) setting IOR[7]. Select appropriate Data Window order access correct option byte (refer Table 10). Then, execute write instruction (LDI adr, #data) into Data Window. order program option byte, "write" instruction must performed exactly programming sequence (refer chapter programming sequence). ST63 EPROM OPTION BYTE PROGRAMMING programming procedure this byte same used ST62 (With management MDIS Register C9h) setting Register CAh. Table ST63 Option Byte addresses
DEVICE ST63E71/73 ST63E76/78 ST63E85/87 ST63E156 Master Slave OPTIONS [0:7] [0:7] [0:7] [0:7] ADDRESS 1700h 1700h 4B80h 4B80h
READ-OUT PROTECTION
HARDWARE PROTECTION Hardware read-out protection achieved ST62 devices thanks option byte. read-out protection effective soon relevant option byte programmed (see datasheet further information). Once programmed, this disables access program memory serial testmode. Thus, more possible read device content. More precisely, whole program memory space will then read 0FFh. whole option byte content programmed single pass. However, recommended separate operations, since setting hardware read-out protection prevents read option byte. protection isn't set, corresponding Slave address exists) must order keep complementary content between Master Slave.
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ST62 ST63 FAMILIES Read-out protection
SOFTWARE PROTECTION When there option byte devices, hardware read-out protection possible. Then bytes dedicated implement software read-out protection. This concerns ST62 devices without option byte which production been stopped 1997. programming tool must able handle this feature following manner: Program these bytes protect devices requested customer. Refuse read-out devices these bytes have been previously programmed. This will ensure compatibility with STMicroelectronics programmers. relevant addresses 0FFAh 0FEFh. Both addresses reserved areas, that their programming will corrupt device behaviour inside customer application. These bytes allow management both EPROM device followed: 0FFAh content 00h, device unprotected read. 0FFAh nibble content equal byte 0FEFh tested. (Case device). 0FEFh content device unprotected. other cases, device considered protected. These bytes have checked programmed test equipment order implement this SOFTWARE protection. they normal EPROM bytes, programming verifying phases must respect EPROM algorithm described previous chapters. Regarding above description, appears that order protect devices, address 0FFAh address 0FEFh case OTP) programmed with 0FFh.
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ST62 ST63 FAMILIES Appendix
APPENDIX
APPENDIX ENVIRONMENT Working environment These recommendations list major points defined CECC00015 specifications named "Protection electrostatic sensitive devices". Refer this document detailed information. Equipment equipment, tools instruments used during programming flow must connected ground. Working station working station must antistatic. This station include table with conductive material, covered with antistatic (surface resistivity <0.5 connected ground conductor cable series with resistance. include also antistatic ground carpet grounded conductive cable (0.9 usage grounded antistatic armlet connected grounded equipment mandatory. Antistatic gloves, finger coats, also required. plastic object station must antistatic material. APPENDIX LIST EXISTING DEVICES Hereafter given list existing devices family that order with request form attached this document. This list exhaustive allows components able emulate other existing type.
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ST62 ST63 FAMILIES Appendix
Table List ST62 devices with option byte
MASTER DEVICE DEVICE ST62T00C ST62T00C ST62T01C ST62T01C ST62T01C ST62T03C ST62T03C ST62T08C ST62T08C ST62T09C ST62T20C ST62T09C ST62T10C ST62T10C ST62T20C ST62T20C ST62T15C ST62T25C ST62T15C ST62T25C ST62T25C ST62T18C ST62T28C ST62T30B ST62T32B ST62T35B ST62T40B ST62T42B ST62T45B ST62T46B ST62T18C ST62T18C ST62T28C ST62T28C ST62T30B ST62T30B ST62T32B ST62T32B ST62T35B ST62T40B ST62T42B ST62T45B ST62T46B PACKAGE PDIP16 PSO16 PDIP16 PSO16 PDIP16 PSO16 PDIP20 PSO20 PDIP20 PSO20 PDIP20 PSO20 PDIP20 PSO20 PDIP28 PSO28 PDIP28 PSO28 PDIP20 PSO20 PDIP28 PSO28 PDIP28 PSO28 PSDIP42 PQFP52 PQFP52 PQFP80 PQFP64 PQFP52 SDIP56 PART-NUMBER ST62T00CB6 ST62T00CM6 ST62T01CB6 ST62T01CM6 ST62T03CB6 ST62T03CM6 ST62T08CB6 ST62T08CM6 ST62T09CB6 ST62T09CM6 ST62T10CB6 ST62T10CM6 ST62T20CB6 ST62T20CM6 ST62T15CB6 ST62T15CM6 ST62T25CB6 ST62T25CM6 ST62T18CB6 ST62T18CM6 ST62T28CB6 ST62T28CM6 ST62T30BB6 ST62T30BM6 ST62T32BB6 ST62T32BQ6 ST62T35BQ6 ST62T40BQ6 ST62T42BQ6 ST62T45BQ6 ST62T46BB6 supplied samples supplied samples supplied samples upon specific request upon specific request supplied samples upon specific request upon specific request upon specific request supplied samples supplied samples supplied samples SAMPLES AVAILABILITY
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ST62 ST63 FAMILIES Appendix
MASTER DEVICE
DEVICE ST62T53B ST62T53B ST62T60B ST62T60B ST62T63B ST62T63B ST62T52B ST62T62B ST62T55B ST62T55B ST62T65B ST62T65B ST62T53C ST62T53C ST62T60C ST62T60C ST62T63C ST62T63C ST62T52C ST62T52C ST62T62C ST62T62C ST62T55C ST62T55C ST62T65C ST62T65C ST62T80B ST62T85B
PACKAGE PDIP20 PSO20 PDIP20 PSO20 PDIP20 PSO20 PSO16 PSO16 PDIP28 PSO28 PDIP28 PSO28 PDIP20 PSO20 PDIP20 PSO20 PDIP20 PSO20 PDIP16 PSO16 PDIP16 PSO16 PDIP28 PSO28 PDIP28 PSO28 PQFP100 PQFP80
PART-NUMBER ST62T53BB6 ST62T53BM6 ST62T60BB6 ST62T60BM6 ST62T63BB6 ST62T63BM6 ST62T52BM6 ST62T62BM6 ST62T55BB6 ST62T55BM6 ST62T65BB6 ST62T65BM6 ST62T53CB6 ST62T53CM6 ST62T60CB6 ST62T60CM6 ST62T63CB6 ST62T63CM6 ST62T52CB6 ST62T52CM6 ST62T62CB6 ST62T62CM6 ST62T55CB6 ST62T55CM6 ST62T65CB6 ST62T65CM6 ST62T80BQ6 ST62T85BQ6
SAMPLES AVAILABILITY
ST62T60B*
upon specific request
ST62T62B*
upon specific request
ST62T65B*
upon specific request
ST62T60C
supplied samples
ST62T62C
supplied samples
ST62T65C
supplied samples
ST62T80B ST62T85B
supplied samples upon specific request
termination progress, replaced version
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ST62 ST63 FAMILIES Appendix
Table List ST62 devices without option byte
MASTER DEVICE DEVICE ST62T00/xxx ST62T00/xxx ST62T01B6/HWD* ST62T01/xxx ST62T01/xxx ST62T03/xxx ST62T03/xxx ST62T08/xxx ST62T08/xxx ST62T09/xxx ST62T20B6/HWD* ST62T09/xxx ST62T10/xxx ST62T10/xxx ST62T20/xxx ST62T20/xxx ST62T15/xxx ST62T25B6/HWD* ST62T15/xxx ST62T25/xxx ST62T25/xxx PACKAGE PDIP16 PSO16 PDIP16 PSO16 PDIP16 PSO16 PDIP20 PSO20 PDIP20 PSO20 PDIP20 PSO20 PDIP20 PSO20 PDIP28 PSO28 PDIP28 PSO28 PART-NUMBER ST62T00B6/xxx ST62T00M6/xxx ST62T01B6/xxx ST62T01M6/xxx ST62T03B6/xxx ST62T03M6/xxx ST62T08B6/xxx ST62T08M6/xxx ST62T09B6/xxx ST62T09M6/xxx ST62T10B6/xxx ST62T10M6/xxx ST62T20B6/xxx ST62T20M6/xxx ST62T15B6/xxx ST62T15M6/xxx ST62T25B6/xxx ST62T25M6/xxx upon specific request upon specific request SAMPLES AVAILABILITY
termination progress, replaced version. xxx: version
Table List ST63 devices
MASTER DEVICE ST63T73 ST63T78 ST63T85 ST63T87 ST63T88 ST63T89 ST63T156 DEVICE ST63T73 ST63T78 ST63T85 ST63T87 ST63T88 ST63T89 ST63T156 PACKAGE PSDIP42 PSDIP42 PSDIP42 PSDIP42 PSDIP42 PSDIP42 PDIP40 PART-NUMBER ST63T73J5B1 ST63T78B1/xxx ST63T85B1/xxx ST63T87B1/xxx ST63T88B1 ST63T89B1 ST63T156B1/xxx
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ST62 ST63 FAMILIES Appendix
REQUEST PROGRAMMING ALGORITHM STMicroelectronics mail STMicroelectronics Avenue Martyrs 38019 GRENOBLE CEDEX FRANCE Attn: Development Tools AUCLAIR
YES, wish automatically receive version Programming Algorithm when released.
Please send samples devices addition devices have already received. Master Device Name:
(See list existing devices Appendix ST62EXX Programming Specification)
USER REGISTRATION DATA Name: Company: Address: City: code: .State: .Country:
Telephone number: number:
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ST62 ST63 FAMILIES Appendix
Notes:
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics ©1998 STMicroelectronics Rights Reserved. Purchase Components STMicroelectronics conveys license under Philips Patent. Rights these components system granted provided that system conforms Standard Specification defined Philips. STMicroelectronics Group Companies Australia Brazil Canada China France Germany Italy Japan Korea Malaysia Malta Mexico Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A. http://www.st.com
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