GM71V18163C GM71VS18163CL 1,048,576 WORDS CMOS DYNAMIC Featu
|
|
|
Top Searches for this datasheet
GM71V(S)18163C/CL generation dynamic organized 1,048,576 bit. GM71V(S)18163C/CL realized higher density, higher performance various functions utilizing advanced CMOS process technology. GM71V(S)18163C/CL offers Extended Data out(EDO) Mode high speed access mode. Multiplexed address inputs permit GM71V(S)18163C/CL packaged standard 42pin plastic SOJ, standard 400mil 44(50)pin plastic TSOP package size provides high system densities compatible with widely available automated testing insertion equipment.
GM71V18163C GM71VS18163CL
1,048,576 WORDS CMOS DYNAMIC
Features
1,048,576 Words Organization Extended Data Mode Capability Single Power Supply (3.3V+/-0.3V) Fast Access Time Cycle Time
(Unit:
tRAC tCAC
GM71V(S)18163C/CL-5 GM71V(S)18163C/CL-6 GM71V(S)18163C/CL-7
tHPC
Configuration
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
Power Active 684/612/540mW (MAX) Standby 7.2mW (CMOS level MAX) 0.83mW (L-version MAX) Only Refresh, before Refresh, Hidden Refresh Capability inputs outputs Compatible 1024 Refresh Cycles/16ms 1024 Refresh Cycles/128ms (L-version) Self Refresh Operation (L-version) Battery Back Operation (L-version) byte Control
44(50) TSOP
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 LCAS UCAS
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8
LCAS UCAS
(Top View)
Semicon
GM71V18163C GM71VS18163CL
A0-A9 A0-A9 I/O0-I/O15 UCAS, LCAS
Function
Address Inputs Refresh Address Inputs Data-In/Out Address Strobe Column Address Strobe
Function
Read/Write Enable Output Enable Power (+3.3V) Ground Connection
Ordering Information
Type
GM71V(S)18163CJ/CLJ GM71V(S)18163CJ/CLJ GM71V(S)18163CJ/CLJ GM71V(S)18163CT/CLT GM71V(S)18163CT/CLT GM71V(S)18163CT/CLT
Access Time
50ns 60ns 70ns 50ns 60ns 70ns
Package
Plastic 44(50) Plastic TSOP
Absolute Maximum Ratings*
Symbol TSTG VIN/OUT IOUT Parameter
Ambient Temperature under Bias Storage Temperature Voltage Relative Supply Voltage Relative Short Circuit Output Current Power Dissipation
Rating
-0.5 Vcc+0.5 (<=4.6V(MAX)) -0.5
Unit
Note: Operation above Absolute Maximum Ratings adversely affect device reliability.
Semicon
GM71V18163C GM71VS18163CL
Recommended Operating Conditions 70C)
Symbol Parameter
Supply Voltage Input High Voltage Input Voltage
-0.3
Unit
Note: voltage referred Vss. supply voltage with pins must same level. supply voltage with pins must same level.
Truth Table
LCAS
UCAS
Output
Open Valid Valid Valid Open Open Open Undefined Undefined Undefined Valid Valid Valid Open Open Open Open Open
Operation
Standby Lower byte Upper byte Word Lower byte Upper byte Word Lower byte Upper byte Word Lower byte Upper byte Word Word Word Word Word Refresh Self Refresh (L-series) RAS-only Refresh cycle Read-modify -write cycle Delayed Write cycle Early write cycle Read cycle
Notes
1,2,3
1,2,3
Read cycle (Output disabled)
Notes: High (inactive) Low(active) tWCS Early write cycle tWCS Delayed write cycle Mode determined function UCAS LCAS. (Mode earliest UCAS LCAS active edge reset latest UCAS LCAS inactive edge.) However write OPERATION output High-Z control done independently each UCAS,LCAS. UCAS LCAS then CAS-before-RAS refresh cycle selected.
Semicon
GM71V18163C GM71VS18163CL
Electrical Characteristics (VCC 3.3V+/-0.3V, 70C)
Symbol ICC1 Parameter
Output Level Output Level Voltage (IOUT -2mA) Output Level Output Level Voltage (IOUT 2mA) Operating Current Average Power Supply Operating Current (RAS, UCAS LCAS Cycling: min) Standby Current (TTL) Power Supply Standby Current (RAS, UCAS, LCAS VIH, DOUT High-Z) Only Refresh Current Average Power Supply Current Only Refresh Mode (tRC min) Page Mode Current Average Power Supply Current Page Mode (tHPC tHPC min) Standby Current (CMOS) Power Supply Standby Current (RAS, UCAS LCAS 0.2V, DOUT High-Z) CAS-before-RAS Refresh Current (tRC min) 50ns 60ns 70ns 50ns 60ns 70ns 50ns 60ns 70ns
50ns 60ns 70ns
Unit
Note
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
Battery Back Operating Current(Standby with Ref.) (CBR refresh, tRC=125us, tRAS<=0.3us, DOUT=High-Z, CMOS interface) Standby Current UCAS, LCAS DOUT Enable Self-Refresh Mode Current (RAS, UCAS LCAS<=0.2V, DOUT=High-Z) Input Leakage Current Input (0V<=VIN<= 4.6V) Output Leakage Current (DOUT Disabled, 0V<=VOUT<= 4.6V)
ICC8
ICC9 IL(I) IL(O)
Note: depends output load condition when device selected. ICC(max) specified output open condition. Address changed once less while VIL. Address changed once less while LCAS UCAS VIH. UCAS (<=0.2) LCAS (<=0.2) while (<=0.2). L-version.
Semicon
GM71V18163C GM71VS18163CL
Capacitance (VCC 3.3V+/-0.3V, 25C)
Symbol CI/O Parameter
Input Capacitance (Address) Input Capacitance (Clocks) Output Capacitance (Data-In/Out)
Unit
Note
Note: Capacitance measured with Boonton Meter effective capacitance measuring method. UCAS LCAS disable DOUT.
Characteristics (VCC 3.3V+/-0.3V, +70C, Note
Test Conditions
Input rise fall times Input levels Input timing reference levels 0.8V, 2.0V Output timing reference levels 0.8V, 2.0V Output load 1TTL gate (100 (Including scope jig)
Read, Write, Read-Modify-Write Refresh Cycles (Common Parameters)
Symbol Parameter
Random Read Write Cycle Time Precharge Time Precharge Time Pulse Width Pulse Width Address Time Address Hold Time Column Address Set-up Time Column Address Hold Time Delay Time Column Address Delay Time Hold Time Hold Time Precharge Time Delay Time Delay Time from Delay Time from Transition Time (Rise Fall)
GM71V(S)18163 GM71V(S)18163 GM71V(S)18163 C/CL-5 C/CL-6 C/CL-7
Unit
Note
tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC
10,000 10,000
10,000 10,000
10,000 10,000
Semicon
GM71V18163C GM71VS18163CL
Read Cycle
Symbol Parameter
Access Time from Access Time from Access Time from Address Access Time from Read Command Setup Time Read Command Hold Time Read Command Hold Time Column Address Lead Time Column Address Lead Time Output Low-Z Output Data Hold Time Output Data Hold Time from Output Buffer Turn-off Time Output Buffer Turn-off Time Delay Time Read Command Hold Time from Output Data hold Time from Output Buffer turn Output Buffer turn Delay Time Delay Time
GM71V(S)18163 GM71V(S)18163 GM71V(S)18163 C/CL-5 C/CL-6 C/CL-7
Unit
Note
9,10,17 9,11,17
tRAC tCAC tOAC tRCS tRCH tRRH tRAL tCAL tCLZ tOHO tOFF tOEZ tCDD tRCHR tOHR tOFR tWEZ tWDD tRDD
12,22
13,27
Semicon
GM71V18163C GM71VS18163CL
Write Cycle
Symbol Parameter
Write Command Setup Time Write Command Hold Time Write Command Pulse Width Write Command Lead Time Write Command Lead Time Data-in Setup Time Data-in Hold Time
GM71V(S)18163 GM71V(S)18163 GM71V(S)18163 C/CL-6 C/CL-7 C/CL-5
Unit
Note
14,21
tWCS tWCH
tRWL tCWL
15,23 15,23
Read- Modify-Write Cycle
Symbol Parameter
Read-Modify-Write Cycle Time Delay Time Delay Time Column Address Delay Time Hold Time from
GM71V(S)18163 GM71V(S)18163 GM71V(S)18163 C/CL-5 C/CL-6 C/CL-7
Unit
Note
tRWC tRWD tCWD tAWD tOEH
Refresh Cycle
Symbol Parameter
Setup Time (CAS-before-RAS Refresh Cycle) Hold Time (CAS-before-RAS Refresh Cycle) Precharge Hold Time
GM71V(S)18163 GM71V(S)18163 GM71V(S)18163 C/CL-5 C/CL-6 C/CL-7
Unit
Note
tCSR tCHR tRPC
Semicon
GM71V18163C GM71VS18163CL
Page Mode Cycle
Symbol Parameter
Page Mode Cycle Time Page Mode Pulse Width Access Time from Precharge Hold Time from Precharge Output data Hold Time from Hold Time referred Setup Time Read command Hold Time from Precharge
GM71V(S)18163 GM71V(S)18163 GM71V(S)18163 C/CL-5 C/CL-6 C/CL-7
Unit
Note
9,17,22
tHPC tRASP tACP tRHCP tDOH tCOL tCOP tRCHP
100,000
100,000
100,000
Page Mode Read-Modify-Write Cycle
Symbol Parameter
Page Mode Read-Modify-Write Cycle Time Delay Time from Precharge
GM71V(S)18163 GM71V(S)18163 GM71V(S)18163 C/CL-5 C/CL-6 C/CL-7
Unit
Note
tHPRWC tCPW
14,22
Refresh
Symbol Parameter
GM71V(S)18163 GM71V(S)18163 GM71V(S)18163 C/CL-5 C/CL-6 C/CL-7
Unit
Note
1024 cycles 1024 cycles
tREF tREF
Refresh period Refresh period -Series)
Semicon
GM71V18163C GM71VS18163CL
Self Refresh Mode L-version
Symbol Parameter
Pulse Width(Self-Refresh) Precharge Time(Self-Refresh) Hold Time(Self-Refresh)
GM71VS18163 CL-5 GM71VS18163 CL-6 GM71VS18163 CL-7
Unit
Note
tRASS tRPS tCHS
Notes measurements assume initial pause 200us required after power followed minimum eight initialization cycles (any combination cycles containing RAS-only refresh CAS-before-RAS refresh). Operation with tRCD (max) limit insures that tRAC (max) met, tRCD (max) specified reference point only; tRCD greater than specified tRCD (max) limit, then access time controlled exclusively tCAC. Operation with tRAD (max) limit insures that tRAC (max) met, tRAD (max) specified reference point only; tRAD greater than specified tRAD (max) limit, then access time controlled exclusively tAA. Either tODD tCDD must satisfied. Either tDZO tDZC must satisfied. (min) (max) reference levels measuring timing input signals. Also, transition times measured between (min) (max). Assumes that tRCD tRCD (max) tRAD tRAD (max). tRCD tRAD greater than maximum recommended value shown this table, tRAC exceeds value shown. Measured with load circuit equivalent 1TTL loads 100pF. Assumes that tRCD tRCD (max) tRAD tRAD (max). Assumes that tRCD tRCD (max) tRAD tRAD (max). Either tRCH tRRH must satisfied read cycles. tOFF (max) tOEZ (max) define time which outputs achieve open circuit condition referred output voltage levels. tWCS, tRWD, tCWD, tAWD tCPW restrictive operating parameters. They included data sheet electrical characteristics only; tWCS tWCS (min), cycle early write cycle data will remain open circuit(high impedance) throughout entire cycle; tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min), tCWD>=tCWD(min) tAWD tAWD (min) tCPW tCPW (min), cycle read-modify-write data output will contain data read from selected cell; neither above sets conditions satisfied, condition data access time) indeterminate.
Semicon
GM71V18163C GM71VS18163CL
These parameters referred UCAS LCAS leading edge early write cycles leading edge delayed write read-modify-write cycles. tRASP defines pulse width mode cycles. Access time determined longer tCAC tACP. delayed write read-modify-write cycles, must disable output buffer prior applying data device. After reset, tOEH>=tCWL, will remain open circuit (high impedance): tOEH<=tCWL, invalid data will each I/O. When both LCAS UCAS same time, 16-bits data written into device. LCAS UCAS cannot staggered within same write/read cycles. pins shall supplied with same voltages. tASC, tCAH, tRCS, tWCS, tWCH, tCSR tRPC determined earlier falling edge UCAS LCAS. tCRP, tCHR, tRCH, tACP tCPW determined later rising edge UCAS LCAS. tCWL, tDH, tCHS should satisfied both UCAS LCAS. determined time that both UCAS LCAS high. tHPC(min) achieved during series page made write cycles mode write cycles. both write read operation mixed mode cycle(EDO mode cycle (1),(2)) minimum Value cycle (tCAS+tCP+2tT) becomes greater than specified tHPC (min) value. value cycle time mixed mode shown mode cycle (2). When output buffers enabled once, sustain impedance state until valid data obtained. When output buffer turned within very short time generally causes large Vcc/Vss line noise, which causes degrade min/VIL level. Data output turns becomes high impedance from later rising edge CAS. Hold time turn time specified timing specification later rising edge between tOHR tOH, between tOFR tOFF. Hi-Z control rising edge disables data outputs. When goes high during high, data will come until next access. When goes during high, data will come until next access. Please tRASS timing, 10us<=tRASS<=100us. During this period, device transition state from normal operation mode self refresh mode. tRASS>=100us, then precharge time should tRPS instead tRP. VIH(min) VIH(max), VIL(min) VIL(max)
Semicon
GM71V18163C GM71VS18163CL
Notes concerning 2CAS control
Please separate UCAS LCAS operation timing intentionally. However skew between UCAS LCAS allowed under following conditions. Each UCAS LCAS should satisfy timing specifications individually. Different operation mode upper/lower byte allowed, such following.
Delayed write Early write LCAS
UCAS
Closely separated upper/lower byte control allowed. However when condition (tCP tUL)is satisfied, page mode performed.
UCAS
LCAS
Byte control operation remaining UCAS LCAS high guaranteed.
Semicon
GM71V18163C GM71VS18163CL
tRAS
Timing Waveforms
tCSH tRCD
UCAS LCAS
tCRP tRSH tCAS
tRAD
tRAL tCAL
tOFR tOHR
tASR
ADDRESS
tRAH
tASC
tCAH
tRDD
COLUMN
tRCHR tRCS
tRRH tRCH tWEZ
tDZC
High-Z
tCDD
tWDD
tDZO
tOAC
tODD
tCAC tRAC tCLZ
High-Z DOUT
INVALID DOUT DOUT
tOEZ tOHO tOFF
FIGURE READ CYCLE
Don't care
Semicon
tRAS
GM71V18163C GM71VS18163CL
tRSH tRCD tCSH tCAS tCRP
UCAS LCAS
tASR
ADDRESS
tRAH
tASC
tCAH
COLUMN
tWCS
tWCH
High-Z*** DOUT
Don't care
Don't care tWCS tWCS (min)
FIGURE EARLY WRITE CYCLE
Semicon
tRAS
GM71V18163C GM71VS18163CL
tRSH tRCD tCSH tCAS tCRP
UCAS LCAS
tASR
ADDRESS
tRAH
tASC
tCAH
COLUMN
tCWL tRCS
tRWL
tDZC
High-Z
tDZO
tODD
tOEH
tOEZ tCLZ
DOUT
INVALID DOUT
High-Z Don't care
FIGURE DELAYED WRITE CYCLE
*Note delayed write read-modify-write cycles, must disable output buffer prior applying data device. After reset, tOEH>=tCWL, will remain open circuit (high impedance); tOEH<=tCWL, invalid data will each I/O.
Semicon
tRWC tRAS
GM71V18163C GM71VS18163CL
tRCD
tCAS
tCRP
UCAS LCAS
tRAD tASR tRAH tASC tCAH
COLUMN
ADDRESS
tRCS tRWD
tCWD tAWD
tCWL tRWL
tDZC
High-Z
tDZO tOAC
tODD
tOEH
tCAC tRAC
DOUT
INVALID DOUT
tOEZ tOHO
DOUT
High-Z Don't care
tCLZ
FIGURE READ MODIFY WRITE CYCLE
*Note delayed write read-modify-write cycles, must disable output buffer prior applying data device. After reset, tOEH>=tCWL, will remain open circuit (high impedance); tOEH<=tCWL, invalid data will each I/O.
Semicon
tRAS
GM71V18163C GM71VS18163CL
tCRP
UCAS LCAS
tRPC
tCRP
tASR
ADDRESS
tRAH
tOFR tOFF
DOUT
INVALID DOUT
High-Z
Don't care
Don't care
FIGURE ONLY REFRESH CYCLE
Semicon
GM71V18163C GM71VS18163CL
tRAS
tRAS
tRPC
UCAS LCAS
tCSR tCHR
tRPC tCSR tCHR
tCRP
ADDRESS
tOFF
DOUT
INVALID DOUT
tOFR
High-Z
Don't care
Don't care
FIGURE BEFORE REFRESH CYCLE
Semicon
tRAS
GM71V18163C GM71VS18163CL
tRAS tRAS
tRCD tRSH tCHR tCRP
UCAS LCAS
tRAD tASR
ADDRESS
tRAL tCAH
COLUMN
tRAH
tASC
tRRH tRCS
tRCH
tWDD
High-Z
tDZC tDZO tOAC
tRDD tCDD tODD
tCAC tRAC tCLZ
High-Z DOUT
INVALID DOUT DOUT
tOFF
tOHO
tOEZ tWEZ
tOHR
FIGURE HIDDEN REFRESH CYCLE
Don't care
tOFR
Semicon
GM71V18163C GM71VS18163CL
tRASP tRHCP
tRCD
UCAS LCAS
tCSH tCAS
tHPC tCAS
tRSH tCAS tCRP
tRAD tASR tRAH tASC
tCAL tCAH tASC
tCAL tCAH tASC
tRAL tCAH
ADDRESS
COLUMN
COLUMN
COLUMN
tRCHP tRCS
tRCH tRRH
tCAL tACP tCAC tACP tCAC tOEZ tDOH tDOH
DOUT DOUT
tWEZ tOHR tOFR tOFF
tOAC tRAC tCAC
DOUT
High-Z
DOUT
INVALID DOUT
INVALID DOUT
INVALID DOUT
Don't care
FIGURE EXTENDED DATA MODE READ CYCLE
Semicon
GM71V18163C GM71VS18163CL
tRASP tRHCP
tHPC tCSH
UCAS LCAS
tHPC tCAS
tHPC tRSH tCAS tRCHP
tCRP
tCAS tRCHR tCAS
tRCS
tRCH
tRCS
tRRH tRCH
tRAL tASC tCAH tASR
ADDRESS
tWDD tRDD tCDD
tASC
tCAH
tASC
tCAH
tASC
tCAH
tRAH
COLUMN COLUMN COLUMN COLUMN
tCAL tDZC
High-Z
tCAL
tCAL
tCAL
tOFR tOHR tOFF
tDZO tCOL
tCOP
tODD
tACP tOAC tCAC tRAC tWEZ
DOUT High-Z
DOUT
tOEZ tCAC tOHO tOAC
DOUT
tACP tCAC tDOH
DOUT INVALID DOUT
tACP tOEZ tOHO
DOUT
tOEZ tOHO tCAC
tOAC
DOUT
Don't care
FIGURE EXTENDED DATA MODE READ CYCLE CONTROL)
*Note Hi-Z control rising edge disables data outputs. When goes high during high, data will come until next access. When goes during high, data will come until next access.
Semicon
GM71V18163C GM71VS18163CL
tRASP tHPC tCAS tCAS tCAS tHPC tHPC tCAS tRSH tCRP
tCSH
LCAS
UCAS
tASR tRAH tASC
ADDRESS
tASC tCAH
COLUMN
tASC
tCAH
tCAH
COLUMN
tASC
tCAH
COLUMN
COLUMN
tDZC tRCS
tCAL
tCAL
tCAL
tRCHP tCAL
tRRH tRCH
tWDD
High
tCAC tDZO
tCAC tDOH tCOL tOAC tOHO tOEZ tCOP tODD
tRAC
High
tOAC tACP
DOUT INVALID DOUT
tOEZ tOHO
tCAC tOAC tACP
DOUT
tOEZ tOHO tOFF tOFR tOHR
DOUT
LDOUT
DOUT
DOUT
tACP
tCAC
DOUT
High UDOUT
DOUT
Don't care
FIGURE EXTENDED DATA MODE READ CYCLE (2CAS TYPE)
Semicon
GM71V18163C GM71VS18163CL
tRASP tRCD
tCSH tCAS
tHPC tCAS
tRSH tCAS
tCRP
UCAS LCAS
tASR tRAH tASC tCAH tASC tCAH tASC tCAH
ADDRESS
COLUMN
COLUMN
COLUMN
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
High-Z** DOUT
Don't care tWCS >=tWCS (min)
Don't care
FIGURE EXTENDED DATA MODE EARLY WRITE CYCLE
Semicon
GM71V18163C GM71VS18163CL
tRASP
tRCD
UCAS LCAS
tCSH tCAS tHPC tCAS
tRSH tCAS
tCRP
tRAD tASR tRAH tASC tCAH
COLUMN
tASC tCAH
COLUMN
tASC tCAH
COLUMN
ADDRESS
tCWL tRCS
tCWL tRCS tRCS
tCWL tRWL
tDZC
tDZC
tDZC
High-Z
tDZO tODD tOEH
tDZO tODD tOEH
tDZO tODD tOEH
tCLZ tOEZ
DOUT
INVALID DOUT
tCLZ tOEZ
tCLZ tOEZ
High-Z
INVALID DOUT
INVALID DOUT
Don't care
FIGURE EXTENDED DATA MODE DELAYED WRITE CYCLE
Semicon
GM71V18163C GM71VS18163CL
tRASP
tRCD
UCAS LCAS
tHPRWC tRSH tCAS tCAS tCAS
tCRP
tRAD tASR tRAH tASC tCAH
COLUMN
tASC tCAH
COLUMN
tASC tCAH
COLUMN
ADDRESS
tRCS
tRWD tAWD tCWD
tCWL tRCS
tCPW tAWD tCWD
tCWL tRCS
tCPW tAWD tCWD
tCWL tRWL
tDZC
tDZC
tDZC
High-Z
tDZO tODD tOEZ
tDZO tDZO tOEH tOEZ tOHO tOAC tCAC tCLZ tOHO tODD tOEH tOEZ tOAC tCAC tACP tCLZ
High-Z
tODD tOEH tOHO
tOAC tCAC tRAC tCLZ
DOUT
INVALID DOUT
tACP
DOUT
INVALID DOUT
DOUT
INVALID DOUT
DOUT
Don't care
FIGURE EXTENDED DATA MODE READ MODIFY WRITE CYCLE
Semicon
GM71V18163C GM71VS18163CL
tRASP
tRCD tCAS tCSH tWCS tWCH
tCAS
tCAS
tCAS tRCHP tRSH tRAL tCAL tASC tCAH tCAH
COLUMN
tCRP
UCAS LCAS
tCPW tAWD
tRRH tRCH
tRAH tASR
ADDRESS
tASC tCAH
COLUMN
tASC tCAH
COLUMN
tASC
COLUMN
tCAL
High
tRDD tCDD
tWDD tODD
tCAC tOAC tACP
High DOUT
tDOH tACP
DOUT
tOHO tCAC tOEZ
tCAC tOAC tACP tOFF tOFR
DOUT
tOEZWEZ tOHO
DOUT
Don't care
FIGURE EXTENDED DATA MODE CYCLE
Semicon
GM71V18163C GM71VS18163CL
tRASP
tRCD tCSH tCAS tRCHR tRCS tRCH tWCH tWCS tCPW tASC tASC tCAH tCAH
COLUMN
tCAS tCAS
tCAS
tCRP
UCAS LCAS
tRSH tRAL
tRRH tRCH
tRAH tASR
ADDRESS
tCAH
COLUMN
tASC
tASC tCAH
COLUMN
COLUMN
tCAL
High
tCAL
tCAL
tCAL
tRDD tCDD tWDD
tODD
tCOL
tODD
tCAC tOAC tRAC
DOUT
tOEZ tOHO
DOUT
tCAC tACP tOAC
High
tCOP tOEZ
tCAC tOAC tACP
tOFF tOFR
DOUT
tWEZ tOEZ tOHO
DOUT
Don't care
FIGURE EXTENDED DATA MODE CYCLE
*Note :tHPC(min) achieved during series mode write cycles mode read cycles. both write read operation mixed mode cycle(EDO mode cycle (1),(2) minimum value cycle (tCAS 2tT) becomes greater than specified tHPC(min) value. value cycle time mixed mode shown mode cycle (2).
Semicon
GM71V18163C GM71VS18163CL
tRASS
tRPS
tRPC
UCAS LCAS
tCSR
tCHS
tCRP
tOFR tOFF
DOUT
INVALID DOUT
High-Z
Don't care
Address, Don't care
self refresh current achieved introducing extremely long internal refresh cycle. Therefore some care needs taken refresh. Please tRASS timing, 10us<=tRASS<=100us. During this period, device transition state from normal operation mode self refresh mode. tRASS>=100us, then precharge time should tRPS instead tRP. only refresh burst refresh mode normal read/write cycle, 1024 4096 cycles distributed refresh with 15.6us interval should executed within 16ms 64ms immediately after exiting from before entering into self refresh mode. distributed refresh mode with 15.6us interval normal read/write cycle, refresh should executed within 15.6us immediately after exiting from before entering into self refresh mode. Repetitive self refresh mode without refreshing memory allowed. Once exit from self refresh mode, memory cells need refreshed before re-entering self refresh mode again.
Note GM71C(V)16163 4096 Refresh Cycles 64ms GM71C(V)18163 1024 Refresh Cycles 16ms
FIGURE SELF-REFRESH CYCLE
Semicon
GM71V18163C GM71VS18163CL
Unit: Inches (mm)
Package Dimension
0.025(0.64) 0.405(10.29) 0.445(11.30) 0.395(10.03) 0.435(11.06) 0.380(9.65) 0.360(9.15)
1.058(26.89) 1.072(27.23)
0.093(2.38)
0.128(3.25) 0.148(3.75) 0.050(1.27) 0.015(0.38) 0.020(0.50) 0.026(0.66) 0.032(0.81)
44(50) TSOP
0.016(0.40) 0.024(0.60)
0.405(10.29)
0.455(11.56) 0.471(11.96)
0.394(10.03)
0.820(20.82) 0.830(21.08) 0.037(0.95) 0.041(1.05) 0.047(1.20) 0.012(0.30) 0.017(0.45) 0.031(0.80) 0.002(0.05) 0.006(0.15)
0.004(0.12) 0.008(0.21)
Other recent searches
SG120 - SG120 SG120 Datasheet
SG7800A - SG7800A SG7800A Datasheet
NTE3016 - NTE3016 NTE3016 Datasheet
MPC5500 - MPC5500 MPC5500 Datasheet
BFS17P - BFS17P BFS17P Datasheet
AP08055 - AP08055 AP08055 Datasheet
XC886 - XC886 XC886 Datasheet
AF9926N - AF9926N AF9926N Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
