W928C73 high performance bits microcontroller with build-in POCSAG dec
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Preliminary W928C73 POCSAG MICROCONTROLLER
W928C73 high performance bits microcontroller with build-in POCSAG decoder driver. possible switch normal mode, idle mode power down mode power saving purpose. W928C73 extended from standard 8031 (excluding UART) that easily applied pager system other telecommunication system.
512, 1200 2400 POCSAG decoder independent user addresses Instruction compatible with MCS51 System clock
OSC2: 76.8
bytes on-chip fast bytes on-chip MOVX bytes on-chip program bits on-chip flash Timer
16-bit timer/counters timer Watch-dog timer
Buzzer timer Four 8-bit bit-addressable ports Three external interrupt source, INT0, INT1 (BAT_DET_INT), INT3 (KEY_INT) Battery detector Battery detector Power fail detector Power down wake-up external interrupts 16-bit Data Pointers (Selected DPS.0) source, vector interrupts structure with priority-level interrupts Built-in programmable power-saving modes Idle mode Power-down mode Operating voltage range: 2.4V 3.3V
segment common, bias, duty driver output Packaged 64-pin LQFP
Publication Release Date: June 2000 Revision
Preliminary W928C73
CONFIGURATION
RESET P1.5/MOTOR P1.6/BUZZER P1.7/LED BL_RF TEST1 TEST2 PSEN P3.0 P3.1
SEG29 SEG28 SEG27 SEG26 SEG25 SEG24
W928C73
LQFP
SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14
Preliminary W928C73
DESCRIPTIONS
SYMBOL P1.5 P1.6 P1.7 BL_RF TEST1 TEST2
PSEN
TYPE GROUND: ground potential
DESCRIPTIONS RESET: this machine cycles while oscillator running resets device. Motor output, hi-drive Buzzer clock output, hi-drive output, hi-drive Connect chip POCSAG signal input control control control External access enable pin. Should connect VDD. connection. Test pin. Internal pull connection. Test pin. Internal pull connection. Test pin. addressable general port addressable general port addressable general port INT0 defined Battery fail interrupt input. Connect V1.5. voltage potential battery less than 0.8V, INT1 interrupt flag will set. segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal
P3.0 P3.1 P3.2/INT0 P3.3/INT1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13
Publication Release Date: June 2000 Revision
Preliminary W928C73
Descriptions, continued
SYMBOL SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 P2.2/SEG34 P2.3/SEG35 P2.4/VDD3 P2.5 P2.6 P2.7 COM0 COM1 COM2 COM3 P0.4 P0.5 P0.6 XOUT2 XIN2
TYPE segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal segment signal voltage input (VDD)
DESCRIPTIONS
common signal output pins. common signal output pins. common signal output pins. common signal output pins. addressable general port Key_0 interrupt addressable general port Key_1 interrupt addressable general port Key_2 interrupt POWER SUPPLY: Supply voltage operation. Output clock_2. inversion XIN2. Input clock_2
Note TYPE input, output, I/O: bi-directional, pull-high, pull-low, open drain
Preliminary W928C73
BLOCK DIAGRAM
P0.3 P0.7 P1.0 P1.2 P1.5 P1.7 P3.0 P3.3
Port
Port
P2.5 P2.7
register Port
register Port Stack Pointer
P4.0~4.7 P5.0~5.7 P6.0~6.7 P7.0~7.7 P8.0~8.3
Port 128B
LCD_OFF DPTR DPTR 384B MOVX Address LCD_ON
Timer Timer Buzzer Timer Timer Watchdog Timer
FLASH 16KB program 32x4 Address Driver
Instruction Decoder Sequencer
RESET
Power power reset
System control Clock Generator L_Clock XIN2 XOUT2
Data
Publication Release Date: June 2000 Revision
Preliminary W928C73
FUNCTIONAL DESCRIPTION
W928C73 high performance bits POCSAG microcontroller with build-in driver POCSAG decoder. 8031 instruction compatible with addition: DPTR (op-code A5H, DPTR decreased W928C73 standard features 8031 except UART, extra peripherals features like watchdog, RTC, buzzer timers, driver, build-in POCSAG decoder. W928C73 features faster running better performance 8-bit reducing machine cycle duration from standard 8031 period twelve clocks four clock cycles majority instructions. W928C73 also provides dual Data Pointers (DPTRs) speed block data memory transfers. addition, W928C73 contains on-chip 384B MOVX SRAM. only accessed MOVX instruction; this on-chip data memory enabled software commend.
Memory Organization
W928C73 separates memory into sections, Program Memory Data Memory. Program Memory used store instruction op-codes, while Data Memory used storing data memory mapped devices. must connect high access on-chip program ROM.
3FFFH
bytes Program Memory 0200H 0080H System testing 0000H Interrupt vector Program Memory 0000H Internal Data Memory 017FH Bytes Data MOVX Direct indirect Addressing Internal Data Memory Special Function Register Direct addressing
On-chip memory space W928C73
Stack
scratch-pad used stack. This area selected Stack Pointer (SP), which stores address stack. Whenever jump, call interrupt invoked return address placed stack. There restriction where stack begin RAM. default however, Stack Pointer contains reset. user then change this value desired. will point last used value. Therefore, will incremented then address saved onto stack. Conversely, while popping from stack contents will read first, then decreased.
Preliminary W928C73
Data Area
When indirect area EEH-FFH work data (LCD00-LCD35). Instruction such "MOV @R0, (Where EEH-FFH) used control data RAM. data data (bit7-bit0) transferred segment output pins automatically without program control. When value data "1", turned When value data "0", turned off. relation between data segment/common pins shows below. Data COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17 SEG19 SEG21 SEG23 SEG25 SEG27 SEG29 SEG35
SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22 SEG24 SEG26 SEG28 SEG34
Publication Release Date: June 2000 Revision
Preliminary W928C73
Descriptions Special Function Registers(SFRS)
ADDRESS /NAME 80H/P0 81H/SP 82H/DPL 83H/DPH 84H/DPL1 85H/DPH1 86H/DPS 87H/PCON B7~0 B7~0 B7~0 B7~0 B7~0 Key_2 Key_1 Key_0 DEC_ADDT F_ADR DEC_ SYNVAL F_data DPL1 DPH1 DPS.0 SMOD SMOD0 Enable Enable Disable Disable NAME Pointer Pointer SYNC Lost SYNC Matched Unmatched INITIAL Key_2 input. corresponding key_INT(INT3_3) enabled. Key_1 input. corresponding key_INT(INT3_3) enabled. Key_0 input. corresponding key_INT(INT3_3) enabled. POCSAG address matched flag. corresponding INT(INT2) could setup. Flash serial address output Decoder synchronization condition Flash data FUNCTION
00000111 Stack pointer address. Always points stack. 00000000 byte data pointer 00000000 High byte data pointer 00000000 byte data pointer 00000000 High byte data pointer Selection data pointer, B7~1 used use. Clear after power_on reset use. Clear after power_on reset use. Clear after power_on reset use. Clear after power_on reset General purpose user defined flag General purpose user defined flag Power down mode enable bit. this will stop oscillation. Idle mode enable bit. this will stop clock, oscillator keep running. Timer overflow flag,. will automatically clear after service routine. Timer enable Timer overflow flag, will automatically clear after service routine Timer enable Interrupt 1(battery fail INT) flag. hardware when pre-selected level (high low) detected INT1. flag will keep only level held.
88H/TCON
Overflow
Enable Overflow
Disable
(Bat_fail)
Enable
Disable
Preliminary W928C73
Descriptions Special Function Registers (SFRS), continued ADDRESS /NAME NAME High level level INITIAL FUNCTION Interrupt level selection. software specify high (>0.8V) (<0.8V) level external triggered. Interrupt edge detect: hardware when edge/level detected INT0. This cleared hardware when service routine vectored only interrupt edge triggered. Otherwise follows pin. Interrupt type selection. Set/cleared software specify falling edge/ level triggered external inputs Timer timer control: Tx_GATE (gating control): When this set, Timer/counter will enabled both INTx high control set. When this cleared, Timerx enabled whenever control set. Tx_C/T (timer counter select): When cleared, timer incremented internal clocks. When set, timer counts high-to-low edges pin. Mode 8-bits with 5-bit pre-scalar. 16-bits, pre-scalar. 8-bits with auto-reload from (Timer 8-bit timer/counter controlled standard Timer control bits. 8-bit timer only controlled Timer control bits. (Timer Timer/counter stopped.
Falling edge
level
89H/TMOD
T1_GATE
T1_T
Timer
T1_M1
T1_M0
T0_GATE
T0_T
Timer
T0_M1
T0_M0
8AH/TL0 8BH/TL1 8CH/TH0 8DH/TH1 8EH/CKCON
B7~0 B7~0 B7~0 B7~0
00000000 byte timer 00000000 byte timer 00000000 High byte timer 00000000 High byte timer (watchdog timeout period) Fs/214+512 clock Fs/216+512 clock Fs/218+512 clock Fs/221+512 clock RTC1 RTC0 (RTC timeout period) RTLCD
RTC1
RTC0
Publication Release Date: June 2000 Revision
Preliminary W928C73
Descriptions Special Function Registers (SFRS), continued ADDRESS /NAME NAME Enable Disable INITIAL ELC: enable L_clock. Keep this high whole operation. 90H/P1 DEC_RST DEC_ON DEC_ DATA 91H/PBCON 92H/TONE0 96H/PLC 97H/PLH A0H/P2 B7~0 B7~0 B7~0 DEC_CLK ENBT ENBUZ TONE0 P2.7 P2.6 P2.5 P2.4 P2.3 High High Enable Enable Disable Disable High 00000000 00000000 00000000 SEG35~32 work segment. P2.3 value SEG35~32 work P2.3~P2.0 function (P2M (A1.1H) P2.2 P2.1 High High P2.2 value SEG35~32 work P2.3~P2.0 function (P2M (A1.1H) SEG35~32 work segment. P2.1 value SEG35~32 work P2.3~P2.0 function (P2M (A1.1H) Buzzer timer enable (used general timer) Buzzer output enable Auto reload value buzzer timer byte program counter High byte program counter P2.7 B6~B4 when Decoder option setup clock output control Clear B7~B2 after power reset. Buz_out Motor High High High High High High Clear after reset. output port P1.7 (HI-drive) Initial value buzzer output Motor output pin(Hi-drive) Decoder reset control Decoder enable control Decoder option setup data output control FUNCTION after power reset.
Preliminary W928C73
Descriptions Special Function Registers (SFRS), continued ADDRESS /NAME NAME P2.0 High INITIAL FUNCTION SEG35~32 work segment. P2.0 value SEG35~32 work P2.3~P2.0 function (P2M (A1.1H) A1H/LCDR LCDWAVE FLCD1 Type Type FLCD1 FLCD0 frequency FLCD0 RTLCD Clear B7~B4 after reset. Default LCDWAVE type)
scan rate frequency/ P2.0~2.3/SEG32~35 function selection. This only while While these pins work SEG32~35 output. clear these pins will work P2.0~2.3. A2H/RTLCD A8H/IE B7~0 AAH/SDTMF LCDON RTLCD INT33 INT32 INT31 INT30 Enable Enable Enable Enable Enable Enable Enable Enable Disable Disable Disable Disable Disable Disable Disable Disable Enable Enable Disable Disable driver enable control
11111111 timer value. RTLCD 76.8 crystal Global interrupt enable control POCSAG receiving buffer interrupt enable control Clear this after power reset Clear this after power reset Timer interrupt enable control External interrupt (battery fail INT) enable control Timer interrupt enable control External interrupt enable control Clear this after reset Enable INT32 (key2) Enable INT31 (key1) Enable INT30 (key0) Clear B3~B0 after reset
Publication Release Date: June 2000 Revision
Preliminary W928C73
Descriptions Special Function Registers (SFRS), continued ADDRESS /NAME B0H/P3 NAME DEC_BL Battery Battery INITIAL Battery condition. battery voltage lower than volt, this will change otherwise this will This works only BL_RF connect output. Flash mode control Flash clock output Flash control Battery fail condition. battery voltage lower than volt, this will change otherwise this will additional level interrupt(INT1) enabled monitor this bit. B2/HB B8H/IP B7~0 C0H/CSCON C1H/SMODE C2H/SB1 C3H/SB2 B7~0 B7~0 B7~0 P3.2/INT0 P3.1 P3.0 OVFH OVFL REN1 SMODE Enable Disable High High High High High High 00000000 00000000 00000000 00000000 OSC2 clock stable flag POCSAG receiving buffer interrupt request flag POCSAG receiving buffer enable control POCSAG mode control, SMODE 11101101 after reset POCSAG receiving buffer POCSAG receiving buffer P3.2 external interrupt input P3.1 P3.0 High byte address "MOVX @Ri" Buzzer timer interrupt priority level POCSAG receiving buffer interrupt priority level Clear this after reset Clear this after reset Timer interrupt priority level Interrupt (INT1) interrupt priority level Timer interrupt priority level Interrupt (INT0) interrupt priority level Clear B7~B4 after reset FUNCTION
F_Mode F_CLK F_ctrl Bat_fail/ INT1
High High High
Battery Battery fail battery
Preliminary W928C73
Descriptions Special Function Registers (SFRS), continued ADDRESS /NAME C4H/SB3 C9H/T2MOD B7~0 D0H/PSW NAME DME0 TONESEL 50-50duty On-chip External INITIAL FUNCTION
00000000 POCSAG receiving buffer MOVX selection (384 bytes), after reset Clear this after reset Clear this after reset Clear this after reset Clear this after reset Buzzer tone duty control Clear this after reset Clear this after reset Carry flag: arithmetic operation which results carry being generated from ALU. also used accumulator operations.
Auxiliary carry: when previous operation resulted carry (during addition) borrowing (during subtraction) from high order nibble. User define flag Register bank selection Bank Bank Bank Bank 00-07(B0-B7) 08-0F(B0-B7) 10-17(B0-B7) 18-1F(B0-B7)
Overflow flag: when carry generated from seventh from result previous operation viceversa.
User defined flag Parity flag: Set/cleared hardware indicate odd/even number accumulator.
D8H/WDCON
RTIF
interrupt request flag Power-on reset flag: Hardware will this flag power condition. This flag read written software. write software only clear this once set.
Clear this after reset Clear this after reset
Publication Release Date: June 2000 Revision
Preliminary W928C73
Descriptions Special Function Registers (SFRS), continued ADDRESS /NAME D8H/WDCON NAME WDIF INITIAL FUNCTION Watchdog Timer Interrupt Flag: watchdog interrupt enabled, hardware will this indicate that watchdog interrupt occurred. interrupt enabled, then this indicates that time-out period elapsed. WTRF Watchdog Timer Reset Flag: Hardware will this when watchdog timer causes reset. Software read must clear manually. power-fail reset will also clear bit. This helps software determining cause reset. watchdog timer will have affect this bit. Enable Watchdog timer Reset: Setting this will enable Watchdog timer Reset function. Reset Watchdog Timer: This helps putting watchdog timer into know state. also helps resetting watchdog timer before time-out occurs. Failing before time-out will cause interrupt, EWDI (EIE.4) set, clocks after that watchdog timer reset will generated set. This selfclearing. control P0.7 (key3): use, clear this after. P0IO.6 control P0.6 (key2): input mode without pull high output mode input with pull high Clear this after reset key2 input with pull high function. P0IO.5 control P0.5 (key1): input mode without pull high output mode input with pull high Clear this after reset key1 input with pull high function. P0IO.4 control P0.4 (key0): input mode without pull high output mode input with pull high Clear this after reset key0 input with pull high function. P0IO.3 P0IO.2 P0IO.1 P0IO.0 control P0.3: this after reset DEC_ADDT input control P0.2: Clear this after reset F_ADR output function control P0.1: this after reset DEC_SYNVAL input control P0.0: this after reset. read-in F_data, this "1". write-out F_data, clear this "0".
D9H/P0IO
P0IO.7
Preliminary W928C73
Descriptions Special Function Registers (SFRS), continued ADDRESS /NAME DAH/P1IO B7~0 NAME P1IO INITIAL FUNCTION
00000000 addressable control input mode without pull high output mode input with pull high "00000000 after reset, since output mode. 00000000 addressable control input mode without pull high output mode input with pull high "X0000000 after reset. value P2IO.7 depends function P2.7 (input output) 00000000 addressable control input mode without pull high output mode input with pull high "10001XXX after reset. values P3IO.2~P3IO.0 depend functions P3.2~P3.0 (input output) 00000000 Accumulator Enable Enable Enable Enable Enable Enable H_clock High High High Falling High Falling High Disable Disable Disable Disable Disable Disable L_clock Rising Rising timer clock enable Buzzer timer interrupt enable timer interrupt enable Watchdog timer interrupt enable External interrupt request flag External interrupt enable External interrupt request flag External interrupt enable System clock selection Buzzer timer interrupt priority timer interrupt priority Watchdog timer interrupt priority INT3 (key_INT) trigger edge selection External interrupt priority INT2 (ADDT) trigger edge selection External interrupt priority Clear "00" after reset.
DBH/P2IO
B7~0
P2IO
DCH/P3IO
B7~0
P3IO
DDH/P48IO
P8IO P7IO P6IO P5IO P4IO ERTLC EBTI ERTI EWDI SMSC PBTI PRTI PWDI
E0H/ACC E8H/EIE
B7~0
F0/B F8H/EIP
B7~0
00000000 register
Notes: SFRs bold addressable, others byte addressable. SFRs only accessed direct addressing. P2.4 pulled high internal, when external connect p2.4 LCD. must following instruction P2IO,#10H P2.4 P0IO~P8IO default output mode(0), when need input mode then P0IO~P8IO
Publication Release Date: June 2000 Revision
Preliminary W928C73
Data Pointers
original 8031 only 16-bit Data Pointer (DPL, DPH). W928C73, there additional 16-bit Data Pointer (DPL1, DPH1). This Data Pointer uses locations which were unused original 8031. addition there additional instruction, DPTR (op-code A5H), which helps improving programming flexibility user.
MOVX Instruction
W928C73, like standard 8031, uses MOVX instruction access external Data Memory. external data memory includes bytes on-chip data RAM. MOVX instruction types, MOVX MOVX @DPTR. MOVX @Ri, address external data comes from sources. lower 8-bits address stored register selected working register bank. upper 8-bits address store register (B2h SFR). MOVX @DPTR type, full 16-bit address supplied Data Pointer. Since W928C73 Data Pointers, DPTR DPTR1, user select between setting clearing bit. Data Pointer Select (DPS) SFR, which exists location 86h. Rest bits this have effect, When then DPTR selected, when DPTR1 selected. user switch between DPTR DPTR1 toggling bit. quickest this instruction. register dual Data Pointers will provide enough flexibility performing block move operations.
SYSTEM CLOCK
W928C73 provides oscillation circuit, OSC2 L_clock (76.8 KHz), whole system. During power reset, L_clock activated. Timer, timer, buzzer output frequency clock sources directly come from L_clock. CPU, timer0, timer1 interrupt operation based machine cycle. machine cycle consists four oscillator clock sequence states). control activate L_clock. OVFL clock stable flag L_clock. power state system proper operation, L_clock suggested turn time. clock architecture system shown below.
Timer/Counter Interrupt
/IDL OSC2 L_Clock WDT,RTC, LCD,
Preliminary W928C73
Power Management
Operation Mode (Normal Mode) After power reset, W928C73 will enter normal operation mode. this mode, system operable with main clock. Idle Mode While setting PCON.0 system will idle mode. idle mode, stopped rest system oscillator still running previous state idle mode waked interrupt sources. Power Down Mode instruction setting PCON.1 last executed prior going into Power-down mode. Power-down mode oscillator stopped. contents on-chip SFRS preserved. port pins output values held their respective SFRs. PSEN held LOW. Power-down mode reduced minimize power consumption. However, supply voltage must reduce until Power-down mode active, must restored before hardware reset applied frees oscillator. Reset must held active until oscillator restarted stabilized. wake-up operation W928C73 after power-down mode approaches, wake-up using external interrupt INT0, INT1or wake-up using RESET. INT0 INT1 wake-up, controller will enter interrupt service routine slow operation mode contents on-chip SFRS preserved. RESET wake-up, RESET kept HIGH minimum oscillator periods, will enter power reset state after wake OPERATION MODE Setting Command NORMAL MODE Power reset Idle mode wake Power down mode wake Oscillator Interrupt Watchdog Timer Timer0, Timer1 Buzzer Timer Release Condition L_clock Operable interrupt operable Operable L_clock/4 operable L_clock operable L_clock operable enabled interrupts Clock keeps oscillation Stopped Clock stops Stopped INT0, INT1 Stopped Stopped Stopped Stopped RESET External interrupt INT0, INT1 Release Time main clock
IDLE PCON.0
POWER DOWN PCON.1
Publication Release Date: June 2000 Revision
Preliminary W928C73
Timer W928C73 16-bit Timer. Each these Timer registers which form counting register. Timer they TH0, upper bits register, TL0, lower register. Similarly Timer registers, TL1. configured operate timers, counting machine cycles. timer clock system clock. inputs sampled every machine cycle sampled value high machine cycle next, then valid high transition recognized count register incremented. Since takes machine cycles recognize negative transition pin, maximum rate which counting will take place 1/24 master clock frequency. "Timer" mode, recognized negative transition cause count register value updated only machine cycle following which negative edge detected. "Timer" function selected "C/T" TMOD Special Function Register. Each Timer selection own; TMOD selects function Timer TMOD selects function Timer addition each Timer operate four possible modes. mode selection done bits TMOD SFR. Mode Mode timer counter with bit, divide pre-scale. this mode have timer. counter consists bits lower bits TLx. upper bits ignored. negative edge clock increments count register. When fifth moves from then count register incremented. When count moves from 00h, then overflow flag TCON set. counted input enabled only either GATE When then will count clock cycles, then will count transitions (P3.4) timer (P3.5) timer When count reaches 1FFFh next count will cause roll-over 0000h. timer overflow flag relevant timer enabled interrupts will occur. Note that when used timer, time-base clock cycles/4.
TMOD.2 (C/T TMOD.6) System Clock
TMOD1, TMOD0 (M1, TMOD5, TMOD4) (TL1) (TH1)
TCON.4 (TR1 TCON.6) GATE TMOD.3 (GATE TMOD.7) INT0 P3.2 INT1 P3.3
Interrrpt (TF1) Timer functions shown brakets
Mode Timer
Preliminary W928C73
Mode Mode similar Mode except that counting register forms counter, rather than counter. This means that bits used. Roll-over occurs when timer moves from count FFFFh 0000h. timer overflow flag relevant timer enabled interrupt will occur. selection time-base timer mode similar that Mode gate function operates similarly that Mode Mode Mode timer Auto Reload Mode. this mode, acts count register, while holds reload value. When register overflows from 00h, TCON reloaded with contents THx, counting process continues from here. reload operation leaves contents register unchanged. Counting enabled proper setting GATE INTx pins. other modes mode allows counting either clock cycles (clock/4) pulses
TMOD.2 (C/T=TMOD.6) System Clock
Timer functions shown brakets (TL1) Interrrpt (TF1)
TCON.4 (TR1 TCON.6) GATE TMOD.3 (GATE TMOD.7) INT0 P3.2 INT1 P3.3
(TH1)
Mode Timer
Mode Mode different operating methods timer. timer mode simply freezes counter. Timer however, configures separate count registers this mode. logic this mode shown figure. uses Timer control bits C/T, GATE, TR0, INT0 TF0. used count clock cycles (clock/12 clock/4) 1-to-0 transitions determined (TMOD.2). forced clock cycle counter (clock/12 clock/4) takes over from Timer Mode used cases where extra timer needed. With Timer Mode Timer still used Modes flexibility somewhat limited. While basic functionality maintained, longer control over overflow flag enable TR1. Timer still used timer retains GATE INT1 pin. this condition turned switching into Mode
Publication Release Date: June 2000 Revision
Preliminary W928C73
TMOD.2 System Clock Interrrpt TCON.4 GATE TMOD.3 INT0 P3.2 TCON.6 Interrrpt
Mode Timer
Watchdog Timer
watchdog timer free-running timer which programmed user serve system monitor, time-base generator event timer. When time occurs request flag set, which cause interrupt system reset depend EWDI enable SFR. interrupt reset functions independent each other used separately together depending users software. watchdog timer should first restarted using RWT. This ensures that timer starts from known state.
Fosc=76.8KHz L_Clock Divider1
Fosc/8192 9.375Hz
WDIF Interrupt EWDI
4.64 2.34 1.17 0.59 0.29 0.15 0.07 0.04
divider2 clock delay Reset
EWDI:E8.4H WD1, WD0:8E.7H, 8E.6H
WDIF:D8.3H WTRF:D8.2H EWT:D8.1H RWT:D8.0H
WD1~0 Selector
WTRF
Buzzer Timer
W928C73 provides buzzer timer. buzzer timer output single tone signal that frequency range from 150Hz 38400 operation buzzer timer following. First proper value tone0 then ENBUZ will output corresponding frequency (50% duty cycle) P1.6/BUZ output pin. timer also generate different duty cycle control buzzer volume.
Preliminary W928C73
auto-reload condition: When bits down counter overflow (From "01H" change "FFH") ENBUZ ENBT signal rising edge (From change "H") divider reset condition: RESET TONE,#I instruction ENBUZ rising edge Timer Frequency W928C73 provides flexible timer real time clock calculation. auto-reload downcounter, RTLCD, download suitable value different main clock frequency generate clock interrupt. 76800Hz crystal, RTLCD value should This timer also used provide frequency source. Controller/Driver W928C73 directly drive with segment output pins common output pins total dots. LCDR used driver control. alternating frequency addition, LCDON (LCDR.0) also used four driver output pins (segment segment 31/35) port. (For 76.8 RTLCD 74). driving potentials connected external through port 2.4~2.6 while LCDON connections output waveforms bias, duty driving modes shown below.
LCD_ON P2.6
Vlcd3
driver outputs seg. COM1 COM2 sides being driver outputs seg. COM0 COM2,3 sides being driver outputs seg. COM0 COM1,2,3 sides being
VDD3 VDD2 VDD1
P2.5 Vlcd2
P2.4 Vlcd1
VDD3 VDD2 VDD1
VDD3 VDD2 VDD1
Voltage Connection Output Waveform (1/3 Bias Duty)
Publication Release Date: June 2000 Revision
Preliminary W928C73
Ports
W928C73 four 8-bit addressable ports, port port segment common signal driver change port driver disabled. additional port port byte addressable. Port used address port used data when external program running external memory/device accessed MOVC MOVX instruction. ports W928C73 same 8031 with extra pull high resister control. While read value port, port will function input mode. While write data port SFR, port will work output port. P0IO-P3IO define pull high condition port port When setting will port input mode without pull high resister opendrain output mode. When clear will port input mode with pull high resister output mode. Port port addressable. initial state W928C73 input mode with pull high resister. off, P48IO used control pull high resister port port byte controllable.
Interrupt
W928C73 provides interrupt sources with priority levels. External interrupt highest natural priority. Software assign high priority each interrupt source. interrupt source priorities reset low. Name INT0 INT1 SCON1 INT2 INT3 WDTI RTCI DESCRIPTION External interrupt Timer overflow interrupt External interrupt (BAT_DET_INT) Timer overflow interrupt POCSAG data buffer interrupt External interrupt External interrupt (Key_interrupt) Watchdog interrupt Real-time timer interrupt Buzzer timer interrupt VECTOR NATURAL PRIORITY
POCSAG Decoder
build-in decoder fully compatible with CCIR Radio Paging Code Number (POCSAG code) operating 512, 1200, 2400 bps. build-in POCSAG decoder supports user addresses independent frames.
Preliminary W928C73
Initial Option Setup
decoder should initialized through DEC_TXCLK (P1.0), DEC_TXDATA (P1.1), DEC_RST (P1.3) Clearing DEC_ON (P1.2) from high after option bits setting will enable decoder. BS1, pins will then control receive POCSAG signal. functions option bits described below.
DEC_RST (P1.3)
Total clock
DEC_TXCLK (P1.0)
least
least
least
DEC_TXDATA (P1.1)
D192
DEC_ON (P1.2)
Publication Release Date: June 2000 Revision
Preliminary W928C73
POCDSG Decoder Setup Option
CLOCK DATA CLOCK DATA CLOCK DATA CLOCK DATA CLOCK DATA CLOCK DATA TEST0 TEST1 ADA17 ADA16 ADA15 ADA14 ADA13 ADA12 ADA11 ADA10 ADA9 ADA8 ADA7 ADA6 ADA5 ADA4 ADA3 ADA2 ADA1 ADA0 Baud1 Baud0 Over1 Over0 Smith ADB17 ADB16 ADB15 ADB14 ADB13 ADB12 ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADB3 ADB2 ADB1 ADB0 ADC17 ADC16 ADC15 ADC14 ADC13 ADC12 ADC11 ADC10 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Outr1 Outr2 PREL1 PREL0 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 ADE17 ADE16 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 D160 D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 ADF17 ADF16 ADF15 ADF14 ADF13 ADF12 ADF11 ADF10 ADF9 ADF8 ADF7 ADF6 ADF5 ADF4 ADF3 ADF2 ADF1 ADF0
Preliminary W928C73
FUNCTION Address Disable Enable
OPTION EnA, EnB, EnC, EnD, EnE,
FUNCTION Message reception error termination condition Reception termination first uncorrectable codeword Reception termination consecutive uncorrectable codeword Reserved Reserved Over1
OPTION Over0
FUNCTION Signal Input Without Schmitt Trigger With Schmitt Trigger
OPTION Shmt
FUNCTION range hold time when synchronization lost 1200/2400 OUTR1
OPTION OUTR2
FUNCTION Baud rate 1200 2400 Baud0
OPTION Baud1
Publication Release Date: June 2000 Revision
Preliminary W928C73
bits
TBS3 TBS2
TBS2
FUNCTION TBS2 3.90 11.71 19.53 27.34 FUNCTION TBS3 0.00 31.25 62.50 93.75 1200/2400 0.00 13.33 26.67 40.00 1200/2400 1.67 5.00 8.33 11.67
OPTION OPTION
FUNCTION Preamble length 1024 1792 PREL1
OPTION PREL0
Preliminary W928C73
FUNCTION signal Non-inversion Inversion
OPTION
option TEST0, TEST1 only used testing. normal operation, insert those three option bits. POCSAG data output format While receiving address matched message SCON1 will generate interrupt data will present SBUF1-3. value SBUF first interrupt address word, followed message words, ended with termination word. another addressed matched message received right after first message, second address word will come followed previous termination word shown below. detail formats address word, message word termination word following:
POCSAG Signal
Address
Data
Data
Address
DEC_ADDT(P0.3) SINT
SBUF3~1
Word previous message
Address Word Format
FUN21 FUN20
Publication Release Date: June 2000 Revision
Preliminary W928C73
ADR2 ADR1 ADR0
Note: Address word, Message word, Termination word Func21, function POCSAG ADR2~0: define received address number
ADR2-0 Address
Message Word Format
SYNC
Note: SYNC: sync detection syncloss catch sync ER0: error condition after correction 1:error 0:No error
Termination Word Format
Note: (termination condition): proper termination, 1:Termination error condition
Preliminary W928C73
Decoder related
NAME P0.1 P0.3 P1.0 P1.1 P1.2 P1.3 P3.7 NAME DEC_SYNVAL DEC_ADDT DEC_TXCLK DEC_TXDATA DEC_ON DEC_RST DEC_BLDET I/INT DESCRIPTION Decoder synchronization Decoder Decoder option setup clock Decoder option setup data Decoder on/off control Decoder reset control Battery detector (1V)
bits Flash Operation
W928C73 provides frame flash cell typically used store POCSAG addresses parameters. single voltage supply eliminates need extra pump circuit during programming erasing. There different operation mode, read, program erase. different mode determined number clocks CTRL while MODE high. programming timing shown below.
Read Mode
MODE CTRL DATA
Program Mode
MODE
400uS
CTRL
DATA
bits
bits
Erase Mode
MODE CTRL DATA
High-Z
Publication Release Date: June 2000 Revision
Preliminary W928C73
Read mode
This mode will read data from flash ROM. first bits DATA starting frame address reading-out. DATA these bits, then output data will start from address "0". stored data will shift with each clock data shifted first.
Program mode
This mode will write data into flash ROM. This flash programmed frame basis. Each frame contains bits data. data shift first. programming time (Tpr) must more than Each programming pulse will increase frame address
Erase Mode
This mode will erase data flash ROM. typical whole-chip-erase time should larger than (Twe).
TIMING WAVEFORMS
Flash Programming
Read Cycle
Write Cycle
DATA
DATA
Address Shift-in Cycle
ADDR
Mode Select Duration
ADDR DATA
MODE CTRL
1/FCTRL
Preliminary W928C73
Flash Programming Configuration
NAME P0.0 P0.2 P3.4 P3.5 P3.6
NAME DATA ADDR CTRL MODE
DESCRIPTION Bi-direction data line Output clock start address shift-out Enable signal program erase operations when MODE (P3.6) Input clock mode counter when MODE (P3.6) Output clock data write-out read-in Mode select control
Fast frame-write operation: Frame bits) program cycle time: (typical) Fast whole-chip-erase duration: (max.) Read data access time: (max.) Program/erase cycles: 3000 (typical) Data retention: years (typical)
Notes: program mode, DATA should latched falling edge. read mode, DATA should latched before low. when read mode, must P0IO.0 P0.0 (DATA) input mode). GF1(general flag) will enable flash.
CHARACTERISTICS
(VDD
PARAMETER Operating Voltage Flash Operating Voltage Normal Mode Current Idle Mode Current Stop Mode Current Flash Operating Current Input Voltage Output Current High-drive Port Output Current P1.5 P1.7
High Sink Drive Sink Drive
SYM. VFLASH INORMAL IIDLE ISTOP
CONDITIONS
MIN.
LIMITS TYP.
UNIT
MAX.
load, decoder operating 76.8K load, main clock, decoder load, stop read mode DATA open input pins 0.3V 2.7V 0.3V 2.7V
-0.3
0.6/0.1
Publication Release Date: June 2000 Revision
Preliminary W928C73
FLASH CHARACTERISTICS
(VDD
PARAMETER MODE Pulse Width CTRL Pulse Width Clock Frequency ADDR Clock Frequency Clock Ffrequency CTRL Interval Between ADDR Begin Interval Between CTRL Interval Between ADDR CTRL Interval Between Addressing Block-erase Begin Interval Between MODE Rising Edge CTRL Clock Begin Interval Between CTRL Clock MODE Falling Edge Interval Between MODE Falling Edge Another Active Data Access Time Data Set-up Time Data Hold Time
SYMBOL FADDR FCLK FCTRL TGCC TGCA
CONDITIONS Page coding mode Read/Write mode Write mode Page coding mode Block erase mode Mode selection
MIN.
TYP.
MAX.
UNIT
Mode selection
Read mode Write mode Read mode Write mode Write mode Whole-chip-erase mode Block-erase mode
Programming Duration Whole-chip-erase Time Block-erase Time
Preliminary W928C73
APPLICATION CIRCUIT
Key2
Key1
76.8K
Key0
RESET
SEG29 SEG28 SEG27 SEG26 SEG25 SEG24
Motor Buzzer From bat_det Signal_in RFEN PLEN
P1.5 P1.6 P1.7 BL_RF TEST1 (NC) TEST2 (NC) PSEN (NC)
W928C73
LQFP
SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15
PLL/EP_1 PLL/EP_2 PLL/EP_3
P3.0 P3.1
SEG14
Battery detector
Publication Release Date: June 2000 Revision
Preliminary W928C73
Headquarters
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, Creation III, Kwun Tong Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice Fax-on-demand: -2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 First Street, Jose, 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, 115, Sec. -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: data specifications subject change withou notice.
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