Address Sequencer Intersil HSP45240 high speed Address Sequencer

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Address Sequencer Intersil HSP45240 high speed Address Sequencer

Datasheet Thumbnail

Top Searches for this datasheet

HSP45240
Address Sequencer
Intersil HSP45240 high speed Address Sequencer which provides specialized addressing functions like FFTs, filtering, matrix operations, image manipulation. sequencer supports block oriented addressing large data sets 24-bits clock speeds 50MHz. Specialized addressing requirements using onboard crosspoint switch. This feature allows mapping address bits output address generator address outputs chip. result, reverse addressing, such that used FFTs, made possible. single chip solution read/write addressing also made possible configuring HSP45240 12-bit sequencers. compensate system pipeline delay, programmable delay provided address outputs. HSP45240 manufactured using advanced CMOS process, power fully static design. configuration device controlled through standard microprocessor interface inputs/outputs, with exception clock, compatible.
September 1997
Features
Block Oriented 24-Bit Sequencer Configurable Independent 12-Bit Sequencers Crosspoint Switch Programmable Delay Outputs Multi-Chip Synchronization Signals Standard Interface 100pF Drive Outputs 50MHz Clock Rate
Applications
1-D, Filtering Pan/Zoom Addressing Processing Matrix Math Operations
Ordering Information
PART NUMBER HSP45240JC-33 HSP45240JC-40 HSP45240JC-50 HSP45240GC-33 HSP45240GC-40 HSP45240GC-50 TEMP. RANGE (oC) PACKAGE PLCC PLCC PLCC PKG. N68.95 N68.95 N68.95 G68.A G68.A G68.A
Block Diagram
STARTOUT ADDVAL DONE BLOCKDONE STARTIN START CIRCUITRY SEQUENCE GENERATOR CROSSPOINT SWITCH OUT12-23 DELAY OUT0-11 PROCESSOR INTERFACE BUSY
DLYBLK
D0-6,
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. Rights Reserved
File Number
2489.3
HSP45240 Pinouts
ADDRESS SEQUENCER HSP45240 PLASTIC LEADED CHIP CARRIER (PLCC)
OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 DLYBLK STARTIN STARTOUT ADDVAL BUSY BLOCKDONE DONE OUT0 OUT1 OUT2 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3
GRID ARRAY (PGA) BOTTOM VIEW
DLYBLK
START START
BLOCK DONE
OUT1
OUT2
BUSY
DONE
OUTO
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT22
OUT21
OUT18
OUT17
OUT14
OUT23
OUT20
OUT19
OUT16
OUT15
OUT13
HSP45240 Descriptions
NAME TYPE PLCC NUMBER power supply pin. GROUND. DESCRIPTION
RESET: This active input causes chip reset which lasts clocks after been deasserted. reset initializes Crosspoint Switch some configuration registers described Processor Interface Section. chip must clocked reset complete. CLOCK: "CLK" signal CMOS input which provides basic timing address generation. WRITE: rising edge this input latches data/address D0-6 latched into Processor Interface. CHIP SELECT: This active "low" input enables configuration data/address D0-6 latched into Processor Interface. ADDRESS This input defines D0-6 configuration register address "high", configuration data "low", (see Processor Interface text). DATA BUS: Data Processor Interface. OUTPUT ENABLE HIGH: This asynchronous input used enable output buffers 12-23. OUTPUT ENABLE LOW: This asynchronous input used enable output buffers OUT0-11. START-IN: This active input initiates addressing sequence. tied STARTOUT another H5P45240 multichip synchronization. STARTIN should only asserted because address sequencing begins after STARTIN deasserted. DELAY BLOCK: This active "high" input used halt address generation address block boundaries (see Sequence Generator text). required timing relationship this signal address block shown Application Note 9205. OUTPUT BUS: compatible 24-bit Address Sequencer output.
D0-6 STARTIN
11-17
DLYBLK
OUT0-23
62-64,
BLOCK DONE DONE ADDVAL START-OUT
BLOCK DONE: This active output signals when last address address block OUT0-23. DONE: This active output signals when last address address sequence OUT0-23. ADDRESS VALID: This active output signals when first address address sequence 0UT0-23. START-OUT: This active output generated when address sequence initiated mechanism other than STARTIN. tied STARTIN other H5P45240's multichip synchronization. BUSY: This active output asserted after deasserted will remain asserted CLK's. While BUSY asserted, writes Processor Interface disabled.
BUSY
NOTE: #Denotes active low.
HSP45240 Functional Address Sequencer 24-bit programmable address generator. shown Block Diagram, sequencer consists functional blocks: start circuitry, sequence generator, crosspoint switch, processor interface. addresses produced sequence generator input into crosspoint switch. crosspoint switch maps bits address input 24-bit output. This allows addressing schemes like "bit-reverse" addressing FFT's. programmable delay block provided allow output skewed from LSW. This feature used compensate processor pipeline delay when sequence generator configured independent 12-bit sequencers. Address Sequencer operation controlled values loaded into configuration registers associated with sequence generator, crosspoint switch, start circuitry. configuration registers loaded through processor interface. shown Figure Sequence Generator subdivided into address generation control sections. address generation section performs accumulation based output MUX1 MUX2. control section governs operation multiplexers, enables loading Block Start Address register, signals completion address sequence. address sequence started when control section Sequence Generator receives internal START signal from Start Circuitry. When START signal received, control section multiplexes contents Start Address Register adder. result this summation first address first block address sequence. This value stored Block Start Address register enable generated from control section, multiplexers switched feed output Holding Address Increment registers adder. Address generation will continue with Address Increment added contents Holding Register until first address block been completed. address block completed when number addresses generated since beginning address block equals value stored Block Size register. When last address block generated, BLOCKDONE asserted signal address block (see Application Note 9205). following CLK, multiplexers configured pass contents Block Start Address Block Increment registers adder which generates first address next address block. enable from control section allows this value update Block Start Address register, multiplexers switched feed Holding Address Increment registers adder generation remaining addresses block. address sequence completed when number address blocks generated equals value loaded into Number Blocks register. When final address last address block been generated, DONE BLOCKDONE asserted signal completion address sequence. parameters governing address generation loaded into five 24-bit configuration registers Processor Interface. These parameters include Start Address, beginning address sequence; Block Size, number addresses address block; Address Increment, increment between addresses block; Number Blocks, number address blocks sequence (minimum Block Increment, increment between starting addresses each block. loading structure these registers detailed Processor Interface text.
Start Circuitry
Start Circuitry generates internal START signal which causes Sequence Generator initiate addressing sequence. START signal produced writing Processor Interface's "Sequencer Start" address (see Processor Interface text), asserting STARTlN input, terminal address sequence generated under "One-Shot Mode with Restart" (see Sequence Generator Section). Care should taken assert STARTlN only clock cycle ensure proper operation. programmable delay from clocks provided delay initiation addressing sequence delaying internal START signal (see Processor Interface text). Start Circuitry generates output signal ADDVAL which asserted when first valid output address pads. addition, Start Circuitry generates "STARTOUT" signal multichip synchronization. Note: STARTOUT only generated when addressing sequence started writing "Sequencer Start" address Processor Interface, internal START generated reaching addressing sequence produced "One-Shot Mode with Restart".
Sequence Generator
Sequence Generator block oriented address generator. This means that desired address sequence subdivided into more address blocks, each containing user defined number addresses. User supplied configuration data determines number address blocks characteristics address sequence generated.
HSP45240
CURRENT BLOCK START ADDRESS
HOLDING REGISTER CROSSPOINT SWITCH
STEP SIZE
START ADDRESS
BLOCK STEP SIZE
ADDRESS GENERATION TEST MODE DATA CONTROLS/ REGISTER ENABLES CONTROL
BLOCK SIZE
DONE NUMBER BLOCKS SEQUENCE GENERATOR CONTROL BLOCKDONE DLYBLK MODE
"START"
FIGURE SEQUENCE GENERATOR BLOCK
Three modes operation selected loading 6-bit Mode Control register (see Processor Interface). three modes operation are: One-Shot Mode without Restart Address generation halts after completion user specified address sequence. Address generation will resume until internal START signal generated Start Circuitry. When final address final block address sequence generated, both DONE BLOCKDONE asserted last address held OUT0-23 (See Application Note 9205). One-Shot Mode with Restart: This mode identical One-Shot Mode without Restart with exception that Start Circuitry automatically generates internal START user specified sequence restart address generation. address sequence signaled assertion DONE, BLOCKDONE, STARTOUT shown Application Note 9205. this mode, first address next sequence immediately follows last address current sequence start delay disabled. Continuous Mode: Address generation never terminates. Address generation proceeds based Start Address, Address Increment, Block Size, Block Increment Parameters. Number Blocks parameter ignored, DONE signal never asserted. Mode Control register also used configure Sequence Generator operation independent 12-bit address sequencers. dual sequencer mode, adder sequence generator suppresses carry from LSBs MSBs. With carry suppressed, inde-
pendent sequences produced. These 12-bit address sequences delayed relative each other programming Mode Control register delay clocks. This feature useful compensate pipeline delay when using dual sequencer mode generate read/write addressing. DLYBLK input used halt address generation address block within sequence. addition, DLYBLK used delay address sequence from restarting asserted final address block generated under "One-Shot Mode with Restart". Application Note 9205 timing relationship DLYBLK address block required halt address sequencing.
Crosspoint Switch
crosspoint switch responsible reordering address bits output sequence generator. switch allows inputs independently connected outputs. crosspoint switch outputs driven only input, however, input drive number switch outputs. none inputs mapped particular output bit, that output will "low". input output configured through processor interface. stored bank configuration registers. Each register corresponds output bit. output mapped input value, stored register. After power-up, user option configuring switch mode using reset input, "RST". mode crosspoint switch outputs same order input. More details configuring switch registers contained Processor Interface text.
HSP45240 Processor Interface
Processor Interface consists microprocessor interface register bank which holds configuration data. data loaded into register bank first writing register address processor Interface then writing data. auto address increment mode provided that base address written followed number data writes. microprocessor interface consists data (D06), address select (A0) specify D0-6 either address data, write input (WR) latch data into Processor Interface, chip select input (CS) enable writing interface. Processor Interface input decoded either data address shown Table
TABLE REGISTER ADDRESSES Switch Output Registers. Sequencer Starting Address. Sequencer Block Size. Sequencer Number Blocks. Sequencer Block. Address Increment. Sequencer Address. Increment. Mode Control. Test Control. Start Delay Control. Address Sequencer "START". DATA WORDS Current Address Data. Address Increment). Current Address Data (Address Increment). NOTES: Table means "don't care", denotes bits which decoded address address registers data data registers. When transitions "high" write Sequencer "Start" address (1x111111), must remain high until after rising edge clock. Otherwise, sequencer "start" signal will generated.
include: Address Start, Block Size, Number Blocks, Block Increment, Address Increment. Each register maps five 24-bit configuration registers Sequence Generator block (see Sequence Generator). mapping 6-bit registers register bank 24-bit configuration registers determined LSBs register address. higher value LSBs higher relative mapping 6-bit register 24-bit register. example, LSBs register address both register contents will LSBs configuration register. register bank registers which contain data Cross point Switch mapping. These registers accessed LSBs address Crosspoint Mapping registers Table value from accesses mapping registers OUTO-23 respectively. value greater than ignored. output represented particular register mapped input 6-bit value loaded into register. value loaded into register exceeds corresponding output will "0". example, LSBs Crosspoint Mapping address equal valued loaded into register accessed this address equal OUT3 would mapped sequence generator output. After reset, Mode Control, Test Control, Start Delay registers reset described section describing each register's map; Crosspoint Mapping registers reset crosspoint switch mapping; registers which hold five address generation parameters affected. save user expense alternating between address data writes, auto address increment mode provided. address increment mode invoked performing data writes with location data word shown Table example, crosspoint switch could configured writes Processor Interface (one write starting address crosspoint mapping registers followed data writes those registers). Mode Control Register Mode Control Register used control operation sequence generator. addition, also controls output delay between OUTO-23. following tables illustrate structure mode control register.
TABLE MODE CONTROL REGISTER FORMAT ADDRESS LOCATION: 1x11O1OO
register bank consists series 6-bit registers which addressed individually shown Table data these registers down loaded into configuration registers Start Circuitry, Sequence Generator, Crosspoint Switch when address sequence initiated internal START signal (see Start Circuitry). This double buffered architecture allows configuration data down loaded Processor Interface while address sequence being completed using previous configuration data. register bank five sets four registers which contain address generation parameters. These parameters
HSP45240
Output Delay: Delays OUTO-1 from OUT12-23 following number clocks.
Output Delay Output Delay Output Delay Output Delay Output Delay Output Delay Output Delay Output Delay
Start Delay: Delays "START" decoded number clocks.
Start Delay Start Delay Start Delay Start Delay
During reset, this register will reset zeros. This will bring chip mode with Start Delay disabled. Test Control Register Test Control Register provided configure sequence generator produce test sequences. this mode, sequence generator configured multiplex contents down counters sequence generator control circuitry, Figure These counters used determine when block sequence complete. shown Figures down counters multiplexed address generator output. addition, test mode provided which sequence generator performs shifting operation contents start address register. structure Test Control Register shown Table
ADDRESS GENERATION SECTION DONE REGISTERED NUMBER BLOCKS CONTROL BLOCKDONE DLYBLK CONTROLS/ REGISTER ENABLES
Dual Sequencer Enable: Allows independent 12bit sequences generated.
24-bit sequence generated. 12-bit sequences generated.
Mode: Sequencer Mode.
One-Shot Mode without Restart. One-Shot Mode with Restart. Continuous Mode don't care).
During reset, this register will reset zeroes. This will configure chip 24-bit sequencer with zero delays outputs. chip will also one-shot mode without restart. Start Delay Control Register Start Delay Control Register used configure start circuitry delayed starts from clock cycles. Internal "START", external "START", restarts will delay programmed amount. structure Start Delay Control Register shown Table
TABLE START DELAY CONTROL REGISTER FORMAT ADDRESS LOCATION: 1x110110
REGISTERED BLOCK SIZE
"START"
REGISTERED MODE
FIGURE SEQUENCE GENERATOR CONTROL TABLE TEST CONTROL REGISTER FORMAT ADDRESS LOCATION: 1x110101
Start Delay Enable: Enables "START" delayed programmed amount. When Start Delay enabled, minimum required programmed delay.
Start Delay Disabled. Start Delay Enabled.
Bits "D5" "D6" currently used. Shifter Enable: Input crosspoint switch generated shifting Start Address Register clock.
HSP45240
Sequence Generator Functions Normally. Sequence Generator Functions Shift Register.
Counter Output Enable: Enable contents down counters sequence generator control circuitry muxed MSBs address generator output.
Disable Muxing down counters. Enable Muxing down counters.
Counter Select: Selects which 12-bit word down counters muxed address generator output.
Select Counter bits 0-11. Select Counter bits 12-23. Select Counter bits 0-11. Select Counter bits 12-23.
FIGURE SEQUENCER IMAGE ADDRESSING
During reset, this register will reset zeroes. This will bring chip mode with test features disabled.
sub-image address sequence shown Figure generated configuring sequence generator with following: Start Address Block Size Step Size Block Step Size
Applications
Image Processing application shown Figure uses HSP45240 Address Sequencer satisfy addressing requirements simple image processing system. this example controller configures sequencers generate specialized addressing sequences reading writing frame buffers. typical mode operation this system might perform edge detection subsection image stored frame buffer. this application, data Convolver address sequence driving input frame buffer. graphical interpretation sub-image addressing shown Figure Each figure corresponds image pixel stored memory. assumed that pixel values stored row. example, first memory locations would contain first pixel values. 17th memory location would contain first pixel second row.
INPUT FRAME BUFFER HSP48808 CONVOLVER FRAME BUFFER OUTPUT
Number Blocks
this example start address corresponds address first pixel first row. length corresponds Block Size which programmed Within block, consecutive addresses generated programming Step Size completion first block addresses, Block Step Size added Start Address generate address first pixel second row. Finally, rows addressing generated setting Number Blocks this application, sub-image processed time then sub-image area chosen. result, Mode Control Register would configured One-Shot mode without Restart. Also, Start Delay Control register Sequencer driving output frame buffer would configured with start delay compensate pipeline delay introduced Convolver. Finally, crosspoint switch would configured mode that sequence generator output mapping chip output. applications requiring decimation original image, Step Size could increased provide addressing which skips over pixels along row. Similarly, Block Step Size could increased such that pixel rows skipped. Processing
ADDRESSING HSP45420 SYNC SEQUENCER
ADDRESSING HSP45420 SEQUENCER
CONTROLLER
FIGURE IMAGE PROCESSING SYSTEM
application shown Figure depicts architecture simplified radix processor. this application Address Sequencer drives memory bank which feeds arithmetic processor with data. radix implementation, arithmetic processor takes complex data inputs
HSP45240
produces results. These results then stored registers from which data came. This type implementation referred place" algorithm. arithmetic processing unit performs operation know radix butterfly which shown graphically Figure this diagram node center butterfly represents summing point while arrow represents multiplication point. flow computation described diagrams comprised many butterflies shown Figure processing shown Figure consists three stages radix butterfly computation. read/write addressing, expressed binary, each stage shown Table specialized addressing required here produced using crosspoint switch address bits from sequence generator chip output. mapping sequencer's crosspoint switch determined, inspecting addressing each stage. example, first stage addressing generated configuring crosspoint switch that switch input mapped switch output, switch input mapped output, switch input mapped switch output. remainder switch configured 1:1, i.e., bit-3 switch input mapped switch output. Under this configuration, sequence generator output 0,1,2,3,4,5,6,7 will produce crosspoint switch output 0,4,1,5,2,6,3,7. switch maps other stages, well bit-reverse addressing result given Table serial count required input crosspoint switch generated configuring sequence generator with following: Start Address Block Size Step Size Block Step Size switch mapping changes each stage computation. Thus, while address sequence being completed, crosspoint switch being configured next stage addressing. When stage addressing complete, switch configuration loaded into current state registers internal externally generated start restart. crosspoint switch configured first stage addressing writing switch output register switch output register switch output register These values loaded first writing address switch output register then loading data using autoaddress increment mode (see Table remaining registers assumed configured mode result prior "RESET". second third stages addressing generated reconfiguring above three registers. Address Sequencer configured dual sequencer mode provide both read write addressing each butterfly. Since independent 12-bit sequences generated Address Sequencer, used provide read/write addressing FFT's 4096 points. programmable delay between Sequencer output used compensate pipeline delay associated with arithmetic processor.
TABLE ADDRESSING COMPUTATIONAL STAGE STAGE R/WADDR. SWITCH MAPPING STAGE R/W/ADDR. STAGE R/W/ADDR. OUTPUT ADDRESSING
Number Blocks
Under this configuration sequence generator will produce count from increments length corresponds Block Size, this case serial count from sequence generator converted into desired addressing sequence applying appropriate crosspoint switch. this application,
HSP45240
HSP45240 SEQUENCER
MEMORY
CONTROLLER
ARITHMETIC PROCESSOR
FIGURE PROCESSOR
X=A+B
LENGTH =e-j
FIGURE BUTTERFLY DECIMATION-IN-FREQUENCY
X(0) X(1) X(2) X(3) X(4) X(5) X(6)
X(0)
X(4) X(2)
X(6) X(1) X(5) X(3) X(7)
X(7)
FIGURE COMPLETE EIGHT-POINT-IN-PLACE DECIMATION-IN-FREQUENCY
HSP45240
Absolute Maximum Ratings
25oC
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) PLCC Package 43.1 15.1 Package 37.1 10.1 Maximum Package Power Dissipation 70oC PLCC Package 1.86W Package 2.84W Maximum Junction Temperature PLCC Package 150oC Package 175oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC
Supply Voltage +8.0V Input, Output Voltage Applied. -0.5V +0.5V Classification Class
Operating Conditions
Temperature Range .+5.0V Voltage Range 70oC
Characteristics
Number Transistors Gates 8388 Gates
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Logical Input Voltage Logical Zero Input Voltage High Level Clock Input Level Clock Input Output HIGH Voltage Output Voltage Input Leakage Current Leakage Current Standby Power Supply Current
5.0V 70oC SYMBOL VIHC VILC ICCSB ICCOP TEST CONDITIONS 5.25V 4.75V 5.25V 4.75V 400µA, 4.75V +2.0mA, 4.75V GND, 5.25V VOUT GND, 5.25V GND, 5.25V, Outputs Open 33MHz, GND, 5.25V, Outputs Open, (Note 1MHz, Open, Measurements referenced device GND. (Note UNITS
Operating Power Supply Current
Input Capacitance Output Capacitance NOTES:
Power supply current proportional operating frequency. Typical rating ICCOP 3mA/MHz. tested, characterized initial design major process/design changes.
HSP45240
Electrical Specifications
PARAMETER Clock Period Clock Pulse Width High Clock Pulse Width Setup Time D0-6 High Hold Time D0-6 from High Setup Time Hold Time from High Pulse Width Pulse Width High Cycle Time Setup Time STARTIN, DLYBLK Clock High Hold Time STARTIN, DLYBLK Clock High Clock Output Prop., Delay OUT0-23 Clock Output Prop. Delay STARTOUT, BLKDONE, DONE, ADDVAL BUSY Output Enable Time Output Disable Time Output Rise/Fall Time Time NOTES: Controlled design process parameters directly tested. Characterized upon initial design after major process and/or design changes. Testing performed follows: Input levels (CLK input) 4.0V input levels (all other inputs) 3.0V; input timing reference levels: (CLK) 2.0, Others) 1.5V; Output timing references: 1.5V, 1.5V. 5.0V +5%, 70oC, (Note (33MHz) SYMBOL tWRL tWRH tPDO tPDS tORF tRST Note Note NOTES (40MHz) (50MHz) UNITS
Clock Cycles
Test Load Circuit
OUTPUT BLOCKDONE DONE ADDVAL STARTOUT BUSY OUTTO-23
40pF
(NOTE
100pF
1.5V
EQUIVALENT CIRCUIT
NOTES: Includes stray capacitance. Switch Open ICCSB ICCOP Tests.
HSP45240 Timing Diagrams
D0-6
FIGURE CLOCK PARAMETERS
FIGURE DATA SETUP HOLD
tWRH
tWRL
FIGURE ADDRESS/CHIP SELECT SETUP HOLD
FIGURE PARAMETERS
OUTO STARTIN DLYBLK STARTOUT BLOCKDONE DONE ADDVAL BUSY tPDS tPDO
FIGURE INPUT HOLD
FIGURE OUTPUT PROPAGATION DELAY
OEL, OUT0 1.7V 1.3V tORF 2.0V 0.8V tORF
FIGURE OUTPUT ENABLE, DISABLE TIMING
FIGURE OUTPUT RISE FALL TIMING
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com

Address Sequencer Intersil HSP45240 high speed Address Sequencer

Top Searches for this datasheet

Other recent searches