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Preliminary W89C982AF INTEGRATED MULTIPLE REPEATER
GENERAL DESCRIPTION. FEATURES. ORDERING INFORMATION. SYSTEM DIAGRAM CONFIGURATION DESCRIPTION BLOCK DIAGRAM FUNCTIONAL DESCRIPTION Interface Twisted Pair Line Transceiver Link Test Function.8 Automatic Polarity Reversal Function Port Partition/Reconnection Logic.9 Port Status Direct Report Function Initial State After Reset Management Logic Management Interface IMPR Programmable Options.15 IMPR Kernel Logic.15 Inter-IMPR Interface.16 ABSOLUTE MAXIMUM RATINGS CHARACTERISTICS CHARACTERISTICS System Clock Timing.19 Reset Timing.19 Management Clock Timing.20 Management Carrier Sense Timing.20 Inter-IMPR Interface Input Timing Inter-IMPR Interface Output Timing Inter-IMPR Interface Collision Timing.23 Inter-IMPR Interface AUI/TP Port Timing.23 Output Driver Timing.24 Repetition Timing (part Repetition Timing (part Link Test Timing.26 PACKAGE DIMENSIONS
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
GENERAL DESCRIPTION
Integrated Multiple Port Repeater (IMPR implements repeater functions specified section IEEE 802.3 standard twisted pair line transceiver functions conforming 10BASE-T standard. IMPR provides eight Twisted Pair (TP) Line Transceiver Ports Attachment Unit Interface (AUI) port. Each Twisted Pair (TP) Line Transceiver Port connect Ethernet segment through twisted pair line. port connect thick Ethernet segment means 50-meter cable. IMPR provides AUI/TP port status direct report function, which uses port status pins select pins indicate collisions, port link/activity, partition, polarity, network utilization. inter-IMPR interface includes signals connecting more than IMPR increase total number ports. manageable functions repeater twisted pair line transceiver IMPR accessed through serial interface.
FEATURES
Functions conform IEEE 802.3 section specifications Single power supply CMOS process lower power dissipation Twisted-Pair (TP) line media interface compatible with BASE-T specifications Differential interface compatible with specifications Port status direct report function Asynchronous Inter-IMPR interface large applications Serial management interface allows network management makes port status information accessible port carrier sense signals observable through port activity monitor port Internal main state machine performs fragment extension, packet repetition, collision handling functions Internal jabber lockup protection state machine monitors length each input packet prevent transmission excessively large packets Separate partition state machine each port port isolate ports when excessive number collisions occur reconnect them using certain algorithms On-chip PLL, Manchester encoder/decoder, FIFO
ORDERING INFORMATION
TYPE W89C982AF PACKAGE 100-pin
Preliminary W89C982AF
SYSTEM DIAGRAM
Inter-IMPR Interface Mngrmnt Controller IMPR Mngrmnt Preequalizer Port status direct report Twisted-pair Media
CONFIGURATION
TDDTT
RD6RD6+ RD5RD5+ RD4RD4+ AVDD RD3RD3+ RD2RD2+ RD1RD1+ AVss RD0RD0+ DIDI+ CICI+
TP1RPT TP0RPT AUIRPT XCOLRPT ICRS IDAT IDCLK DVss IJAM ICOL IBEN TEST DVss PCRS
W89C982AF
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
DESCRIPTION
NETWORK INTERFACE PINS NAME DONO. DESCRIPTION Transmit Output: Differential line driver that sends differential signal Medium Attached Unit (MAU). These pins require pull-down resistor GND. Receive Input: Differential receiver that receives AUI-compliant receive signal from MAU. Collision Input: Differential receiver that receives AUI-compliant collision signal from MAU. Data Positive: Transmit data driver positive that transmits data twisted pair line. driver will source sink driver during idle. Data Negative: Transmit data driver negative that transmits inverted data twisted pair line. driver will source sink Driver during idle. Delayed Data Positive: Transmit data driver positive that transmits delayed inverted data twisted pair line. driver will source sink Driver during idle. Delayed Data Negative: Transmit data driver negative that transmits delayed data twisted pair line. driver will source sink during idle. Twisted Pair Line Receive Positive: Positive data from twisted pair line received internal receiver through this pin. Twisted Pair Line Receive Negative: Negative data from twisted pair line received internal receiver through this pin. INTER-IMPR INTERFACE PINS
ICRS
DICI+ CIDT0+ DT7+ DT0to DT7DD0+ DD7+ DD0to DD7RD0+ RD7+ RD0to RD7-
100,
Inter-IMPR Carrier Output: inter-IMPR carrier active this pin) will present when IMPR repeating packets. IMPR output this signal interface inter-IMPR retransmitting valid packets propogating network collision messages other IMPR IIs.
Preliminary W89C982AF
Continued
INTER-IMPR INTERFACE PINS NAME
IBEN
DESCRIPTION Inter-IMPR interface Enable: IBEN driven integrator. integrator will drive IBEN there only IMPR which outputs ICRS inter-IMPR interface. IMPR that asserts ICRS will allowed transmit valid messages IMPR integrator when IBEN low. Inter-IMPR Collision: ICOL will driven when more than IMPR simultaneously output ICRS IMPR integrator. IMPR will transmit data IMPR integrator when ICOL low. this situation collision messages will still sent ports IMPR Inter-IMPR Data Clock: IDCLK will drive clock output when ICRS asserted IBEN driven. ICRS asserted IBEN driven, IDCLK will driven IDCLK signal another IMPR dumb used, i.e., IBEN present, this high impedance. This synchronous IDAT data. Inter-IMPR Data: IMPR sends/receives valid packets inter-port collision messages to/from other IMPR through IDAT format. IDAT high-Z state during inter-IMPR collisions when network idle. IDAT remains high when there transmit collision IMPR Inter-IMPR IJAM: IJAM driven when valid packet being sent. IJAM driven high when IDAT carries collision message (i.e., always high always low). IDAT indicates multiport collision IDAT indicates single port collision condition. During inter-IMPR collisions when network idle, IJAM should high-Z state. MANAGEMENT PINS IMPR Reset: IMPR will forced into initial state when driven low. Management Clock: management data clocked MCLK serially. rising edge MCLK will latch data into IMPR
ICOL
IDCLK
IDAT
IJAM
MCLK
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
Continued
MANAGEMENT PINS NAME DESCRIPTION Management Data management command serially clocked into IMPR MCLK. Management Data Out: network status internal management status IMPR serially read from whenever IMPR receives status read command. IMPR Test Mode: This should tied high during test mode tied during normal operations. Network Port Carrier Sense: carrier sense signals IMPR II's internal logic from port eight ports serially sampled output through PCRS. output bits stream synchronized clock. Network Port Carrier Sense Strobe: serial stream PCRS latched external latch using signal. goes high clock cycles after nine carrier sense bits output through PCRS. System Clock Input: external system clock source connected this provide operating clock. crystal applications, crystal connected across pins Crystal Clock Feedback: should left floating when external clock source used.
TEST
PCRS
PORT STATUS DIRECT REPORT INTERFACE PINS Port Status Direct Report Select Pins: These pins control output status port status pins. Four output states selected XCOLRPT Link/Activity Partition Polarity error COL/Activity Partition Loopback error Utilization Utilization
Collision Status Direct Report Output: Whenever collision event occurs, this active high. This drives data buffer, which directly drives LED.
Preliminary W89C982AF
Continued
PORT STATUS DIRECT REPORT INTERFACE PINS NAME DESCRIPTION Port Status Direct Report Output: This outputs port status selected M0/M1. This drives data buffer, which directly drives LED. Port Status Direct Report Output: These pins output port status selected M0/M1. These pins drive data buffer, which directly drives LED. POWER GROUND PINS AVDD Receive Power Supply: power supply. This should decoupled with capacitor kept separate from other power ground planes. AVSS DVDD DVSS Receive Ground: Grounding pins. Power Supply: power supply. This should decoupled with capacitor kept separate from other power ground planes. Ground: Grounding pins. Digital Power Supply: power supply. Digital Ground: Grounding pins. Power Supply Transmit/Port Status Pins: power supply. Ground Transmit/Port Status Pins.
49-51, 54-58
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
BLOCK DIAGRAM
Port Partition/ Reconnection Logic Decoder
Twisted Pair Line Transceiver
Inter-IMPR Interface
Timer Counters
Main state Machine Glue logic
FIFO Control Logic
FIFO
Jabber lockup Fragment extension Logic
Preamble/ Generator
Twisted Pair Line Transceiver
Encoder Transmitter Logic
Interface
Management Logic
Management Interface
Port status direct report
FUNCTIONAL DESCRIPTION
Integrated Multiple Port Repeater implements functions stipulated IEEE repeater specifications, functions specified 10BASE-T standards, functions network management. provides Inter-IMPR interface allow implementation repeater with more network ports. block functions IMPR described below.
Interface Twisted Pair Line Transceiver
provides interface external Medium Attached Unit (MAU) connected IMPR IMPR used connect 10BASE2 10BASE5 Ethernet 10BASE-T Ethernet coaxial transceiver. Twisted Pair Line Transceiver provides interface used connect IEEE 802.3 stations (Data Terminal Equipment, DTEs) into Ethernet networks constructed from twisted pair media. Twisted Pair Line Transceiver also contains link test function autopolarity reversal function wiring detection.
Link Test Function
link test function port used check whether port linked active port. port will enter link fail state does receive packets link test pulses more than until receives either consecutive link pulses packet. When port link
Preliminary W89C982AF
fail state, IMPR will transmit signal (packets link pulses) port first input packet will retransmitted. IMPR will transmit link test pulses port after transmitter port been inactive more than after port enters link good state. link test function port user-programmable using management functions IMPR port forced into link good status link test function disabled. link test function enabled default each time IMPR reset.
Automatic Polarity Reversal Function
automatic polarity reversal function checks polarity input data packets link pulses. polarity port will negative when polarity first input packet first three consecutive link pulses following reset following entry port into link fail state detected negative. Once polarity port negative, consequent input packets will retransmitted with data that inverted with respect input packet after port enters link good state. polarity port negative, input packets will retransmitted without modification data polarity. Once polarity port determined, polarity this port will updated until IMPR either reset re-enters link fail state, regardless whether automatic polarity reversal function disabled enabled. automatic polarity reversal function user-programmable using management functions IMPR enabled default each time IMPR reset. default status polarity "correct" when IMPR reset state.
Port Partition/Reconnection Logic
port partition/reconnection logic implements segment partitioning algorithm segment reconnection algorithm. These algorithms defined IEEE specifications used protect network from malfunctioning segments. There nine partition/reconnection machines IMPR Each port partition reconnection machine controls individual network port. network port will partitioned IMPR when either following conditions detected: collision condition exists continuously period 1024 times. Thirty-two consecutive collisions occur. collision condition defined more than network ports attempting transmit simultaneously receive collision from AUI. IMPR reconnect partitioned network port using algorithms selected programming management logic. following reconnection algorithms: Standard reconnection algorithm: partitioned network port will reconnected data packet longer than times retransmitted received from that port without collision. Alternative reconnection algorithm: partitioned network port will reconnected data packet longer than times retransmitted that port without collision. reconnection algorithms ports port programmed individually; however, ports same algorithm. standard algorithm selected default each time IMPR reset.
Port Status Direct Report Function
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
IMPR provides (XCOLRPT) collision status report, pins (M0/M1) port status report mode selection, nine pins port status report (AUIRPT, TP0-7RPT). XCOLRPT active when collision occurs. Each nine port status report pins directly report four aspects port status. Which aspect network status reported these pins determined mode selection pins, shown table below. LINK/ACTIVITY COL/ACTIVITY PARTITION POLARITY LOOPBACK ERROR UTILIZATION UTILIZATION
When "0," pins report link/activity COL/activity. this mode, output AUIRPT TP0-7RPT means ports link fail state, high means ports link good state, collision state, signal means incoming packets being received AUI/TP ports. (Note that signal still reported ports partitioned disabled.) "0," port partition status will reported. this mode, output means that ports connected correctly, means that AUI/TP ports partition state. When "1," loopback errors polarity status will reported. this mode, output means that loopback polarity correct, means that loopback error been detected port polarity reversed. both "1," network utilization will reported. this mode, each stands utilization. percentage network utilization shown following table.
UTILIZATION
Using pins external transistors, IMPR drive LEDs indicate status AUI/TP ports sequentially; application circuit LEDs shown below. simple decoder connected pins switch circuit connected TP0RPT TP7RPT, port link/activity, partition, polarity, network utilization displayed simultaneously.
Preliminary W89C982AF
Collision
W89C982AF
XCOLRPT AUIRPT TP0RPT
TP7RPT
status
select port status output.
Initial State After Reset
When driven low, IMPR reset. minimum time reset signal must held trigger reset During reset, IMPR places outputs inactive state (except auto polarity reversal function). Active outputs stay high, active high outputs stay low, link test enabled, link fail state. AUI/TP auto partition/reconnection uses standard algorithm, AUI/TP transmitters idle, AUI/TP receivers enabled, IDAT IJAM highimpedance state, low, auto polarity reversal function enabled.
Management Logic Management Interface
major functions management logic enabling/disabling networks, partitioning/reconnecting network ports, enabling/disabling link test autopolarity reversal functions twisted pair line transceiver, accessing link status polarity status twisted pair line transceiver. management interface signal that contains input/output signals to/from management logic internal carrier sense signals nine network ports IMPR management logic accept execute management commands when IMPR normal mode, i.e., TEST IMPR tied low. management commands byteoriented clocked into IMPR serially external clock. Some commands require output from IMPR response some not. least clocks required send command that requires output response from IMPR clocks needed send command that requires response. serial command data stream associated output response data stream structured manner compatible with RS232 serial data format, i.e., start followed eight data bits, with sent first last.
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
following table summarizes management commands. LSBs both data data shown right MSBs shown left. Each command described more detail below. INPUT DATA 11010000 11100000 10000000 10001111 11110000 10001111 10001011 10001101 10001001 00111111 00101111 00110bbb 00100bbb 01010bbb 01000bbb 01110bbb 01100bbb 00011111 00010000 00001CSA READ DATA M0000000 PBSL0000 PBSL0000 PBSL0000 PBSL0000 None None None None None None None None None None None FUNCTIONS Read link test status ports Read polarity status ports Read partition status ports Read rate error status ports Read MJLP status Read port status cleared) Read port status cleared) Read port status cleared) Read port status (None cleared) Enable port Disable port Enable ports Disable ports Enable port link test function Disable port link test function Enable ports auto polarity reversal function Disable ports auto polarity reversal function port alternate reconnection algorithm port alternate reconnection algorithm IMPR programmable option
Read Link Test Status Ports
link test status eight ports read using this command. Bits through correspond link test status ports through indicates "Link Good" status indicates "Link Fail" status.
Read Polarity Status Ports
polarity status eight ports read using this command. Bits through correspond polarity status ports through indicates reversed polarity indicates positive polarity.
Read Partition Status Ports partition status eight ports read using this command. Bits through correspond polarity status ports through indicates connected status indicates partitioned status.
Preliminary W89C982AF
Read Rate Error Status Ports
rate error status ports read using this command. Bits through correspond polarity status ports through indicates that rate error occurred indicates rate error occurred.
Read MJLP Status
jabber lock-up protection status accessed using this command. indicates transmit function IMPR been inhibited. status also cleared using this command.
Read Port Status
port status, including partition, rate error, test, loopback error, accessed using different variations this command. Four different specific commands used, shown following table. DATA 10001111 10001011 10001101 10001001 DATA PBSL0000 PBSL0000 PBSL0000 PBSL0000 CLEAR BITS read cleared. cleared. read cleared. cleared. read cleared. cleared. cleared.
Enable Port
When disabled, port re-enabled using this command. port will then carry normal transmitting receiving operations. reconnect partitioned port, port must first disabled then re-enabled using this command.
Disable Port
This command used disable port. When port disabled, inputs (the carrier sense SQE) port will ignored IMPR IMPR will transmit signal port. addition, partition machine port will forced into idle status.
Enable Ports
This command used enable disabled port, allowing perform normal transmitting receiving operations. reconnect partitioned port force port into link fail state, port must first disabled then re-enabled using this command.
Disable Ports
Each port disabled individually. Bits used indicate port that disabled, follows:
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
PORT DISABLED
When port disabled, inputs (the carrier sense) that port will ignored IMPR IMPR will transmit signal port. partition machine port will forced into idle state link test will indicate that port "Link Fail" state.
Enable Port Link Test Function
This command used re-enable link-test disabled port. Using this command port that already enabled will have effect port.
Disable Port Link Test Function
port link test function enabled disabled port-by-port. Bits used select which port disabled manner described under "Disable ports" command above. Once link test function disabled, port will enter link fail state.
Enable Port Auto Polarity Reversal Function
auto polarity reversal function ports enabled disabled port-by-port. Bits used indicate which port enabled, manner described under "Disable ports" command above. When auto polarity reversal function enabled, port will check polarity input packets once enters link fail state. This function enabled default each time IMPR reset.
Disable Port Auto Polarity Reversal Function
This command used disable auto polarity reversal function port that port will longer check polarity input packets. input packet with reversed data received, IMPR will correct polarity retransmit packet network ports. this case, failure reverse polarity cause network error.
Port Alternative Reconnection Algorithm
partition/reconnection scheme programmed alternative (transmit only) reconnection algorithm using this command. return partition/reconnection logic port back standard reconnection (transmit receive) algorithm, IMPR must reset.
Port Alternative Reconnection Algorithm
partition/reconnection scheme programmed alternative (transmit only) reconnection algorithm using this command. return partition/reconnection logic port back standard reconnection (transmit receive) algorithm, IMPR must reset.
Preliminary W89C982AF
other main function management logic port activity monitoring function. internal carrier sense signal network ports sampled serially. accuracy carrier sense signals times. first samples internal carrier sense signal port, second samples TP0, third samples TP1, forth. tenth time idle, strobe signal will active during tenth time. With help strobe signal, serial sampled carrier sense signal latched serial-to-parallel shifter.
IMPR Programmable Options
Three IMPR programmable options this command appropriate data. three programmable options reporting, test mask, alternative port activity monitor function, which correspond bits respectively. Reporting Setting will alter function pin. will become input repeater management devices PCRS will insert immediately before bit. Test Mask Setting will disable test when signal within test window pattern will asserted after transmitted packets. test window from times times. When signal larger than test window, collision condition occurred. Alternative Port Activity Monitor Setting will enable alternative function, that repeater management devices monitor status each port using unmodified PCRS signal.
IMPR Kernel Logic
kernel logic IMPR includes main state machine glue logic, timers counters, jabber lockup fragment extension logic, decoder, encoder transmitter, 64-bit FIFO with FIFO control logic, preamble/jam generator. These blocks perform most operations needed fulfill requirements IEEE repeater specification. When packet received connected port, sent receive multiplexer decoder. Data collision status sent main state machine port partition/reconnection logic. This enables main state machine determine source data repeated type data transmitted. transmit data either received packet's data field preamble/jam pattern consisting 1010. pattern. Associated with main state machine series timers counters which ensure that various IEEE specification times (referred times) fulfilled. decoder decodes received data from Manchester code format into format recovers jitter accumulated over receiving segment. preamble/jam generator FIFO compensate preamble loss caused receptions twisted pair line transceiver. FIFO used store bits data field temporarily while preamble/jam generator sending preamble transmitting packet. 1010. pattern generated under network collision conditions. jabber lockup fragment extension logic monitors retransmitted packet. pattern will appended short packets (less than bits length) extend them full bits. jabber
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
lockup fragment extension logic will inhibit encoder/transmitter logic when retransmitted packet more than 65536 bits length. Packet repetition network collision handling performed main state machine according IEEE specifications. Soon after network port receiving data packet been identified, main state machine enables preamble/jam generator generate preamble pattern onto encoder/transmitter. While preamble being transmitted, received data still being monitored. main state machine will enable FIFO control logic read valid data into FIFO when start frame delimiter "SFD" detected. 1011 pattern filled into FIFO before detected. Removal FIFO data begins after 60-bit preamble pattern been sent.
Inter-IMPR Interface
inter-IMPR interface designed large applications. inter-IMPR interface allows minimum four IMPR integrated together implement with twisted pair line ports four ports. external integrator needed handle IMPR IIs. data transfers inter-IMPR interface format certain signals used indicate network status. Signals included inter-IMPR interface allow IMPR cooperate with each other appropriate manner. Those signals include IDAT, IDCLK, IJAM, ICRS IBEN ICOL ICRS IBEN ICOL IJAM, control signals. IDAT IDCLK used transmit receive data when IMPR asserts ICRS external integrator asserted IBEN deasserted ICOL each IMPR IDAT IDCLK transmit data clock IMPR integrator. When IMPR asserted ICRS integrator asserted IBEN deasserted ICOL each IMPR IMPR receives data clock from IDAT IDCLK. When IJAM asserted, indicates that single port collision (IDAT multiport collision (IDAT occurring.
IMPR Integrator ICRSBa IDATa, IBENBa, IDCLKa, ICOLBa IJAMa ICRSBb IDATb, IBENBb, ICRSBc IDCLKb, ICOLBb IJAMb IDATc, IBENBc, IDCLKc, ICOLBc IJAMc
982Aa
982Ab
982Ac
figure above depicts inter-IMPR application circuit. circuit requires external inter IMPR integrator. external integrator integrated ICRS signal from each IMPR generates signals, IBEN ICOL IMPR Each IMPR checks IBEN ICOL handle IDAT, IDCLK, IJAM signal direction.
Note that inter-IMPR uses different clocks source (X1a, X1b, X1c, etc.) construct large scale repeater application.
Preliminary W89C982AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER Operating Temperature Storage Temperature Supply Voltage Input Voltage Output Voltage Lead Temperature (soldering seconds maximum) SYM. VOUT MINIMUM -0.5 -0.5 -0.5 MAXIMUM +0.5 +0.5 UNIT
Note: Exposure conditions beyond those listed under Absolute Maximum Ratings adversely affect life reliability device.
Power Supply
(VDD 4.75 5.25V,
PARAMETER Power Supply Current (idle) Power Supply Current (transmitting with load) Power Supply Current (transmitting with load)
SYMBOL IDDI IDDT IDDL
TYPICA
MAXIMU Note
Note: typical load, each port will require additional current (maximum mA). Less than power will dissipated IMPR remaining power dissipated external load.
CHARACTERISTICS
(VDD 4.75V 5.25V,
Digital
PARAMETER Input Voltage High Input Voltage High Output Voltage (VDD 4.5V) High Output Voltage (VDD 4.5V) Input Leakage Current (Note Input Current (Note Output Leakage Current (VDD 5.5V)
Notes: input pins except those stated Note TEST, IBENB, ICOLB, MSI, these pins been pull pull high.
SYMBOL IIL1 IIL2
MINIMUM -0.5 3.85
MAXIMUM +0.5
UNIT
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
PARAMETER Input Current CI+/-, DI+/- pairs Differential Output Voltage (DO+/-) Differential Output Voltage Imbalance (DO+/-) Undershoot Voltage (DO+/-) Differential Squelch Threshold (CI+/-, DI+/-) Differential Input Common Mode Voltage (DI+/-, CI+/-) SYM. -175 +/-550 MIN. MAX. +/-1200 -300 UNIT
Twisted Pair
PARAMETER Power Supply Voltage Input Voltage RD+/- Differential Input Resistance RD+/- Differential Input Voltage (VDD RD+/- Squelched Threshold RD+/- Squelched Threshold RD+/- Input Switching Threshold DT+, DT-, DD+, Imbalance Voltage DT+, DT-, DD+, High Output Voltage DT+, DT-, DD+, Output Voltage DT+, DT-, DD+, Output Current DT+, DT-, DD+, Output Resistance Capacitance SYM. VTIV VTPS VTPU VRDT VTDU VTOH VTOL
-0.44
MIN. -0.3 ±0.3 ±300 ±150
TYP.
MAX. +0.3 ±3.1
±400 ±220
±585 ±300
+0.44
Preliminary W89C982AF
CHARACTERISTICS
(VDD 4.75V 5.25V,
System Clock Timing
DESCRIPTION clock rising time clock falling time clock period clock high clock FIG. 49.995 22.5 22.5 MIN. TYP. MAX. 50.005 27.5 27.5 UNIT
System Clock Timing Diagram
Figure
Reset Timing
DESCRIPTION Reset pulse width hold time with respect clock High setup time with clock rising time FIG. MIN. TYP. MAX. UNIT
Reset Timing Diagram
Figure
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
Management Clock Timing
DESCRIPTION MCLK Clock Rising Time MCLK Clock Falling Time MCLK Clock Period MCLK Clock High MCLK Clock Input Data Setup Time with Respect MCLK Rising Edge Input Data Hold Time with Respect MCLK Rising Edge Output Data Delay with Respect MCLK Rising Edge FIG. MIN. MAX. UNIT
Management Clock Timing Diagram
MCLK
Figure
Management Carrier Sense Timing
DESCRIPTION Rising Edge High Rising Edge Rising Edge Valid PCRS FIG. MIN. TYP. MAX. UNIT
Management Carrier Sense Timing Diagram
PCRS
Figure
Preliminary W89C982AF
Inter-IMPR Interface Input Timing
DESCRIPTION Receive-in IDAT/IJAM setup time receive-in IDCLK rising Receive-in IDAT/IJAM hold time from receive-in IDCLK rising FIG. MIN. TYP. MAX. UNIT
Inter-IMPR Interface Input Timing Diagram
High_Z
IDCLK
High_Z
ICRSB
IBENB
ICOLB IDAT IJAM
Figure
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
Inter-IMPR Interface Output Timing
DESCRIPTION
ICRS asserted IBEN asserted ICRS deasserted IBEN deasserted
FIG.
MIN.
TYP.
MAX.
UNIT
Transmit-out IDAT/IJAM setup time transmit-out IDCLK rising Transmit-out IDAT/IJAM hold time from transmit-out IDCLK rising
Inter-IMPR Interface Output Timing Diagram
High_Z
High_Z
IDCLK ICRS
IBEN ICOL IDAT IJAM
Figure
Preliminary W89C982AF
Inter-IMPR Interface Collision Timing
DESCRIPTION
ICRS asserted ICOL assertion ICRS deasserted ICOL dessertion
FIG.
MIN.
TYP.
MAX.
UNIT
Inter-IMPR Interface Collision Timing Diagram
ICRS
ICOL
IBEN
Figure
Inter-IMPR Interface AUI/TP Port Timing
DESCRIPTION Inter-IMPR Interface Propagation Delay Inter-IMPR Interface Propagation Delay FIG. MIN. TYP. UNIT Bits Bits
Inter-IMPR Interface AUI/TP port Timing Diagram
IDAT
Valid Data
DI+/DT+
DTDDDD+
Figure
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
Output Driver Timing
DESCRIPTION delay FIG. MIN. TYP. MAX. UNIT
Output Driver Timing Diagram
Twister Pair Drivers
Figure
Repetition Timing (part
DESCRIPTION Minimum Start Idle (SOI) Pulse Width Start Idle Generated Twisted Pair Propagation Delay Inter-IMPR interface Propagation Delay FIG. MIN. TYP. MAX. UNIT Bits Bits
Repetition Timing Diagram (part
DI+/2 DTDDDD+ IDAT Valid Data
Figure
Preliminary W89C982AF
Repetition Timing (part
DESCRIPTION Minimum Twisted Pair (SOI) Pulse Width Propagation Delay Propagation Delay Inter-IMPR Interface Propagation Delay FIG. MIN. TYP. UNIT Bits Bits Bits
Repetition Timing Diagram (part
RD+/2
DTDDDD+
IDAT
Valid Data
Figure
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
Link Test Timing
DESCRIPTION link pulse width Duration between transmitted link pulses Duration between received link pulses FIG. MIN. TYP. MAX. UNIT
Link Test Timing Diagram
DTDDDD+ TX+/Transmitted Link Pulse
RX+/Received Link Pulse
Figure
DO+/- Switch Test Load
DO270
Preliminary W89C982AF
Digital Output Switching Test Load
Pre-equalization Network
DTX+ DDX+ DTX390 DDXRDX+ RDXRxTxRx+ 1.21 Kohm
Publication Release Date: November 1996 Revision
Preliminary W89C982AF
PACKAGE DIMENSIONS
100-pin
Symbol
Dimension inches
Dimension
0.004 0.107 0.010 0.004 0.546 0.782 0.020 0.728 0.964 0.039 0.087
0.130
0.10
3.30
Notes:
0.112 0.012 0.006 0.551 0.787 0.026 0.740 0.976 0.047 0.095
0.117 0.016 0.010 0.556 0.792 0.032 0.752 0.988 0.055 0.103 0.004
2.718 0.254 0.101 13.87 19.87 0.498 18.49 24.49 0.991 2.21
2.845 0.305 0.152 14.00 20.00 0.65 18.80 24.80 1.194 2.413
2.972 0.407 0.254 14.13 20.13 0.802 19.10 25.10 1.397 2.616 0.102
Dimension include interlead flash. Dimension does include dambar protrusion/intrusion. Controlling dimension: Millimeters General appearance spec. should based final visual inspection spec.
Seating Plane
Detail
Detail
Headquarters
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
803, World Trade Square, Tower Winbond Memory Lab. Creation III, Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 852-27513100 TEL: 886-3-5770066 2727 First Street, Jose, FAX: 852-27552064 FAX: 886-3-5792646 95134, U.S.A. http://www.winbond.com.tw/ TEL: 1-408-9436666 Voice Fax-on-demand: 886-2-7197006 FAX: 1-408-5441798
Taipei Office
11F, 115, Sec. Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: data specifications subject change without notice.
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