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64MB / 128MB / 256MB x64 144-PIN SDRAM SODIMMs

SMALL-OUTLINE SDRAM MODULE

64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
SMALL-OUTLINE SDRAM MODULE
Features
MT8LSDT864(L)H(I) - 64MB MT8LSDT1664(L)H(I) - 128MB MT8LSDT3264(L)H(I) - 256MB
For the latest data sheet, please refer to the Micron Web site: www.micron.com / moduleds
Figure 1: 144-Pin SODIMM (MO 190)
TABLE 1:
Address Table
64MB MODULE 128MB MODULE 256MB MODULE
OPTIONS
NOTE:
MARKING
None L
4K 4K 8K Refresh Count Device Banks 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) 4 Meg x16 8 Meg x 16 16 Meg x 16 Device Conf. 4K (A0-A11) 4K (A0-A11) 8K (A0-A12) Row Addr. Column Addr. 256 (A0-A7) 512 (A0-A8) 512 (A0-A8) 2 (S0, S1) 2 (S0, S1) 2 (S0, S1) ModuleBanks
TABLE 2:
None I
G -13E -133 -10E Standard MODULE MARKING -13E -133 -10E
Timing Parameters
PC100 CL - tRCD - tRP 2-2-2 2-2-2 2-2-2 PC133 CL - tRCD - tRP 2-2-2 3-3-3 NA
1. Low Power and Industrial Temperature options not available concurrently. Consult Micron for available option combinations. 2. Consult Micron for availability Industrial Temperature option available in -133 speed only.
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
TABLE 3: Part Numbers
NOTE:
1. The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revision codes. Example: MT8LSDT1664HG-133B1
TABLE 4:
Pin Assignment (144-Pin SODIMM Front)
37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 DQ14 DQ15 VSS DNU DNU CK0 VDD RAS# WE# S0# S1# 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 NC VSS DNU DNU VDD DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VDD A6 A8 Vss 109 A9 111 A10 113 VDD 115 DQMB2 117 DQMB3 119 Vss 121 DQ24 123 DQ25 125 DQ26 127 DQ27 129 VDD 131 DQ28 133 DQ29 135 DQ30 137 DQ31 139 VSS 141 SDA 143 VDD
TABLE 5:
Pin Assignment (144-Pin SODIMM Back)
38 DQ40 40 DQ41 42 DQ42 44 DQ43 46 VDD 48 DQ44 50 DQ45 52 DQ46 54 DQ47 56 VSS 58 DNU 60 DNU 62 CKE0 64 VDD 66 CAS# 68 CKE1 70 NC / A121 72 DNU 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 CK1 VSS DNU DNU VDD DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VDD A7 BA0 VSS 110 BA1 112 A11 114 VDD 116 DQMB6 118 DQMB7 120 VSS 122 DQ56 124 DQ57 126 DQ58 128 DQ59 130 VDD 132 DQ60 134 DQ61 136 DQ62 138 DQ63 140 VSS 142 SCL 144 VDD
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQMB4 DQMB5 VDD A3 A4 A5 VSS
VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 Vss DQMB0 DQMB1 VDD A0 A1 A2 VSS
1. Pin 70 is No Connect for 64MB and128MB modules, or A12 for 256MB module.
Figure 2: PIN Locations (144-PIN SODIMM) Front View Back View
(all odd pins)
PIN 143
PIN 144
(all even pins)
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
TABLE 6: PIN DESCRIPTIONS
SYMBOL RAS#, CAS#, WE# CK0, CK1 TYPE Input DESCRIPTION Pin numbers may not correlate with symbols. Refer to the Pin Assignment table for pin number and symbol information. PIN NUMBERS 65, 66, 67 61, 74
CKE0, CKE1
DQMB0-DQMB7
BA0, BA1
29, 30, 31, 32, 33, 34, 70 (256MB), 103, 104, 105, 109, 111, 112
A0-A11 (64MB, 128MB) A0-A12 (256MB)
SCL SDA
3-10, 13-20, 37- 44, 47-54, 83- 90, 93-100, 121-128, 131-138 11, 12, 27, 28, 45, 46, 63, 64, 81, 82, 101, 102, 113, 114, 129, 130, 143, 144 1, 2, 21, 22, 35, 36, 55, 56, 75, 76, 91, 92, 107, 108, 119, 120, 139, 140 70 (64MB, 128MB), 73 57, 58, 59, 60, 72, 77, 78, 79, 80
DQ0-DQ63
Supply
Ground.
NC DNU
Not Connected: These pins should be left unconnected. Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family.
Draft 9 / 20 / 2002
S0#, S1#
Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Input Clock: CK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. Deactivating the clock provides PRECHARGE, POWERDOWN, and SELF REFRESH operation (all device banks idle), ACTIVE POWER-DOWN (row ACTIVE in any device bank), or CLOCK SUSPEND operation (burst access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CK, are disabled during power-down and self refresh modes, providing low standby power. Input Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Input Input / Output Mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQMB is sampled HIGH during a READ cycle. Input Bank Address: BA0 and BA1 define to which device bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ / WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input / Serial Presence-Detect Data: SDA is a bidirectional pin used to Output transfer addresses and data into and out of the presencedetect portion of the module. Input / Data I / O: Data bus. Output
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
Figure 3: Functional Block Diagram
S0# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQML CS# DQ DQ DQ DQ DQ DQ U2 DQ DQ DQMH DQ DQ DQ DQ DQ DQ DQ DQ S0# DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 RAS# CAS# CKE0 CKE1 WE# A0-A11 (64MB / 128MB) A0-A12 (256MB) BA0-1 VDD VSS DQMH CS# DQ DQ DQ DQ DQ DQ DQ U3 DQ DQML DQ DQ DQ DQ DQ DQ DQ DQ DQML CS# DQ DQ DQ DQ DQ DQ DQ U7 DQ DQMH DQ DQ DQ DQ DQ DQ DQ DQ DQMH CS# DQ DQ DQ DQ DQ DQ U6 DQ DQ DQML DQ DQ DQ DQ DQ DQ DQ DQ S1# DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMH CS# DQ DQ DQ DQ DQ DQ DQ U5 DQ DQML DQ DQ DQ DQ DQ DQ DQ DQ DQML CS# DQ DQ DQ DQ DQ DQ DQ U9 DQ DQMH DQ DQ DQ DQ DQ DQ DQ DQ S1# DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMH CS# DQ DQ DQ DQ DQ DQ DQ U4 DQ DQML DQ DQ DQ DQ DQ DQ DQ DQ S0# DQML CS# DQ DQ DQ DQ DQ DQ U8 DQ DQ DQMH DQ DQ DQ DQ DQ DQ DQ DQ S1# S0# S1#
RAS#: SDRAMs CAS#: SDRAMs CKE: SDRAMs U2-U5 CKE: SDRAMs U6-U9 WE#: SDRAMs A0-A11: SDRAMs A0-A12: SDRAMs BA0-1: SDRAMs SDRAMs, SPD SDRAMs, SPD SCL WP SERIAL PD A0 U1 A1 SDA A2 CK0 CK1 S0# S1# U2-U5 U6-U9 U2-U5 U6-U9
Notes: All resistor values are 10W unless otherwise specified. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at: www.micron.com / numberguide.
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
General Description
access. For more information regarding SDRAM operation, refer to the 64Mb, 128Mb, or 256Mb SDRAM component data sheets.
Serial Presence-Detect Operation
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP Starting at some point . during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All device banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command.
Mode Register Definition
The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 4, Mode Register Definition Diagram, on page 6. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power.
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. For the 256MB module, Address A12 (M12) is undefined but should be driven LOW during loading of the mode register. The mode register must be loaded when all device banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 7, Burst Definition Table, on page 7.
Figure 4: Mode Register Definition Diagram
64MB Module and 128MB Module
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
Mode Register (Mx)
Reserved WB Op Mode
CAS Latency
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in Table 7, Burst Definition Table, on page 7. The block is uniquely selected by A1-A9 when the burst length is set to two by A2-A9 when the burst length is set to four and by A3-A9 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached, as shown in Table 7, Burst Definition Table, on page 7.
256MB Module
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
Mode Register (Mx)
Reserved
WB Op Mode
CAS Latency
Burst Length
Burst Type Sequential Interleaved
CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved this is referred to as the burst type and is selected via bit M3.
M6-M0 Defined -
Operating Mode Standard Operation All other states reserved
Write Burst Mode Programmed Burst Length Single Location Access
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
TABLE 7:
BURST LENGTH
Burst Definition Table
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and, provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 5, CAS Latency Diagram. The CAS Latency Table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used, because unknown operation or incompatibility with future versions may result.
STARTING COLUMN ADDRESS
Figure 5: CAS Latency Diagram
T0 CLK COMMAND T1 T2 T3
NOP tLZ
NOP tOH DOUT
NOTE:
T0 CLK COMMAND
NOP tLZ
NOP tOH DOUT
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
TABLE 8: CAS Latency Table
Test modes and reserved states should not be used, because unknown operation or incompatibility with future versions may result.
Write Burst Mode
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and / or test modes. The programmed burst length applies to both READ and WRITE bursts.
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
Commands
The Truth Table provides a quick reference of available commands. This is followed by written description of each command. For a more detailed description of commands and operations, refer to the 64Mb, 128Mb, or 256Mb SDRAM component data sheet.
TABLE 9:
Truth Table - SDRAM Commands and DQMB Operation
CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable / Output Enable Write Inhibit / Output High-Z
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
Absolute Maximum Ratings
Voltage on VDD, VDDQ Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . -1V to +4.6V Voltage on Inputs NC or I / O Pins Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +4.6V Operating Temperature TA (Commercial) . . . . . . . . . . . . . . . . . 0°C to +70°C TA (Industrial Temperature) . . . . . -40°C to +85°C Storage Temperature (plastic) . . . . . .-55°C to +150°C Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W Short Circuit Output Current . . . . . . . . . . . . . . . .50mA Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 10: DC Electrical Characteristics and Operating Conditions
II IOZ VOH VOL
TABLE 11: IDD Specifications and Conditions - 64MB Module
NOTE:
SYMBOL IDD1a IDD2b IDD3a
-13E 508 16 188
-10E 388 16 148
UNITS mA mA mA
NOTES 3, 18, 19, 30 30 3, 12, 19, 30
IDD4a IDD5b IDD6b IDD7 IDD7
Standard Low Power
a. Value calculated as one module bank in this operating condition, and all other module banks in power-down mode. b. Value calculated reflects all module banks in this operating condition.
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
TABLE 12: IDD Specifications and Conditions - 128MB Module
NOTE:
SYMBOL IDD1
-13E 648 16 208
-10E 568 16 168
UNITS mA mA mA
NOTES 3, 18, 19, 30 30 3, 12, 19, 30
IDD2b IDD3a
IDD4a IDD5b IDD6b IDD7b IDD7b
Standard Low Power
a. Value calculated as one module bank in this operating condition, and all other module banks in power-down mode. b. Value calculated reflects all module banks in this operating condition.
TABLE 13: IDD Specifications and Conditions - 256MB Module
NOTE:
SYMBOL IDD1
-13E 548 16 168
-10E 508 16 168
UNITS mA mA mA
NOTES 3, 18, 19, 30 30 3, 12, 19, 30
IDD2b IDD3a
IDD4a IDD5b IDD6b IDD7b IDD7b
Standard Low Power
a. Value calculated as one module bank in this operating condition, and all other module banks in power-down mode. b. Value calculated reflects all module banks in this operating condition.
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
TABLE 14: Capacitance
Notes 1, 2 notes appear following parameter tables Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters PARAMETER Input Capacitance: A0-A12, BA0, BA1, RAS, CAS, WE Input Capacitance: CKE0, CKE1, S0, S1 Input Capacitance: CK0, CK1 Input Capacitnace: DQMB0- DQMB7 Inuput / Output Capacitnance: DQ0-DQ63 SYMBOL CI1 CI2 CI3 CI4 CIO MIN 20 10 10 5 8 MAX 28 14 15.2 7 12 UNITS pF pF pF pF
TABLE 15: Electrical Characteristics and Recommended AC Operating Conditions
Notes: 5, 6, 8, 9, 11 notes appear following parameter tables Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters AC CHARACTERISTICS PARAMETER Access time from CLK (positive edge) Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period AUTO REFRESH period
-133 MIN MAX 5.4 6 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 1.5 0.8 1.5 5.4 5.4 5.4 6 1 3 1.8 1 3 1.8 120, 000 50 70 20 64 66 70 1 2 3 3 8 10 1 2 1 2 1 2
-10E MIN MAX 6 6 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 6 ns ns ns ns ns 120, 000 ns ns ns 64 ms ns 28 29 10 10 24 24 NOTES 27
MAX 5.4 5.4
AC(3) AC(2)
CK(3) CK(2) CKH CKS
CMH CMS
HZ(3) HZ(2)
OHN RAS
RCD REF RFC
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
TABLE 15: Electrical Characteristics and Recommended AC Operating Conditions
Notes: 5, 6, 8, 9, 11 notes appear following parameter tables Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters AC CHARACTERISTICS PARAMETER PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time
-13E SYMBOL
-133 MIN 20 15 1.2 0.3 1 CLK + 7.5ns 15 75 1.2 MAX
-10E MIN 20 20 0.3 1 CLK + 7ns 15 80 1.2 MAX UNITS ns ns ns ns ns ns 7 24 25 20 NOTES
MIN 15 14 0.3 1 CLK + 7ns 14 67
Exit SELF REFRESH to ACTIVE command
TABLE 16: AC Functional Characteristics
SYMBOL
UNITS
NOTES 17 14 14 17 17 17 17 15, 21 16, 21 17 17 16, 21 26 17 17
CCD PED
DQD DQZ DAL DPL BDL CDL RDL
DQM DWD
ROH(3) ROH(2)
Draft 9 / 20 / 2002
Notes: 5, 6, 7, 8, 9, 11, 32 notes appear following parameter tables
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
Notes
Q 50pF
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
SPD Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figure 6 and Figure 7).
SPD Acknowledge
Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (Figure 8). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode.
SPD Start Condition
All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
SPD Stop Condition
All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode.
Figure 6: Data Validity
Figure 7: Definition of Start and Stop
DATA STABLE DATA CHANGE DATA STABLE
START BIT
STOP BIT
Figure 8: Acknowledge Response From Receiver
SCL from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
TABLE 17: EEPROM Device Select code
The most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER b7 Memory Area Select Code (two arrays) Protection Register Select Code 1 b6 0 0 b5 1 1 b5 0 1 b4 0 0 b3 SA2 SA2 CHIP ENABLE b2 SA1 SA1 b1 SA0 SA0 RW b0 RW RW
TABLE 18: EEPROM Operating modes
TABLE 19: Serial Presence-Detect EEPROM DC Operating Conditions
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
Figure 9: SPD EEPROM Timing Diagram
tF t LOW t HIGH tR
t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO
SDA IN
SDA OUT
UNDEFINED
TABLE 20: Serial Presence-Detect EEPROM AC Operating Conditions
NOTE:
SYMBOL
MIN 0.3 4.7 300
MAX 3.5
UNITS µs µs ns
NOTES
HD:DAT HD:STA
SU:DAT SU:STA
SU:STO WRC
1. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase / program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
TABLE 21: Serial Presence-Detect Matrix
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
TABLE 21: Serial Presence-Detect Matrix
"1" / "0": Serial Data, "driven to HIGH" / "driven to LOW" notes appear at end of Serial Presence-Detect Matrix BYTE DESCRIPTION 31 32 33 34 35 36-61 62 63 ENTRY (VERSION) MT8LSDT864(L)H(I) MT8LSDT1664(L)H(I) MT8LSDT3264(L)H(I) 08 15 20 08 10 15 20 08 10 00 12 57 9D E5 2C FF 01 - 0B Variable Data 01-09 00 Variable Data Variable Data Variable Data - 64 CF 10 15 20 08 10 15 20 08 10 00 12 60 A6 EE 2C FF 01 - 0B Variable Data 01 - 09 00 Variable Data Variable Data Variable Data - 64 CF 20 15 20 08 10 15 20 08 10 00 12 73 B9 01 2C FF 01 - 0B Variable Data 01-09 00 Variable Data Variable Data Variable Data - 64 CF
NOTE:
1. The value of tRAS used for -13E modules is calculated from tRC - tRP. Actual device spec. value is 37ns.
Draft 9 / 20 / 2002
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
Figure 10: 144-PIN SODIMM
FRONT VIEW
2.666 (67.72) 2.656 (67.45) .150 (3.80) MAX
.079 (2.00) R (2X)
.071 (1.80) (2X)
1.255 (31.88) 1.245 (31.62) .787 (20.00) TYP
PIN 143
BACK VIEW
PIN 144
NOTE: All dimensions in inches (millimeters)
MAX or typical where noted. MIN
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.
Draft 9 / 20 / 2002
.059 (1.50) .024 (.60) TYP TYP
.0315 (.80) TYP
64MB / 128MB / 256MB (x64) 144-PIN SDRAM SODIMMs
Revision History
Rev. b, Pub. 8 / 02, ...............................................................................7 / 02 · Converted to FrameMaker, Added Industrial Temperature
Draft 9 / 20 / 2002