Preliminary BM29F040 MEGABIT (512K VOLT SECTOR ERASE CMOS FLASH M
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Preliminary BM29F040
MEGABIT (512K VOLT SECTOR ERASE CMOS FLASH MEMORY
GENERAL DESCRIPTION
BM29F040 Megabit, Volts only Flash memory device organized 512K bits each. BM29F040 offered Industry standard 32-pin package which backward compatible Megabit also compatible EEPROMs. device offered PDIP, PLCC TSOP packages. device designed programmed erased system with standard system Volt supply. external 12.0 Volts required program erase operation. device also reprogrammed standard EPROM programmers. BM29F040 offers access times between device separate chip enable write enable output enable controls eliminate contention. flash memory technology reliably stores memory information even after 100,000 erase program cycles. proprietary cell technology enhances programming speeds eliminates over erase problems seen classical ETOXtype Flash cell technologies. combination cell technology internal circuit design techniques give reduced internal electrical fields this provides improved reliability endurance. BM29F040 entirely command compatible JEDEC standard Megabit EEPROM. commands written Command State machine using standard microprocessor write timings. internal Programming Erase Algorithms automatically implemented based input commands. BM29F040 programmed executing program command sequence. This will start internal automatic program Algorithm that times program pulse width also verifies proper cell margin. Erase accomplished executing erase command sequence. internal Power Switching State Machine automatically executes algorithms generates necessary voltages timings erase operation. program erase verify also done internally proper margin testing automatically performed. This scheme unburdens microprocessor microcontroller from generating program erase algorithms controlling necessary timings voltages. entire memory typically erased seconds. preprogramming necessary this technology. BM29F040 also features sector erase architecture. divided into sectors bytes each. Each sector erased individually without affecting data other sectors they erased random combination groups. This multiple sector erase capability full chip erase makes very flexible alter data BM29F040. protect data from accidental program erase device also sector protect multiple sector protect function. device features single Volt power supply read, program erase operation. Internally generated well regulated voltages provided program erase operation. detector inhibits write operations during power transitions. program erase detected Data polling Toggle feature DQ6. Once program erase cycle been successfully completed, device internally resets Read mode.
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Publication Release Date: 1999 Revision
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FEATURES
Preliminary BM29F040
Program Erase Minimizes system power consumption Simplifies system design
Sector Erase architecture Equal sectors bytes each combination multiple Sector Erase Full Chip Erase
Compatible with JEDEC standard commands Uses same software commands EEPROMs
Sector Protection number sectors protected from Program Erase operation
Compatible with JEDEC-standard byte wide pinout PLCC/TSOP
Power Consumption Typically 100,000 Program/Erase cycles Erase Suspend Resume Suspend Sector Erase Operation allow READ another sector
Automated sector/chip Erase Algorithms programming before Erase needed Internal program Erase Margin Check
Write inhibit volts Single Cycle reset command
Data Polling Toggle useful detection Program Erase cycle completion
Product Selection Guide FAMILY PART Maximum Access Time (nS) Access time (nS) Access time (nS) -75*
Table
-120
-150
*This speed available with variation
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CONFIGURATIONS
View I/O0 I/O1 I/O2
Preliminary BM29F040
I/O7 I/O6 I/O5 I/O4 I/O3
PLCC View I/O0 I/O7
I/O's GND3
TSOP View
TYPE
I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00
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Flexible Sector-erase Architecture:
bytes sector Individual sector, multiple sector bulk erase capability. Individual multiple-sector protection user definable. Table Sector Definition
byte sector byte sector byte sector byte sector byte sector byte sector byte sector byte sector 70000H-7FFFFH 60000H-6FFFFH 50000H-5FFFFH 40000H-4FFFFH 30000H-3FFFFH 20000H-2FFFFH 10000H-1FFFFH 00000H-0FFFFH
Preliminary BM29F040
DESCRIPTION
SYMBOL DQ0-DQ7 TYPE NAME FUNCTION ADDRESS INPUTS: memory addresses. Addresses internally latched during write cycle. ADDRESS INPUT: When Volts mode accessed. During this mode decodes between manufacturer device IDs. DATA INPUTS OUTPUTS: Inputs array data fourth cycle during program command. Inputs commands Command register when active. Data internally latched during program cycles. Outputs from Array Intelligent Identifier information. output pins float tri-state when chip deselected outputs disabled. CHIP ENABLE: Activates device's control logic, input buffers, decoders sense amplifiers. active control; high deselects memory device reduces power consumption standby levels. OUTPUT ENABLE: active control signal. This gates device's outputs through data buffers during read cycle. When high outputs tri-state. WRITE ENABLE: Controls writes Command state Machine memory array. active signal. Addresses Data latched during rising edge pulse. DEVICE POWER SUPPLY: Main power source device. value GROUND: device ground internal circuitry.
Table
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BLOCK DIAGRAM
Preliminary BM29F040
Erase Voltage Generator
Input output Buffers
State Control Command Register Program Voltage Generator
Detect Timer
Chip Enable Output Enable Logic
Data latch
Y-Decode
Y-MUX SENSING
X-decode ARRAY
Figure
OPERATION
Operation Auto select Manufacturers Auto select Device Read Standby Output Disable Write Enable Sector Protect Verify Sector Protect
Code Code Dout High High Code
Table Notes: LEGENDS: VIL, VIH, don't care, +12V. Manufacturer device codes also accessed command register write sequence. Refer table Command definitions. Refer Table valid during write operation. Refer section sector protection.
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Publication Release Date: 1999 Revision
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Autoselect Codes
TYPE Manufacturer Code BM29F040 Device code Sector Protection
Preliminary BM29F040
Code (Hex) Sector Addresses
Table
PRODUCT FAMILY PRINCIPLES OPERATION
Flash memory devices electrically alterable non-volatile memory products. BM29F040 augments this feature requiring additional power supply. Megabit flash family uses Command register internally generated voltages timing algorithms make program erase operations simple. user need worry about generating tightly controlled high voltages board tying microcontroller generate program erase algorithms. Command register allows 100% TTL-level control inputs, maximum compatibility with Flash memory functions. device provides standard EPROM read, standby output disable operations. Manufacturer Identification Device Identification data accessed through Command register through standard EPROM high voltage access (VID) PROM programming equipment. Command register Power Switching State Machine built inside device. Their purpose completely automate program erase operation. command register receives commands given user internally controls power switching state machine.
Read Mode
BM29F040 three control pins they should logically active obtain valid data outputs. Chip-Enable device selection control. Output Enable data input/output control. This when high (VIH) brings output drivers tristate allows data into device. Data input then controlled When (VIL) enables output buffers valid array data becomes available output pins. Write Enable high during READ mode.
Standby Mode
BM29F040 standby modes: CMOS standby mode input +0.5V) when current consumed less than standby mode held VIH) when current consumed approximately standby mode outputs high impedance state independent input. device deselected during erasure programming, device will draw active current until erase programming operation complete.
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Autoselect Mode
Preliminary BM29F040
Autoselect mode allows access manufacturers device code. This mode enabled either taking address (11.5 12.5 volts) giving Autoselect Command sequence shown Table Once Autoselect mode enabled identifier bytes read device outputs toggling from VIH. Byte VIL) represents manufacturers code (ADH BMI). Byte VIH) represents device identifier this BM29F040. READ command must written Command register return Read mode after Autoselect mode.
Write Operations
on-chip state machines control Chip Erase, Sector Erase byte Write operations. This frees system processor other tasks. Programming Erase voltages generated internally. Write Erase timings algorithms also built into device. byte write/ sector erase Chip Erase Command Interface provides additional data protection avoid accidental Write Erase. Commands written Command register using standard microprocessor write timings. Command register recognizes Read mode, Autoselect mode, Chip Erase, Sector Erase (64K bytes sector) Program commands. Command register does occupy addressable memory location. interface register latch used store command address data information needed execute command.
Command Definitions
Device operations selected writing specific address data sequences into Command register. Table defines these Command sequences.
Read/ Reset Command
read reset operation initiated writing read/reset command sequence command register. Processor read cycles retrieve data from memory. device remains enabled reads until command register contents changed. device will automatically power-up read/reset mode. this case, command sequence needed read memory data. This default power read mode ensures that spurious changes data take place during power-up. shown this data sheet, timing parameters A.C. read waveforms should referenced. single cycle reset also available shown table.
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Publication Release Date: 1999 Revision
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Table Command Definitions Write cycles
required
Preliminary BM29F040
Command Sequence
First Write cycle
Address XXXXH 5555H 5555H Data
Second Write cycle
Address Data
Third Fourth Fifth Write cycle Write cycle Write cycle
Address Data
Sixth Write cycle
Data
Address Data Address Data Addres
Read /Reset Read /Reset Auto Select Auto Select Sector Protect Verify Byte Program Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume
Notes:
2AAAH 2AAAH
5555H 5555H
5555H
2AAAH
5555H
5555H
2AAAH
5555H
5555H 5555H XXXXH
2AAAH 2AAAH
5555H 5555H
5555H 5555H
2AAAH 2AAAH
5555H
XXXXH
Address A15, A16, dont care address commands except Program address (PA) sector address (SA). operations defined Table Address memory location read. Address memory location programmed. Addresses latched falling edge Address sector erased. combination A16, will uniquely select sector. Data from selected address location (RA) during read operation. Data programmed selected memory location (PA). Data latched falling edge /WE. Auto select command used evaluate whether block protected using fourth address 02H. This similar placing High Voltage.
Auto Select Command
BM29F040 contains different procedures autoselect mode. traditional PROM programmer methodology taking Address VID) other writing Auto Select command sequence into command register. Following third cycle write command, read cycle from Address retrieves manufacturer code ADH, read cycle retrieves device code 40H. Scanning sector addresses (A16, A17, A18) while (A6, will produce logical device output protected sector. table more details.
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Preliminary BM29F040
terminate this operation, necessary write read/ reset command command register.
Byte Write Byte program
BM29F040 programmed byte time. Programming four cycle operation. There unlock write cycles which followed program set-up command data write cycles. Addresses latched falling edge data latched rising edge rising edge begins programming. During execution embedded program algorithm host system required provide other controls timings. device also provides adequate program margin necessary voltages timings. When completed, automatic programming will provide equivalent written data DQ7. After successful programming operation device returns back read mode. Data polling must performed memory location which being programmed. Figure illustrates Embedded Programming Algorithm waverforms shown figures
Chip Erase
Chip erase cycle operation. There "unlock" write cycles. These followed writing setup command. more unlock write cycles then followed chip erase command. Chip erase does require user program device prior erase. BM29F040's technology immune overerase does need internal programming algorithm before erase. This save erase time many applications. automatic Chip erase begins rising edge last pulse command sequence terminates when data "1", which time device returns back read mode. Figure illustrates Auto Erase Algorithm Erase Waveforms shown Figure
Sector Erase
Sector erase cycle operation. There "unlock" write cycles followed writing sector erase setup command. more "unlock" write cycles then followed sector erase confirm command. sector address latched failing edge command data latched rising edge time-out from rising edge last sector erase command initiated. actual sector erase starts after last rising edge Multiple sectors erased simultaneously. After writing cycle command sector erase additional sector address sector erase command inserted within time-out period. timer reset every time additional sector erase command inserted. sectors added erased random sequence. command other than sector erase command Erase Suspend command during time-out period will reset device read mode ignoring previous command string. During execution Sector Erase command, only Erase Suspend Erase Resume commands allowed. other commands will reset device Read mode. Once device resets Read mode command error during Sector Erase, data this sector lost integrity. sector should properly erased again.
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Preliminary BM29F040
Sector erase does require user program sector before erase. When erasing sector multiple sectors data unselected sectors remains unchanged. After sector erase operation completed data becomes device returns read mode. Data polling must performed address within sectors being erased. Figure shows Embedded Erase Algorithm Figure shows Sector Erase Waveforms.
Erase Suspend Resume
Erase suspend command allows user interrupt sector erase function then read data from other sectors which were being erased. This command applicable during Chip erase operation during program mode. Erase suspend command (B0H) will terminate Sector erase operation require form suspend erase operation into read mode (pseudo read mode). user must toggle determine chip entered erase suspended read mode, which time toggle will stop toggling. address sector being erased must used read toggle bit. user must keep information whether device pseudo read mode read mode. Every time Erase suspend command followed Erase resume command written internal counters reset. erase suspend command allowed during time window before actual sector erase operation starts. Erase resume command will start erase operation immediately there time window during erase resume. Note that other command during time will reset device read mode. resume Sector erase operation after pseudo read mode Resume command (30H) should written. sector erase will start immediately. Another Erase suspend command written after chip resumed erase operation. Note that data programmed back "1." Attempting give erroneous results hang device. Only erase operation change data from "1". system also write Autoselect Command during Erase Suspend mode. This allows host system correctly read autoselect codes during Erase Suspend since this data stored memory array.
Sector Protection
BM29F040 hardware sector protection. This feature will disable both Program Erase operation protected sector group sectors. device shipped with sectors unprotected. verify sector protected, programming equipment must force address VIH. Reading device particular sector address (A16, A18) XXX2H will produce data outputs protected sector. Figure Waveforms Figure algorithm. Please appropriate approved Programmer contact Bright BM29F040 Programmers Guide specification protecting individual sectors.
Sector Unprotection
BM29F040 also features sector unprotect mode, that protected sector unprotected. sectors unprotected same time. Please appropriate approved Programmer contact Bright BM29F040 Programmers Guide specification unprotect sectors.
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Preliminary BM29F040
also possible determine sector unprotected system writing autoselect command VIH. Performing read operation XXX2H sector address (defined A16, A18) will produce Data outputs unprotected sector. Table Sector Address Table
Sector Address Range 00000H 0FFFFH 10000H 1FFFFH 20000H 2FFFFH 30000H 3FFFFH 40000H 4FFFFH 50000H 5FFFFH 60000H 6FFFFH 70000H 7FFFFH
Data Flags Data polling
BM29F040 features Data polling indicate host system that Embedded Algorithms progress completed. During Embedded Program Algorithm, attempt read device will produce complement Data last written DQ7. Upon completion Embedded Programming Algorithm attempt read device will produce true data last written DQ7. Data polling valid after rising edge fourth pulse four write pulse sequence. During Embedded Erase Algorithm, will until Erase operation completed. Upon completion Erase data "1". sector erase, Data polling valid after last rising edge sector erase pulse. Chip erase, Data polling valid after last rising edge sixth Chip erase pulse. Data polling must performed sector address within sectors being erased protected sector. Once Embedded operation close being completed, BM29F040 data pins (DQ7) change asynchronously while asserted low. This means that device driving status information time bytes valid data other times. Depending when system samples output read status read valid data. Figure Data polling timing diagram.
Toggle
BM29F040 also features "Toggle Bit" method indicate host system that Embedded Algorithms progress completed. During Embedded Program Erase Algorithm cycle, successive attempts read data from device will result toggling between "0". Once Embedded Program Erase algorithm cycle completed, will stop toggling valid data will read successive attempts. During programming toggle valid after rising edge fourth pulse Winbond Company Publication Release Date: 1999 Revision
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Preliminary BM29F040
four write pulse sequence. During Chip Sector Erase, toggle valid after rising edge sixth pulse write pulse sequence. programming, sector being written protected, toggle toggle about then will stop toggling without data being changed. During erase device will erase sectors except sector being protected. sectors protected chip will toggle toggle about then drop back read mode without changing data. Either toggling will cause toggle. toggle valid time period during sector erase. Figure Toggle timing diagrams.
Exceeded Timing Limits
indicates program erase time exceeded specified timing limits. Under these conditions will produce "1". This failure condition which indicates that program erase cycle successfully completed. Data polling only operating function device under this condition. circuit will partially power down device under these conditions. pins will control output disable function shown Table this failure condition occurs during sector erase operation, indicates that particular sector reused. other sectors still functioning properly used. device must reset other good sectors. reset device, write Reset command sequence device. This will allow system other active sectors device. this failure condition occurs during chip erase, indicates that entire chip many sectors bad. this condition occurs during byte write indicates that sector containing this byte bad. This failure condition also occur user tries program non-blank location without erasing. this case device locks never completes operation. Please note that this device failure.
Sector Erase Timer
After completion Sector erase command sequence sector erase time-out begins. will remain until time-out complete. Data polling Toggle valid after initial sector erase command sequence. Data polling Toggle indicates device been written with valid erase command, used determine sector erase timer window still open. internally controlled erase cycle begun. device will accept additional sector erase commands. ensure that command been accepted, user should check status prior following each sector erase command. second status check, command accepted. Once internal erase cycle begins device will accept other command until internal erase cycle completed. BM29F040 designed offer protection against accidental programming erasure. During power-up device automatically resets read mode. multi-bus command sequences also provide data protection accidental write. device also provides additional features prevent inadvertent write operations during power-up power-down transitions system noise.
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Toggle
Preliminary BM29F040
BM29F040 also features "Toggle method indicate host system whether specific sector actively erasing whether sector erase-suspended. Toggle valid after rising edge final pulse command sequence. toggles when host system reads addresses within sector that have been selected erase. system control read cycles. But, distinguish between sector erasing erase-suspended. However, Toggle used determine sector actively erasing erase-suspended. result, both Toggle Bits required host system determine current mode information. Refer Table further comparison DQ2. Whenever host system begins read erase status using toggle bits, they must read least twice row. Typically, system would store first value compare second. bits still toggling, system should also check DQ5(see description). high, system should re-check toggle bits since toggling have just finished. toggle bits have stopped toggling, device successfully completed erase. toggle bits still toggling, device successfully completed erase operation host should issue Reset Command device before continuing. low, host system should continue monitor toggle bits issue erase suspend command performing single multiple sector erase command.
Write Operation Status
Standard Status Auto-Programming Auto-Erase Reading Erase Suspended Sector Reading Non-Erase Suspended Sector Auto-Programming Erase Suspend Auto-Programming Auto-Erasing Data Data Toggle Toggle Toggle Data Data Data Reserved Future Toggle Toggle Toggle Toggle Toggle Toggle
Erase Suspend
Exceeded Time Limits
Table Hardware Sequence Flags
Write Inhibit
During power-up power-down, write cycle inhibited values less than Volts (3.8 Volts typical). Vlko (Vlko lock Voltage) command register disabled internal program/erase circuits disabled. Under this condition device will reset read mode. write command given during Vlko, writes will ignored. users responsibility ensure that control pins logically correct prevent unintentional writes when Vlko.
Write Pulse Glitch Protection
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Preliminary BM29F040
Noise pulses less than will initiate write cycle.
Power-up Wtire Inhibit
Power-up device with will accept commands rising edge internal state machine automatically reset read mode power-up.
Logical Inhibit
Writing inhibited holding control pins VIL, VIH. initiate write cycle, must logical must logical "1".
Sector Protect
Sectors BM29F040 hardware protected user. protection circuitry will disable both program erase functions protected sectors. program erase commands will ignored given protected sectors. Chip erase command will also erase protected sectors.
Parallel Device Erasure
BM29F040 fully self timed device. This makes feasible Erase Program many devices parallel.
Program Command Sequence (Address/Data)
First Write cycle 5555H/
Embedded Programming Flow Chart
Start Write Program Command Sequence (see Fig.
Second Write cycle
2AAAH/
Data poll Device
Third Write cycle 5555H/
Verify Byte
Fourth Write cycle Program Add./Program Data
Byte Write Completed
Figure:
Figure:
Note: Data Polling Algorithm Figure
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Preliminary BM29F040
Embedded Erase Algorithm
Start Write Program Command Sequence (see below) Data poll Device
Data Erasure Completed
Figure Embedded Programming Algorithm Note: Data Polling Algorithm Figure
Chip Erase Command Sequence (Address/Data)
First Write cycle Second Write cycle Third Write cycle Fourth Write cycle Fifth Write cycle Sixth Write cycle 5555H/ 2AAAH/ 5555H/ 5555H/ 2AAAH/ 5555H/
Individual Sector/Multiple Sector Erase Command Sequence (Address/Data)
First Write cycle Second Write cycle Third Write cycle Fourth Write cycle Fifth Write cycle Sixth Write cycle Additional Sector erase commands optional 5555H/ 2AAAH/ 5555H/ 5555H/ 2AAAH/ Sector Address/ Sector Address/ Sector Address/
Figure Automated Erase Flow Chart Sequence
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Data Polling Algorithm
Start
Preliminary BM29F040
Toggle Algorithm
Start
Data
Toggle
Data
Note
Toggle
Pass
Note
Fail
Pass Fail
Note: rechecked even because stop toggling same time changed "1".
Note: rechecked even because change simultaneously with DQ5.
Figure Data Polling Toggle Algorithm
Absolute Maximum Ratings:
Storage Temperature -65°C +125°C Operating Temperature (Note During Read -55°C +125°C During Program/Erase -55°C +125°C Temperature under Bias (With Power Applied) Voltages with Respect GND. pins except (Note (Note (Note Output short circuit current (Note -55°C +125°C +14V 200mA
Operating Ranges:
Commercial Devices Temperature Range +70°C
supply voltage during 4.5V 5.5V operations 4.75V 5.25V Industrial Devices Temperature Range supply voltage during operations -40°C +85°C 4.5V 5.5V
Notes datasheet defines operation specific temperature ranges. Minimum voltage input output pins -0.5V. During voltage transitions, inputs undershoot Volts periods maximum voltage these pins +0.5V. During transitions, inputs overshoot +2.0V periods Maximum voltage overshoot 14.0V periods Outputs shorted more than second. Only one/output shorted time. *Notice: Stresses above those listed under "Absolute Maximum Ratingsz" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods time affect device reliability.
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Maximum Overshoot
Maximum Negative Overshoot
Preliminary BM29F040
+0.8 -0.5 -2.0 Maximum Negative Overshoot Waveform
Maximum positive Overshoot Waveform
Figure Maximum Overshoot Waveforms
Characteristics
Symbo
Parameter
Input Level Input High Level Output Voltage Output High Voltage Output High Voltage Input Load Current Output Leakage Current Output Short Circuit Current Standby Current (CMOS) Standby Current (TTL) Active Current Read Active Current Program Intelligent Identifier Volatge Intelligent Identifier Current
-0.5
0.45
Unit
Test Conditions
12mA Min. -2.5mA Min. lohl -100uA Min. Max. Vout Max. Vout 0.5V Max. 0.5V Max. Max. Vil, 6MHz, Vil,
lsb1 lsb2 lcc1 lcc2
11.5 12.5 Table
Notes: Currents unless otherwise noted. Typical values +5.0V, These parameters sampled 100% tested. Automatic power saving reduces Iccr CMOS inputs +0.5V. inputs either VIH.
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Capacitance:
Symbol Cout Parameter Input Capacitance Output Capacitance Conditiontion Vout
Preliminary BM29F040
Typical
Unit
Testing Input/Output Waveform
Testing Load Circuit
Input 0.45
2.7K Test Points Output Device Under Test includes Capacitance diodes 1N3064 wequivalent. 6.2K
test inputs driven 2.4V VTTL) logic 0.4V VTTL) logic "0". Input timing measurement begins 2.0V VTTL) input 0.8V VTTL) input "0". Output timing measurement ends 2.0V output 0.8V output "0". Input Rise fall times (10% 90%) 10ns.
Figure A.C.Testing Load Waveforms
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Characteristics Read Only Operations
SYMBOL
JEDEC tAVAV tAVQV tELQV tGLQV tELQX tEHQZ tGLQX tGHQZ tAXQX Standard tACC tOLZ Read Cycle Time Address Output Delay
Output Delay Output Delay Output high Output HIGH Output high Output HIGH
Preliminary BM29F040
DESCRIPTION
-120
-150
UNITS
Output Hold from Address, whichever first
Table Notes: A.C. Input/Output Reference Waveforms timing measurements. delayed tCE-tOE after falling edge without impact tCE. Sampled, 100% tested. A.C. Input/Output Reference Waveforms A.C. Testing Load Circuits testing characteristics.
Powerup
Standby
Device Address Select.
Outputs Enabled
Data Valid
Standby
Powerdown
AVAV
Addresses Address Valid
EHQZ
GLQV
DATA (D/Q) High
GHQZ
ELQV AVQV tGLQX
Valid Output
AXQX
High
ELQX
Figure A.C.Waveforms Read Operations
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Preliminary BM29F040
CHARACTERISTICS Controlled Write Operation
SYMBOL
JEDEC tAVAV tELWL tAVWL tDVWH tWLWH tWHEH tWLAX tWLWH tWHWL Standard tWPH tOES tOEH Write Cycle Time
DESCRIPTION
(2,4) (3,4)
-120
-150
UNITS
Setup
Address Setup Time Data Setup Time Data Hold Time
Hold Time
Address Hold Time Write Pulase Width
Pulse Width High Read Toggle Data Polling
Output Enable Setup Time Output Enable Hold Time
tGHWL tWHWH1 tWHWH2
tGHWL tWHWH1 tWHWH2 tVCS tVLHT tWPP1 tWPP2 tCESP tOESP
Read Recover Time Before Write Programming Operation Erase Operation (min.) Setup Time Voltage Transition Time Write Pulse Width Write Pulse Width
Setup
Time
Active
Table
Notes: Erase operation does need programming time. These timings Sector Protect/Unprotect operation. This timing only sector Unprotect. 100% tested.
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Switching Waveforms
Preliminary BM29F040
Data Polling 5555H
Addresses
GHWL
WHWH1
DATA (D/Q) HIGH
DOUT
Figure A.C.Waveforms Program Operations Controlled Writes) Notes: address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence.
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Preliminary BM29F040
CHARACTERISTICS Controlled Write Operation
SYMBOL
JEDEC tAVAV tWLEL tAVEL tDVEH tEHDX tEHWH tWLAX tELEH tEHEL Standard tCPH tOES tOEH Write Cycle Time (Note tVCS Setup time (Note
Table Notes: Erase operation does need programming time. These timings Sector Protect/Unprotect operation. This timing only sector Unprotect. 100% tested.
DESCRIPTION
-120
-150
UNITS
Setup time
Address Setup time Data Setup time Data Hold time
Hold time
Address Hold time
Pulse Width Pulse Width High
Output Enable Setup time Output Enable Hold time Read (Note Toggle Data Polling
tGHEL tWHWH1 tWHWH2
tGHEL tWHWH1 tWHWH2
Read Recover time before Write Programming Operation Erase Operation
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Switching Waveforms
Preliminary BM29F040
Data Polling
Addresses
5555H
GHEL
WHWH1
DOUT
DATA (D/Q)
HIGH
Figure 10.A.C.Waveforms Program Operations Controlled Writes) Notes: address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence.
Switching Waveforms
Addresses
5555H
2AAAH
5555H
5555H
2AAAH
GHWL
DATA (D/Q)
HIGH
sector erase chip erase
Figure A.C. Waveforms Chip/Sector Erase Operations Note: sector address Sector erase 5555H Chip Erase.
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Switching Waveforms
Preliminary BM29F040
DATA (D/Q)
Data
Data
Data
High
WHWH1
Figure Waveforms Data Polling during Embedded Algorithm operations
Data
Figure Waveforms Toggle during Embedded Algorithm operations Operating
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ORDERING INFORMATION
PART
Preliminary BM29F040
ACCESS POWER PACKAGE CYCLING TIME SUPPLY CURRENT (Min) (nS) MAX. (mA) PDIP PDIP PLCC PLCC TSOP TSOP PDIP PDIP PLCC PLCC TSOP TSOP 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000
TEMPERATURE RANGE 70°C 70°C 70°C 70°C 70°C 70°C -40°C 85°C -40°C 85°C -40°C 85°C -40°C 85°C -40°C 85°C -40°C 85°C
29F040-90NC 29F040-12NC 29F040-90AC 29F040-12AC 29F040-90TC 29F040-12TC 29F040-90NI 29F040-12NI 29F040-90AI 29F040-12AI 29F040-90TI 29F040-12TI
Notes:
Winbond reserves right make changes products without prior notice. Purchasers responsible performing appropriate quality assurance testing products intended applications where personal injury might occur consequence product failure. Typical cycling 100,000 program erase cycles.
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APPENDIX
Compatibility AMD's AMD29F040B
Preliminary BM29F040
device fully functional compatible AMD29F040B except during command addresses subset mode. device, Commands require unique address pattern bits A15, A14, A13, (eg.X555H X2AAH instead 5555H 2AAAH). That BM29F040 requires specifically A14,A13,A12 forced during command sequence addition through Note specifically that BM29F040 does require address along with A18, forced during command sequence. AMD's reduced address requirement makes their device slightly easier inadvertently create Command cause some program error malfunction. advantage reducing address simplify hardware interface systems where control signals limited number. 29F040B reduces interface requirement signals from address control pins. However full Command address supplied (i.e. 2AAAH 5555H) host system, there will incompatibility using either device.
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PACKAGE DIMENSIONS
32-pin P-DIP
Preliminary BM29F040
Dimension inches
Dimension
Symbol
Min. Nom. Max. Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 1.650 0.590 0.545 0.090 0.120 0.630 0.650 0.600 0.550 0.100 0.130 0.160 0.022 0.054 0.014 1.660 0.610 0.555 0.110 0.140 0.670 0.085 14.99 13.84 2.29 3.05 16.00 16.51 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 41.91 15.24 13.97 2.54 3.30 4.06 0.56 1.37 0.36 42.16 15.49 14.10 2.79 3.56 17.02 2.16 5.33
Notes:
Base Plane Seating Plane
1.Dimensions Max. include mold flash burrs. 2.Dimension does include interlead flash. 3.Dimensions include mold mismatch determined mold parting line. 4.Dimension does include dambar protrusion/intrusion. 5.Controlling dimension: Inches 6.General appearance spec. should based final visual inspection spec.
32-pin PLCC
Symbol
Dimension Inches
Dimension
Min. Nom.
0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.51 0.410 0.590 0.49 0.090
Max.
0.140
Min. Nom.
0.50
Max.
3.56
Notes:
0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004
2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91
2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.9 10.41 14.99 12.45 2.29
2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10
Dimensions include interlead flash. Dimension does include dambar protrusion/intrusion. Controlling dimension: Inches General appearance spec. should based final visual inspection sepc.
Seating Plane
Winbond Company
Publication Release Date: 1999 Revision
BRIGHT
Package Dimensions, continued
Preliminary BM29F040
32-pin TSOP
Symbol
Dimension Inches Min. Nom. Max. 0.047
Dimension Min. Nom. Max. 1.20 0.15 1.05 0.23 0.17 18.50 8.10 20.20
0.002 0.037 0.007 0.005 0.720 0.311 0.780
0.039 0.008 0.006 0.724 0.315 0.787 0.020 0.020 0.031 0.006 0.041 0.009 0.007 0.728 0.319 0.795
0.05 0.95 0.17 0.12 18.30 7.90 19.80
1.00 0.20 0.15 18.40 8.00 20.00 0.50 0.50 0.80
0.10(0.004)
0.016
0.024
0.40
0.60
0.000
0.004
0.00
0.10
Note:
Controlling dimension: Millimeters
BRIGHT
VERSION HISTORY
VERSION DATE May. 1999 PAGE Initial Issued
Preliminary BM29F040
DESCRIPTION
Headquarters
Winbond Electronics (H.K.) Ltd.
Winbond Electronics Corporation America
2727 First Street, Jose, 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
803, World Trade Square, Tower Creation III, Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice Fax-on-demand: 886-2-27197006
Taipei Office
11F, 115, Sec. Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: data specifications subject change without notice.
Winbond Company
Publication Release Date: 1999 Revision
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