Semiconductor MD56V62320 This version: Apr. 1999 MD56V62320

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Semiconductor MD56V62320 This version: Apr. 1999 MD56V62320

Datasheet Thumbnail

Top Searches for this datasheet

E2G1057-29-41
Semiconductor MD56V62320
This version: Apr. 1999 MD56V62320
4-Bank 524,288-Word 32-Bit SYNCHRONOUS DYNAMIC
DESCRIPTION
MD56V62320 4-bank 524,288-word 32-bit synchronous dynamic RAM, fabricated Oki's CMOS silicon-gate process technology. device operates inputs outputs LVTTL compatible.
FEATURES
Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell 4-bank 524,288-word 32-bit configuration power supply, ±0.3 tolerance Input LVTTL compatible Output LVTTL compatible Refresh 4096 cycles/64 Programmable data transfer mode latency Burst length Data scramble (sequential, interleave) auto-refresh, Self-refresh capability Package: 86-pin plastic TSOP (Type (TSOPII86-P-400-0.50-K) (Product MD56V62320-xxTA) indicates speed rank.
PRODUCT FAMILY
Family MD56V62320-10 Max. Frequency Access Time (Max.) tAC2 tAC3
1/29
Semiconductor CONFIGURATION (TOP VIEW)
VCCQ VSSQ VCCQ VSSQ DQM0 DQM2 DQ17 VSSQ DQ18 DQ19 VCCQ DQ20 DQ21 VSSQ DQ22 DQ23 VCCQ DQ24
MD56V62320
DQ16 VSSQ DQ15 DQ14 VCCQ DQ13 DQ12 VSSQ DQ11 DQ10 VCCQ DQM1 DQM3 DQ32 VCCQ DQ31 DQ30 VSSQ DQ29 DQ28 VCCQ DQ27 DQ26 VSSQ DQ25
86-Pin Plastic TSOP (II) Type)
Name BA0,
Function System Clock Chip Select Clock Enable Address Bank Select Address Address Strobe Column Address Strobe Write Enable
Name DQM0 VCCQ VSSQ
Function Data Input/Output Mask Data Input/Output Power Supply (3.3 Ground Data Output Power Supply (3.3 Data Output Ground Connection
Note:
same power supply voltage must provided every VCCQ pin. same voltage level must provided every VSSQ pin. 2/29
MD56V62320
DESCRIPTION
Fetches inputs edge. Disables enables device operation asserting deactivating inputs except CLK, CKE, DQM0 Masks system clock deactivate subsequent operation. deactivated, system clock will masked that subsequent operation deactivated. should asserted least cycle prior command. Address column multiplexed. address: RA10 Column address: BA0, DQM0 DQM0 controls DQM1 controls DQM2 controls DQ17 DQM3 controls DQ25 Data inputs/outputs multiplexed same pin. Functionality depends combination. details, function truth table. Bank Access pins. These pins dedicated select banks.
3/29
Semiconductor BLOCK DIAGRAM
MD56V62320
CLOCK BUFFER Command Decoding Logic Command Buffers Control Logic
BA0,
Address Buffers
Mode Register
Latency Burst controller
Column Address Latches Counter
Column Decoders Sense Amplifiers
DQM0 DQM3
Address Latches Refresh Counter Decoders Word Drivers
Memory Cells
BANK BANK BANK BANK Input Buffers Input Data Register
DQ32 Output Data Register
Output Buffers
4/29
MD56V62320
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage Relative Supply Voltage Storage Temperature Power Dissipation Short Circuit Current Operating Temperature Symbol VIN, VOUT VCC, VCCQ Tstg Topr Rating -0.5 -0.5 (Voltages referenced VSS) Unit
25°C Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Voltage Symbol VCC, VCCQ Min. -0.3 Typ. (Voltages referenced Max. Unit
Capacitance
(VCC ±0.3 25°C, MHz) Parameter Input Capacitance (ADDR) Input Capacitance (CLK, CKE, RAS, CAS, DQM0 Input/Output Capacitance (DQ1 DQ32) Symbol CIN1 CIN2 COUT Min. Max. Unit
5/29
Semiconductor Characteristics
Condition Parameter Symbol Others Burst ICC7 Min. Version
MD56V62320
Unit Note Max.
Output High Voltage Output Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Stand ICC1
ICC2
Average Power ICC3S Supply Current (Clock Suspension) Average Power Supply Current (Active Stand Power Supply Current (Burst) Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power down) ICC3
ICC4 ICC5
ICC6
Notes:
Measured with outputs open. address data changed once left unchanged during cycle. address data changed once left unchanged during cycles.
6/29
MD56V62320
Mode Address Keys
Latency Reserved Reserved Reserved Reserved Reserved Reserved Burst Type Sequential Interleave Burst Length Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Note:
A10, should stay during mode cycle.
POWER SEQUENCE With inputs state, turn power supply start system clock. After voltage reached specified level, pause more with input kept state. Issue precharge bank command. Apply auto-refresh eight more times. Enter mode register setting command.
7/29
Semiconductor Characteristics
Parameter Clock Cycles Time Access Time from Clock Clock Pulse Time Clock Pulse Time Input Setup Time Input Hold Time Output Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock Cycle Time Precharge Time Active Time Delay Time Write Recovery Time Write Command Input Time from Output Bank Active Delay Time Refresh Time Power-down Exit Set-up Time Input Level Transition Time Delay Time (Min.) Clock Disable Time from Data Output High Impedance Time from Data Input Mask Time from Data Input Time from Write Command Data Output High Impedance Time from Precharge Command Active Command Input Time from Mode Register Command Input (Min.) Symbol tOLZ tOHZ tRAS tRCD lOWD tRRD tREF tPDE lCCD lCKE lDOZ lDOD lDWD lROH lMRD MD56V62320-10 Min. Max.
MD56V62320
Note Unit Note Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle
8/29
Semiconductor Notes measurements assume that reference level timing input signals Output load.
Output
MD56V62320
access time defined longer than then reference level timing input signals VIL.
9/29
Semiconductor TIMING WAVEFORM MD56V62320 Read Write Cycle (Same Bank) Latency Burst Length
tRCD
ADDR
tOHZ
DQM0
Active
Read Command
Active
Write Command
Precharge Command
Precharge Command
10/29
MD56V62320
Single Read-Write-Read Cycle (Same Page) Latency Burst Length
High lCCD ADDR
tOLZ
tOHZ lOWD
DQM0
Active
Write Command
Precharge Command
Read Command
Read Command
11/29
Semiconductor *Notes:
MD56V62320
When "High" clock transition from "Low" "High", inputs except CKE, DQM0 invalid. When issuing active, read write command, bank selected BA1. Active, read write Bank Bank Bank Bank
auto precharge function enabled disabled input when read write command issued. Operation After burst, bank holds idle status. After burst, bank precharged automatically. After burst, bank holds idle status. After burst, bank precharged automatically. After burst, bank holds idle status. After burst, bank precharged automatically. After burst, bank holds idle status. After burst, bank precharged automatically.
When issuing precharge command, bank precharged selected A10, inputs.
Operation Bank precharged. Bank precharged. Bank precharged. Bank precharged. banks precharged.
input data write command latched same clock (Write latency output forced high impedance tOHZ) after DQM0 entry.
12/29
Semiconductor Page Read Write Cycle (Same Bank) Latency Burst Length
MD56V62320
ADDR
DQM0
*Notes:
High
Bank Active
lCCD
lOWD
*Note2
*Note1
Read Command
Read Command
Write Command
Write Command
Precharge Command
write data before burst read ends, DQM0 should asserted three cycles prior write command, avoid contention. assert precharge before burst write ends, wait after last write data input. Input data during precharge input cycle will masked internally.
13/29
,,,,
Semiconductor MD56V62320 Read Write Cycle with Auto Precharge Burst Length
High
tRRD
ADDR
Latency
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
A-Bank Precharge Start
DQM0
Latency
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
A-Bank Precharge Start
DQM0
Active (A-Bank)
Bank Read with Auto Precharge
Bank Write with Auto Precharge
Bank Precharge Start Point
Active (D-Bank)
14/29
Bank Interleave Random Read Cycle Latency Burst Length
ADDR
DQM0
MD56V62320
High
tRRD
QAa0 QAa1 QAa2 QAa3
QCb0 QCb1 QCb2 QCb3
QAc0 QAc1 QAc2 QAc3
Active (A-Bank)
Read Command (A-Bank)
Read Command (C-Bank)
Read Command (A-Bank)
Active (C-Bank)
Precharge Command (A-Bank)
Precharge Command (C-Bank) Active (A-Bank)
15/29
MD56V62320
Bank Interleave Random Write Cycle Latency Burst Length
High
ADDR
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3
DAc0 DAc1
DQM0
Active (A-Bank)
Active (B-Bank)
Write Command (A-Bank)
Precharge Command (A-Bank) Write Command (B-Bank)
Write Command (A-Bank)
Active (A-Bank)
Precharge Command (A-Bank)
Precharge Command (B-Bank)
16/29
Bank Interleave Page Read Cycle Latency Burst Length
ADDR
DQM0
*Note:
MD56V62320
High
*Note1
QAa0 QAa1 QAa2 QAa3 QCb0 QCb1 QCb2 QCb3 QAc0 QAc1 QCd0 QCd1 QAe0 QAe1
lROH
Active (A-Bank)
Active (C-Bank)
Read Command (C-Bank)
Precharge Command (A-Bank)
Read Command (A-Bank)
Read Command (C-Bank)
Read Command (A-Bank)
Read Command (A-Bank)
ignored when RAS, high same cycle.
17/29
Semiconductor MD56V62320 Bank Interleave Page Write Cycle Latency Burst Length
High
ADDR
DBa0 DBa1 DBa2 DBa3 DDb0 DDb1 DDb2 DDb3 DBc0 DBc1 DDd0
DQM0
Active (B-Bank)
Active (D-Bank)
Write Command (D-Bank)
Write Command (B-Bank)
Write Command (D-Bank)
Write Command (B-Bank)
Precharge Command (All Banks)
18/29
MD56V62320
Bank Interleave Random Read/Write Cycle Latency Burst Length
High
ADDR
QAa0 QAa1 QAa2 QAa3
DCb0 DCb1 DCb2 DCb3
QAc0 QAc1 QAc2 QAc3
DQM0
Active (A-Bank)
Active (C-Bank)
Write Command (C-Bank)
Read Command (A-Bank)
Read Command (A-Bank)
Precharge Command (A-Bank)
Active (A-Bank)
19/29
Semiconductor Bank Interleave Page Read/Write Cycle Latency Burst Length
MD56V62320
High
ADDR
DQM0
,,,,
CAa0 CDb0 CAc0 QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 QAc0 QAc1 QAc2 QAc3 Read Command (A-Bank) Write Command (D-Bank) Read Command (A-Bank)
20/29
MD56V62320
Clock Suspension Operation Cycle Latency Burst Length
*Note1
*Note1
ADDR
*Note4
DQ17 DQ25
*Note4 DQM0
DQM1
DQM2
DQM3
*Notes:
*Note3
tOHZ
*Note2
Read
Active
Read
Read Command
CLOCK Suspension
Read Command
Write Write CLOCK Command Suspension
When deactivated, next clock will ignored. When DQM0 asserted, read data after clock cycles will masked. When DQM0 asserted, write data same clock cycles will masked. When DQM0 High, input/output data will masked. When DQM1 High, input/output data DQ16 will masked. When DQM2 High, input/output data DQ17 DQ24 will masked. When DQM3 High, input/output data DQ25 DQ32 will masked.
21/29
Semiconductor Read Interruption Precharge Command Burst Length
MD56V62320
High
ADDR
Latency
*Note1
DQM0
Latency
*Note1
DQM0
Active
Read Command
Precharge Command
*Note:
precharge asserted before burst read ends, then read data will output after second clock cycle precharge command.
22/29
Semiconductor MD56V62320 Power Down Mode Latency Burst Length
*Note1
tPDE *Note2
ADDR
DQM0
Active
Power-down Entry
Power-down Exit
Clock Suspention Entry
Clock Suspention Exit Read Command
Precharge Command
*Notes:
When banks precharge state, low, then MD56V62320 enters power-down mode maintains mode while low. release circuit from power-down mode, high longer than tPDE (tSI CLK).
23/29
Semiconductor Self Refresh Cycle
ADDR
DQM0
MD56V62320
Self Refresh Entry
Self Refresh Exit
Active
24/29
Semiconductor Mode Register Cycle
MD56V62320 Auto Refresh Cycle
ADDR
DQM0
High High lMRD
Command
Auto Refresh
Auto Refresh
25/29
MD56V62320
FUNCTION TRUTH TABLE (Table (1/2)
Current State1 Idle Active Read Write Read with Auto Precharge Write with Auto Precharge ADDR Code ILLEGAL ILLEGAL Active Auto-Refresh Self-Refresh Mode Register Write Read Write ILLEGAL Precharge ILLEGAL (Continue Active after Burst ends) (Continue Active after Burst ends) Reserved Term Burst, start Burst Read Term Burst, start Burst Write ILLEGAL Term Burst, execute Precharge ILLEGAL (Continue Active after Burst ends) (Continue Active after Burst ends) Reserved (Term Burst) Active Term Burst, start Burst Read Term Burst, start Burst Write ILLEGAL Term Burst, execute Precharge ILLEGAL (Continue Burst enter Precharge) (Continue Burst enter Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Continue Burst enter Precharge) (Continue Burst enter Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Action
26/29
MD56V62320
FUNCTION TRUTH TABLE (Table (2/2)
Current State1 Precharge Write Recovery Active Refresh Mode Register Access ABBREVIATIONS Address Column Address Notes: ADDR Idle after Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Active after tRCD Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Action
Bank Address Auto Precharge
OPeration command
inputs enabled when high least cycle prior inputs. Illegal bank specified state, legal some cases depending state bank selection. Satisfy timing lCCD prevent contention. bank precharging idle state. Precharges activated bank A10. Illegal bank idle.
27/29
MD56V62320
FUNCTION TRUTH TABLE (Table
Current State CKEn-1 Self Refresh Power Down Banks Idle (ABI)
CKEn
ADDR INVALID
Action Exit Self Refresh Exit Self Refresh ILLEGAL ILLEGAL ILLEGAL (Maintain Self Refresh) INVALID Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL (Continue power down mode) Refer Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL Refer Operations Table Begin Clock Suspend Next Cycle Enable Clock Next Cycle Continue Clock Suspension
State Other than Listed Above
Note:
Power-down self refresh entered only when banks idle state.
28/29
MD56V62320
PACKAGE DIMENSIONS
(Unit
TSOPII86-P-400-0.50-K Preliminary
Mirror finish
Package material Lead frame material treatment Solder plate thickness Package weight
Epoxy resin alloy Solder plating more TYP.
Notes Mounting Surface Mount Type Package SOP, QFP, TSOP, TQFP, LQFP, SOJ, (PLCC), SHP, surface mount type packages, which very susceptible heat reflow mounting humidity absorbed storage. Therefore, before perform reflow mounting, contact Oki's responsible sales person product name, package name, number, package code desired mounting conditions (reflow method, temperature times).
29/29
E2Y0002-29-11
NOTICE
information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents cotained herein reprinted reproduced without prior permission. MS-DOS registered trademark Microsoft Corporation.
Copyright 1999 Electric Industry Co., Ltd.
Printed Japan

Semiconductor MD56V62320 This version: Apr. 1999 MD56V62320

Top Searches for this datasheet

Other recent searches