FN3555.6 Serial Filter Serial Filter high performance filter

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FN3555.6 Serial Filter Serial Filter high performance filter

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HSP43124
FN3555.6
Serial Filter
Serial Filter high performance filter engine that ideal loading burden filter processing from microprocessor. supports variety multistage filter configurations based user programmable filter fixed coefficient halfband filters. These configurations include programmable filter taps, cascade from five halfband filters, cascade halfband filters followed programmable FIR. half band filters each decimate factor two, filter decimates from eight. When filters selected, maximum decimation provided. digital tuning applications, separate multiplier provided which allows incoming data stream multiplied, mixed, user supplied factor. interface provided serially loading factor from external source selecting factor from onboard ROM. on-board contains samples sinusoid capable spectrally shifting input data quarter sample rate, FS/4. This allows chip function digital down converter when filter stages configured low-pass filter. serial interface for3- input output data compatible with serial ports common microprocessors. Coefficients configuration data loaded over bidirectional eight interface.
Features
45MHz Clock Rate Programmable Filter 24-Bit Data, 32-Bit Coefficients Cascade Half Band Filters Decimation from Interface Down Conversion FS/4 Multiplier Mixing Scaling Input with External Source Serial Compatible with Most Microprocessors
Applications
Cost Filter Filter Co-Processor Digital Tuner
Ordering Information
PART NUMBER HSP43124PC-45 HSP43124PC-33 HSP43124SC-45 HSP43124SC-33 HSP43124SI-40 TEMP. RANGE (oC) PACKAGE PDIP PDIP SOIC SOIC SOIC PKG. E28.6 E28.6 M28.3 M28.3 M28.3
Block Diagram
INPUT FORMATTER
OUTPUT FORMATTER
SCLK SYNCIN MXIN SYNCMX HALF BAND FILTER HALF BAND FILTER HALF BAND FILTER
PROGRAMMABLE FILTER
DOUT SYNCOUT CLKOUT
CONTROL INTERFACE
A0-2
C0-7
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. Rights Reserved
FSYNC
FCLK
HSP43124 Pinout
LEAD PDIP, SOIC VIEW
SCLK SYNCIN
DOUT SYNCOUT CLKOUT
MXIN SYNCMX FSYNC FCLK
HSP43124 Description
NAME TYPE Power Supply Ground Serial Data Input. value present this input sampled rising edge SCLK. "HIGH" this input represents "1", this input represents "0". word format operation serial interface contained Data Input Section. Data Sync. HSP43124 synchronized beginning data word when SCLK samples SYNCIN "HIGH" SCLK before first word. NOTE: SYNCIN should maintain "HIGH" state longer than SCLK cycle. Serial Input CLK. rising edge SCLK clocks data MXIN into part. following signals synchronous this clock: DIN, SYNCIN, MXIN, SYNCMX. Factor Input. MXIN serial input factor. sampled rising edge SCLK. "HIGH" this input represents "1", this input represents "0". Also used specify Weaver Modulator output part FS/4 down conversion interface. Details word format operation contained Factor Section. Factor Sync. HSP43124 synchronized beginning serially input factor when SCLK samples SYNCMX "HIGH" SCLK before first factor. NOTE: SYNCMX should only pulse "HIGH" SCLK cycle. Also used specify Weaver Modulator output part FS/4 down conversion interface. Filter Clock. filter clock determines processing speed Filter Compute Engine. Clock rate requirements FCLK particular filter configurations discussed Filter Compute Engine Section. This clock asynchronous serial input clock (SCLK). FSYNC synchronous this clock. Filter Sync. This input, when sampled rising edge FCLK, resets filter compute engine that data sample following next SYNCIN cycle first data sample into filter structure. data stream currently being input, current products input data "canceled" ignored until next SYNCIN cycle occurs. Write. falling edge loads data present C0-7 into configuration coefficient register specified address A0-2. signal asynchronous other clocks. NOTE: should when low. Read. falling edge accesses control registers coefficient addressed A0-2 places contents that memory location C0-7. When returns "HIGH" C0-7 functions input bus. asynchronous other clocks. NOTE: should when low. Address Bus. A0-2 inputs decoded falling edge both Table shows address control registers. Control Coefficient bus. This bidirectional used access control registers coefficient RAM. Output Clock. Programmable clock serial output. NOTE: Assertion FSYNC initializes CLKOUT high state. Output Data Sync. SYNYOUT asserted HIGH CLKOUT cycle before first output sample available DOUT. Serial Data Output. stream synchronous rising edge CLKOUT. (See Serial Output Formatter section additional details.) DESCRIPTION
SYNCIN
SCLK
MXIN
SYNCMX
FCLK
FSYNC
A0-2
C0-7 CLKOUT
SYNCOUT
DOUT
HSP43124
INPUT FORMATTER VARIABLE LENGTH SHIFT REGISTER (8-24-BITS) BITS FORMAT SYNCIN
FILTER COMPUTE ENGINE
OUTPUT FORMATTER MULTIPLY/ ACCUMULATOR
SYNCIN
INPUT HOLDING FACTOR HOLDING
FCLK CLKOUT BITS SYNCOUT ROUND/ SATURATE CLKOUT DOUT
SERIAL MULTIPLIER
ROUND/ SATURATE
REGISTER FILE
SYNCMX
SYNCMX MXIN WEAVER MODULATOR
PARAMETERS
CONTROL
FILT
ROUND DECIMATION FORMAT RATE GAIN FILTER LENGTH ACCESS
CONTROL HALFBAND COEFFICIENT COEFFICIENT
MXIN
VARIABLE LENGTH SHIFT REGISTER BITS)
BITS FORMAT
A0-2 C0-7 FSYNC FCLK SCLK
Indicates configuration control word data parameter. FIGURE SERIAL FILTER BLOCK DIAGRAM
Functional Descriptions
HSP43124 high performance digital filter designed process serial input data stream. second serial interface provided factor inputs, which multiplied input samples shown Figure multiplier result passed Filter Compute Engine processing. Filter Compute Engine centers around single multiply/accumulator (MAC). performs sum-ofproducts required particular filter configuration. processing rate determined filter clock, FCLK. Increasing FCLK relative input sample rate increases length filter that realized. filtered results passed Output Formatter where they rounded truncated user defined width. Output Formatter then generates timing synchronization signals required serially transmit data external device.
Data written configuration control registers falling edge input. This requires that address, A0-2, data, C0-7, stable valid falling edge shown Figure NOTE: should active when active low. Data read from configuration control registers falling edge input. contents particular register accessed setting address, A0-2, falling edge shown Figure data output C0-7. data C0-7 remains valid until returns HIGH, which point C0-7 Three-Stated functions input. proper operation, address A0-2 must held until returns "high" shown Figure NOTE: should active when active low.
WRITE TIMING
A0-2 C0-7 READ TIMING A0-2 C0-7
Filter Configuration
HSP43124 configured operation loading eight control registers. These registers written through bidirectional interface which also used reading control registers. interface consists 8-bit data bus, C0-7, 3-bit address bus, A0-2, read/write lines, address control registers shown Table
FIGURE READ/WRITE TIMING
HSP43124
TABLE CONFIGURATION CONTROL REGISTER FUNCTIONAL DESCRIPTION ADDRESS REGISTER DESCRIPTION Filter Configuration POSITIONS FUNCTION Specifies number halfbands use. Number ranges from Other values invalid. Filter Enable bit. Enable. Minimum filter bypass (either must enabled output). Coefficient read enable. When enables reading disables writing coefficient RAM. NOTE: This must prior writing Coefficient RAM. Decimation Rate. Range 000). Number Taps Programmable Filter. even symmetric filters, values range from 256, invalid, 0000000 256. asymmetric filters, value loaded this register must times actual number coefficients. Coefficient loaded multiple writes this address. (See Writing Coefficients section additional details.) Number bits input data word, from (01000) (11000). Values outside range invalid. Number System. Two's Complement, Offset Binary. Serial Format. First, First. Unused Number FCLKS CLKOUT. Range (00000 FCLKS) First, First. Unused Number bits output data word, from value represented 00000, values from invalid. Round Select. Round Selected Number Bits, Truncate. Number System. Two's Complement, Offset Binary. Gain Correction. Apply scale factor data. Scaling. Even Symmetric Coefficients Non-Symmetric Coefficients Symmetric Reserved: Must Number bits factor, from (01000) (11000). Values outside range invalid. Serial Format. First, First. Factor Select. Serial Input, Weaver modulator look-up-table. Unused
Programmable Filter Length
Coefficient Access Input Format
Output Timing
Output Format
Filter Symmetry
Factor Format
Writing Coefficients
HSP43124 provides register bank store filter coefficients configurations which programmable filter. register bank consists thirty-two-bit registers. Each register loaded byte writes bidirectional interface used loading configuration registers. coefficients loaded order from least significant byte (LSB) most significant byte (MSB).
coefficient registers loaded first setting coefficient read enable (bit Filter Configuration Register). Next, coefficients loaded setting A2-0 address (binary) writing byte time shown Figure down loaded bytes stored holding register until write cycle. completion fourth write cycle, contents holding register loaded into Coefficient RAM, write pointer incremented next register. user attempts write more than coefficients, pointer
HSP43124
halts 128th register location, writing disabled. coefficient address pointer reset when other configuration register written read. NOTE: coefficient loaded during filter calculation risk corrupting output data until load complete.
A0-2 C0-7 A0-2 (BINARY) X(n) INPUT FIRST COEFFICIENT SECOND COEFFICIENT FIRST FILTER Y(n) C0X2 C1X1 LAST FILTER
ending with center tap. coefficient associated with first first multiplied incoming data sample shown Figure even/odd symmetric filters length coefficients must loaded filter length even, (N+1)/2 coefficients must loaded filter length odd. example, symmetric filter would require loading coefficients. Enough storage provided symmetric filter.
FIGURE COEFFICIENT LOADING
Y(n) OUTPUT
number coefficients that must loaded dependent whether coefficient exhibits even symmetry, symmetry, asymmetry (see Figure
FIGURE THREE TRANSVERSAL FILTER ARCHITECTURE
EVEN SYMMETRIC
POINT SYMMETRY LENGTH EVEN LENGTH
asymmetric filters entire coefficient must loaded. coefficients loaded order starting with first ending with final filter (see Figure tap/coefficient association). Enough storage provided asymmetric filter. asymmetric filters value loaded into Programmable Filter Length Register addressed must twice actual number coefficients.
NOTE: Filters with even symmetric coefficients exhibit symmetry about center coefficient set. Most filters have coefficients which symmetric nature. SYMMETRIC
0.25 -0.1 -0.25 -0.5 CENTER COEFFICIENT
Reading Coefficients
coefficients read from storage registers byte time C0-7 shown Figure read coefficients, user first sets Coefficient Read Enable (bit Filter Configuration Control Register). Setting this resets read pointer disables from being written. Next, with A2-0 010, multiple "high" "low" transitions output coefficients C0-7, byte time, order they were written. NOTE: should "low" when "low".
NOTE: symmetric coefficients have coefficient envelope which characteristics function (i.e. coefficients which equidistant from center coefficient equal magnitude opposite sign). Coefficients designed function differentiator Hilbert Transform exhibit these characteristics. ASYMMETRIC
A0-2 C0-7 A0-2 (BINARY)
FIRST COEFFICIENT
SECOND COEFFICIENT
FIGURE COEFFICIENT READING NOTE: Asymmetric Coefficient sets exhibit symmetry. FIGURE COEFFICIENT CHARACTERISTICS
Data Input
Data serially input HSP43124 through input. rising edge SCLK, value present clocked into Variable Length Shift Register. beginning serial data word designated asserting SYNCIN "high" SCLK prior first data shown
filters that exhibit either even symmetry, only unique half coefficient must loaded. coefficients loaded order starting with first filter
HSP43124
Figure following SCLK, first data clocked into Variable Length Shift Register. Data bits clocked into shift register until data word, user programmable length bits), complete. this point, shifting data into register disabled contents held until SYNCIN asserted rising edge SCLK. When this occurs, contents Variable Length Shift Register transferred Input Holding Register, shift register enabled accept serial data following SCLK. serial data word two's complement offset binary input most significant (MSB) first least significant (LSB) first defined Input Format Register (see Table data word specified less than bits, least significant bits Input Holding Register zeroed. NOTE: SYNCIN should "high" longer than SCLK cycle. multiplier. factor data word programmable length from bits input first specified Factor Format Register. data word specified less than bits, least significant bits Factor Holding Register zeroed. MXIN SYNCMX inputs function interfaces Weaver Modulator addresses. Used proper sequence, down conversion FS/4 achieved. These inputs latched rising edge SCLK when SYNCIN high shown Figure mapping SYNCIN MXIN outputs given Table When SYNCIN high rising edge SCLK, output transferred Factor holding register, SYNCMX MXIN inputs decoded produce output. result, there latency SYNCIN cycle between when SYNCMX MXIN inputs decoded when output loaded into Factor Holding register.
TABLE WEAVER MODULATOR DECODING SYNCMX
SYNC LEADS DATA
SCLK SYNCIN/ SYCNMX DIN/ MXIN
MXIN
FACTOR
NOTE: Assumes data being loaded first. FIGURE SERIAL INPUT TIMING EITHER MXIN INPUTS
Serial Multiplier
Serial Multiplier multiplies Factor Holding register contents Input Holding register. multiplication cycle initiated when SYNCIN sampled high rising edge SCLK. This transfers contents Variable Length Shift register Input Holding Register, loads output Factor Holding Register into Serial Multiplier. subsequent SCLKs, contents Input Holding Register shifted into Serial Multiplier processing. When last data shifted into multiplier, multiplication cycle complete result written Register File next rising edge FCLK. synchronization between data sample factor multiplied dependent which factor source specified. factors which input serially, factor loaded concurrently with data sample multiplied (see Figure
Factor
HSP43124 provides second serial interface loading values which multiplied input samples serial multiplier. These values, factors, input using MXIN SYNCMX pins. Aside from being used serial input, this interface also used select factors from Weaver Modulator ROM. factor source specified Factor Format Register (see Table NOTE: Data passed unmodified through serial multiplier selecting Weaver Modulation factor source tying both SYNCMX MXIN "high". procedure loading serial factors similar that loading data input. value present MXIN clocked into Variable Length Shift register rising edge SCLK. beginning serial word designated assertion SYNCMX SCLK prior first serial word shown Figure After serial word been clocked into shift register, shifting bits into register disabled contents held until next assertion SYNCMX. When SYNCMX asserted rising edge SCLK, contents Variable Length Shift register transferred into Factor Holding Register. parallel output Factor Holding Register feeds directly into serial
HSP43124
SCLK SYNCIN
cascade five halfband filters efficient decimating filter structure. Each fixed coefficient filter chain introduces decimation two, aggregate decimation rate entire halfband filtering stage given
DECHB 2(NUMBER HALFBAND FILTERS SELECTED) (EQ.
SYNCMX MXIN
Thus, cascade halfband filters would decimate input sample stream factor Figure block diagram halfband filter section. normalized frequencies each halfband stage labeled. Figure illustration cascaded filter composed five halfband filters. final stage filter output clocked FCLK/32. Since output each filter half rate input, five halfband filter passband characteristics viewed single plot whose axis normalized filter output clock rate. Notice that halfband filters, design, have 120dB passbands that less than output rate divided Since alias profile well below -120dB filter passband, alias concerns eliminated. frequency responses five filters presented graphically Figure tabular form Table Notice that passband bandwidth 0.25) identical five halfband filters. width transition band, however, different each filter. transition band fifth halfband filter, HB5, narrowest while that first halfband filter, HB1, widest. cascade halfband filters always terminates with preceded filters order increasing transition bandwidth. example, HSP43124 configured operate with three halfbands, chain filters would consist followed terminated with HB5. only halfband selected, used.
SYNC LEADS DATA
FIGURE DATA/MIX FACTOR SYNCHRONIZATION SERIALLY INPUT FACTORS NOTE: Figure shows loading data sample, such that will multiplied factor designated factor widths which less than input width, SYNCMX asserted before SYNCIN desired.
factor generated Weaver Modulator ROM, factor must specified MXIN SYNCMX SYNCIN before that which precedes target data word (see Figure
SCLK SYNCIN
SYCNMX/ MXIN SYNC LEADS DATA
FIGURE DATA/MIX FACTOR SYNCHRONIZATION WEAVER MODULATOR FACTORS
Filter Compute Engine
Filter Compute Engine centers around multiply accumulator which used perform sum-of-products required variety filtering configurations. These configurations include cascade halfband filters, single symmetric filter taps, single asymmetric filter taps, cascade halfband filters followed programmable filter. filter configuration specified programming Filter Configuration Register (see Table
HSP43124
INPUT HALFBAND SECTION FNORMALIZED Fs/2 MUX5 FNORMALIZED FHB1 FHB1= Fs/2 MUX4 FNORMALIZED FHB2 MUX3 FNORMALIZED FHB3 FHB3 FHB2 FHB2/2 FHB3/2 MUX2 FNORMALIZED FHB4 FHB4 FHB3 FHB3/2 MUX1 FHB4/2 FHB1/2 FHB2 FHB1 FHB1/2 FHB2/2 STAGE FCLK FCLK FCLK FCLK FCLK FCLK FCLK STAGE FCLK FCLK STAGE FCLK FCLK 3FCLK FCLK
STAGE FCLK FCLK FCLK FCLK STAGE FCLK COMPOSITE FILTER FCLK FCLK FCLK FCLK FCLK FCLK
FCLK
FIGURE 10B. SPECTRAL COMPOSITION FIVE CASCADED HALFBANDS
OUTPUT HALFBAND SECTION BANDWIDTH
MULTIPLEXERS' DECODER TABLE EQUATIONS MAGNITUDE (dB) BITS2-0 MUX1 MUX2 MUX3 MUX4 MUX5
-100 -120 -140 -160 -180 -200 0.125 0.25 0.375 NORMALIZED FREQUENCY (NORMALIZED OUTPUT FREQUENCY) TRANSITION
MUX1 (BIT2 BIT0) BIT1 MUX2 BIT2 MUX3 (BIT1 BIT0) BIT2 MUX4 BIT1 BIT2 MUX5 BIT0 BIT1 BIT2 INVALID BIT2 BIT1
FIGURE 10A. BLOCK DIAGRAM FIXED COEFFICIENT HALFBAND FILTERS
FIGURE 10C. COMPOSITE RESPONSE FIXED COEFFICIENT HALFBAND FILTERS WITH RESPECT NORMALIZED FREQUENCY SHOWN FIGURE
HSP43124
coefficient each halfband filters given Table These values 32-bit, two's complement, integer representation filter coefficients. Scaling these values 2-31 yields fractional two's complement coefficients used achieve unity gain Filter Processor. specific frequency response desired, programmable filter activated. filter compute engine takes advantage symmetry coefficients summing data samples sharing common coefficient prior multiplication. this manner, filter taps calculated multiply accumulate cycle. asymmetric filter specified, only multiply accumulate cycle calculated. processing rate Filter Compute Engine proportional FCLK. result, frequency FCLK must exceed minimum value insure that filter calculation complete before result required output. configurations which decimation, input sample period available filter calculation before output required. configurations which employ decimation, input sample periods available filter calculation. following equation specifies minimum FCLK rate required configurations which programmable filter filter.
TAPS/(2*DEC CLKS least14F when Halfbands used
DECHB aggregate decimation rate cascade halfband filters (see Table example, input sample rate 800kHz, filter with decimation selected, cascade halfband filters used, calculate minimum FCLK rate follows:
FCLK
Thus, FCLK 19.6MHz.
NOTE: configurations which halfband filters used, FCLK rate must exceed 14FS.
longest length filter realizable particular configuration determined solving above equation TAPS. resulting expression given below.
TAPS 2DECFIR ((FCLK/FS)DECHB HBCLKS (EQ.
maximum throughput sample rate specified solving above equation resulting equation
FCLK*DECHB /(TAPS/(2*DECFIR) HBCLKS (EQ. NOTE: configurations using filters with asymmetric coefficients, term TAPS above equations should multiplied order determine correct FCLK.
FCLK
(EQ.
this equation input sample rate (SCLK/# Bits word), TAPS number taps filter 256), DECFIR decimation rate programmable HBCLKS compute clock factor based number halfband filters configuration (see Table
Filter Compute Engine synchronized with incoming data stream asserting FSYNC input. When this input sampled rising edge FCLK, Compute Engine reset, data word following next assertion SYNCIN recognized first data sample input filter structure.
TABLE FREQUENCY RESPONSE HALFBAND FILTERS NORMALIZED FREQUENCY 0.000000 0.007812 0.015625 0.023438 0.031250 0.039062 0.046875 0.054688 0.062500 0.070312 0.078125 0.085938 0.093750 HALFBAND -0.000000 0.000000 -0.000113 -0.000677 -0.002243 -0.005569 -0.011596 -0.021433 -0.036333 -0.057670 -0.086916 -0.125619 -0.175382 HALFBAND 0.000000 -0.000000 -0.000000 -0.000006 -0.000052 -0.000227 -0.000719 -0.001859 -0.004165 -0.008391 -0.015557 -0.026983 -0.044301 HALFBAND 0.000000 -0.000000 -0.000000 -0.000000 -0.000000 -0.000000 -0.000001 -0.000009 -0.000041 -0.000149 -0.000448 -0.001175 -0.002767 HALFBAND -0.000000 -0.000000 -0.000000 -0.000000 -0.000000 -0.000000 0.000000 -0.000000 -0.000000 -0.000001 -0.000012 -0.000066 -0.000258 HALFBAND -0.000000 -0.000000 -0.000000 -0.000000 -0.000000 0.000000 -0.000000 -0.000000 -0.000000 -0.000000 -0.000000 -0.000000 -0.000000
200kHz 19.6M
(EQ.
least (800kHz) 11.2MHz
HSP43124
TABLE FREQUENCY RESPONSE HALFBAND FILTERS (Continued) NORMALIZED FREQUENCY 0.101562 0.109375 0.117188 0.125000 0.132812 0.140625 0.148438 0.156250 0.164062 0.171875 0.179688 0.187500 0.195312 0.203125 0.210938 0.218750 0.226562 0.234375 0.242188 0.250000 0.257812 0.265625 0.273438 0.281250 0.289062 0.296875 0.304688 0.312500 0.320312 0.328125 0.335938 0.343750 0.351562 0.359375 0.367188 0.375000 0.382812 0.390625 0.398438 0.406250 0.414062 0.421875 HALFBAND -0.237843 -0.314663 -0.407509 -0.518045 -0.647925 -0.798791 -0.972266 -1.169959 -1.393465 -1.644372 -1.924262 -2.234728 -2.577375 -2.953834 -3.365774 -3.814917 -4.303048 -4.832037 -5.403856 -6.020599 -6.684504 -7.397981 -8.163642 -8.984339 -9.863195 -10.803663 -11.809574 -12.885208 -14.035372 -15.265501 -16.581776 -17.991278 -19.502172 -21.123947 -22.867725 -24.746664 -26.776485 -28.976198 -31.369083 -33.984089 -36.857830 -40.037594 HALFBAND -0.069457 -0.104701 -0.152566 -0.215834 -0.297499 -0.400727 -0.528809 -0.685131 -0.873129 -1.096269 -1.358019 -1.661842 -2.011181 -2.409468 -2.860128 -3.366593 -3.932319 -4.560817 -5.255675 -6.020600 -6.859450 -7.776287 -8.775419 -9.861469 -11.039433 -12.314765 -13.693460 -15.182171 -16.788332 -18.520315 -20.387625 -22.401131 -24.573368 -26.918915 -29.454887 -32.201569 -35.183285 -38.429543 -41.976673 -45.870125 -50.167850 -54.945438 HALFBAND -0.005963 -0.011924 -0.022368 -0.039695 -0.067100 -0.108640 -0.169262 -0.254777 -0.371785 -0.527552 -0.729872 -0.986908 -1.307047 -1.698769 -2.170548 -2.730783 -3.387764 -4.149669 -5.024594 -6.020600 -7.145791 -8.408404 -9.816921 -11.380193 -13.107586 -15.009147 -17.095793 -19.379534 -21.873730 -24.593418 -27.555685 -30.780161 -34.289623 -38.110786 -42.275345 -46.821358 -51.795181 -57.254162 -63.270584 -69.937607 -77.378593 -85.762718 HALFBAND -0.000815 -0.002208 -0.005313 -0.011613 -0.023435 -0.044186 -0.078552 -0.132639 -0.214009 -0.331613 -0.495620 -0.717181 -1.008144 -1.380771 -1.847495 -2.420719 -3.112694 -3.935463 -4.900864 -6.020600 -7.306352 -8.769932 -10.423476 -12.279667 -14.352002 -16.655094 -19.205034 -22.019831 -25.119940 -28.528942 -32.274414 -36.389088 -40.912403 -45.892738 -51.390583 -57.483341 -64.272881 -71.898048 -80.556969 -90.550629 -102.379677 -117.007339 HALFBAND -0.000000 -0.000000 -0.000000 -0.000000 -0.000031 -0.000287 -0.001468 -0.005427 -0.016180 -0.041152 -0.092409 -0.187497 -0.349593 -0.606862 -0.991193 -1.536664 -2.278126 -3.250174 -4.486639 -6.020600 -7.884833 -10.112627 -12.738912 -15.801714 -19.344007 -23.416153 -28.079247 -33.409992 -39.508194 -46.509052 -54.604954 -64.087959 -75.444221 -89.610390 -108.973686 -152.503693 -153.443375 -158.914017 -156.960175 -153.317627 -161.115540 -153.504684
HSP43124
TABLE FREQUENCY RESPONSE HALFBAND FILTERS (Continued) NORMALIZED FREQUENCY 0.429688 0.437500 0.445312 0.453125 0.460938 0.468750 0.476562 0.484375 0.492188 HALFBAND -43.585945 -47.588165 -52.164894 -57.495132 -63.861992 -71.755898 -82.156616 -97.627930 -139.751450 HALFBAND -60.304272 -66.385063 -73.392075 -81.640152 -91.658478 -104.468010 -122.641861 -166.537369 -165.699081 HALFBAND -95.332924 -106.462181 -119.793030 -136.802948 -175.030167 -158.939362 -157.095886 -155.613434 -154.708450 HALFBAND -136.890198 -185.130432 -187.297241 -182.300125 -203.460876 -174.691895 -174.737076 -175.108841 -169.966568 HALFBAND -158.650345 -154.637756 -153.870453 -161.882385 -152.278915 -164.329758 -153.535690 -153.507477 -167.665482
TABLE HALFBAND FILTER COEFFICIENTS BITS, UN-NORMALIZED) COEFFICIENT HALFBAND -67230275 604101076 1073741823 604101076 -67230275 HALFBAND 12724188 -105279784 629426509 1073741827 629426509 -105279784 12724188 HALFBAND 624169 -6983862 38140187 -145867861 650958284 1073741793 650958284 -145867861 38140187 -6983862 624169 HALFBAND -197705 2303514 -13225905 51077176 -161054660 657968488 1073741825 657968488 -161054660 51077176 -13225905 2303514 -197705 HALFBAND 23964 -242570 1306852 -4942818 14717750 -37027884 84032070 -191585682 670589251 1073741824 670589251 -191585682 84032070 -37027884 14717750 -4942818
HSP43124
TABLE HALFBAND FILTER COEFFICIENTS BITS, UN-NORMALIZED) (Continued) COEFFICIENT HALFBAND HALFBAND HALFBAND HALFBAND HALFBAND 1306852 -242570 23964
TABLE PERFORMANCE ENVELOPE PARAMETERS NUMBER HALFBANDS HBCLKS DECHB
duty cycle CLKOUT rates that have even number FCLKs CLKOUT. rates that have number FCLKs CLKOUT high portion CLKOUT waveform spans (n+1)/2 FCLKs portion spans (n-1)/2 FCLKs where number FCLKs. External devices synchronize beginning output data word monitoring SYNCOUT. This output asserted "high" CLKOUT prior first next data word shown Figure
CLKOUT SYNCOUT
Serial Output Formatter
Output Formatter serializes parallel output filter compute engine generates timing synchronization signals required support serial interface. Formatter produces serial data words with programmable lengths from bits. data words organized with either most least significant first. Also, data word rounded truncated desired length format output data specified either two's complement offset binary. simplify applications where Serial Filter used down converter, output formatter configured scale output factor above options programmed Output Format Output Timing Registers detailed Table HSP43124 outputs stream through DOUT which synchronous programmable clock signal output CLKOUT. output clock, CLKOUT, derived from FCLK programmable rate from 1/32 times FCLK.
DOUT
SYNC LEADS DATA
NOTE: Assumes data being output first. FIGURE SERIAL OUTPUT TIMING
Input Output Data Formats
data formats input, output coefficients fractional two's complement. weightings data words given Figure Input output data words programmed have less than bits, most significant positions 24-bit word. example, input word defined bits wide would positions with weightings from 2-7.
FRACTIONAL TWO'S COMPLEMENT FORMAT 24-BIT INPUT OUTPUT
2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23
FRACTIONAL TWO'S COMPLEMENT FORMAT 32-BIT COEFFICIENTS
2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 NOTE: negative sign implies complement formt. FIGURE DATA FORMATS
HSP43124 FCLK/SCLK Uncertainty Region
Figure shows clocking relationship HSP43124 Serial filter that could result uncertainty output. simplicity, frequency FCLK SCLK assumed equal each other, CLKOUT assumed equal FLCK. When rising edge FCLK lags behind rising edge SCLK small amount time (TSCFC), then FCLK edge which samples read into filter compute engine determined race condition. order insure proper function HSP43124, TSCFC must greater than 3.8ns. exact timing particular clock edge specific data bit) then make SCLK FCLK synchronous. FCLK SCLK asynchronous, there will jitter specific data will output possible clock edges depending FCLK SCLK phasing). multiple part applications, synchronous clocks separate syncs what receives each data, outputs vary clock cycle. SYNCOUT jitter demonstrated frequency example generalized other asynchronous FFCLK/FSCLK ratios. Setting frequencies FCLK SCLK integer multiples another eliminates timing jitter output sample rate.
SCLK SYNCIN CLKOUT SYNCOUT DOUT NULL
FIGURE 14A. NUMBER CLKOUT NUMBER BITS TIME PERIOD BETWEEN SYNCOUTS WHERE FFCLK/FSCLK
SCLK SYNCIN
SCLK SYNCIN
FCLK SYNCOUT DOUT TSCFC
CLKOUT SYNCOUT DOUT
FIGURE FCLK/SCLK UNCERTAINTY REGION
FIGURE 14B. NUMBER CLKOUT NUMBER BITS TIME PERIOD BETWEEN SYNCOUTS WHERE FFCLK/FSCLK
Asynchronous FCLK SCLK
FCLK SCLK asynchronous clocks, then output sample rate (tracked SYNCOUT) HSP43124 might jitter real time system. This jitter will demonstrated using SCLK with period that times period FCLK (i.e., FFCLK/FSCLK 3/2), shown Figure Figure 14B. occurs when there FCLK edges SCLK period (see Figure 14A), then null data will occur DOUT data stream. occurs when there FCLK edge SCLK period (see Figure 14B), then null data will occur. Given period relationship between FCLK SCLK, user that SYNCOUT jitters clock. example, output data represent bits, then number CLKOUT rising edges between SYNCOUT pulses should jitter between
HSP43124
Absolute Maximum Ratings
Supply Voltage. +7.0V Input, Output Voltage .GND -0.5V +0.5V Rating Class
Thermal Information
Thermal Resistance (Typical, Note (oC/W) SOIC Package. PDIP Package Maximum Junction Temperature 150oC Maximum Storage Temperature -65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Voltage Range (Commercial). 4.75V 5.25V Voltage Range (Industrial) 4.75V 5.25V Temperature Range (Commercial) 70oC Temperature Range (Industrial). -40oC 85oC
Characteristics
Gate Count .40,304
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Power Supply Current Standby Power Supply Current Input Leakage Current Output Leakage Current Clock Input High Clock Input Logical Input Voltage Logical Zero Input Voltage Logical Output Voltage Logical Zero Output Voltage Input Capacitance Output Capacitance NOTES:
5.0V +5%, 70oC Commercial, -40o 85oC Industrial SYMBOL ICCOP ICCSB VIHC VILC COUT TEST CONDITIONS Max, FCLK SCLK 45MHz Notes Max, Outputs Loaded Max, Input Max, Input Max, FCLK SCLK Min, FCLK SCLK -5mA, 5mA, FCLK SCLK 1MHz Measurements Referenced GND. 25oC, Note UNITS
Power supply current proportional frequency. Typical rating 4.5mA/MHz. Output load test circuit 40pF. tested, characterized initial design major process/design changes.
HSP43124
Electrical Specifications
(Note +4.75V +5.25V, 70oC (Commercial) +4.75V +5.25V, -40oC 85oC (Industrial) 45MHz PARAMETER FCLK, SCLK Period FCLK, SCLK High FCLK, SCLK Setup Time DIN, MXIN, SYNCIN, SYNCMX SCLK Hold Time DIN, MXIN, SYNCIN, SYNCMX from SCLK Setup Time FSYNC FCLK Hold Time FSYNC from FCLK Setup Time C0-7, A0-2 Falling Edge Hold Time C0-7, A0-2 from Falling Edge Setup Time A0-2 Falling Edge Hold Time A0-2 from Rising Edge High High Data Valid High Output Disable FCLK CLKOUT CLKOUT SYNCOUT, DOUT Output Rise, Fall Time NOTES: tests performed with 40pF, 5mA, -5mA. Input reference level FCLK SCLK 2.0V, other inputs 1.5V. Test 3.0V, VIHC 4.0V, Controlled design process parameters directly tested. Characterized upon initial design after major process and/or changes. SYMBOL tWRH tWRL tRDH tRDO tFOC Note NOTES 40MHz 33MHz UNITS
Test Load Circuit
(NOTE)
SWITCH OPEN ICCSB ICCOP
1.5V
EQUIVALENT CIRCUIT
NOTE: Test head capacitance.
HSP43124 Waveforms
tWRH tWRL
C0-7, A0-2
2.0V 0.8V
FIGURE TIMING RELATIVE
FIGURE OUTPUT RISE FALL TIMES
tRDH
SCLK DIN, MXIN, SYNCIN, SYNCMX
A0-2
C0-7 tRDO
FIGURE INPUT DATA TIMING
FIGURE TIMING RELATIVE READ
tFOC FCLK
CLKOUT
SYNCOUT
DOUT
FSYNC
FIGURE TIMING RELATIVE FLCK CLKOUT
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FN3555.6 Serial Filter Serial Filter high performance filter

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