SHEET SHEET STATUS SHEETS SHEET PREPARED RICK OFFICER PMIC

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REVISIONS DESCRIPTION Make change 1.2.4. accordance with N.O.R. 5962-R086-96. device class case outline Make editorial changes throughout. Redrawn. DATE (YR-MO-DA) 96-03-20 96-08-16 APPROVED M.A. FRYE MONNIN
SHEET SHEET STATUS SHEETS SHEET
PREPARED RICK OFFICER
PMIC
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216
STANDARD MICROCIRCUIT DRAWING
THIS DRAWING AVAILABLE DEPARTMENTS AGENCIES DEPARTMENT DEFENSE
CHECKED RAJESH PITHADIA
APPROVED MICHAEL FRYE
MICROCIRCUIT, LINEAR, MHZ, 64-BIT, VIDEO INTERFACE PALETTE, MONOLITHIC SILICON
DRAWING APPROVAL DATE 96-01-12 SIZE REVISION LEVEL CAGE CODE
AMSC
SHEET
67268
5962-96758
DESC FORM DISTRIBUTION STATEMENT Approved public release; distribution unlimited.
5962-E497-96
SCOPE Scope. This drawing documents three product assurance class levels consisting high reliability (device classes space application (device class nontraditional performance environment (device class choice case outlines lead finishes available reflected Part Identifying Number (PIN). When available, choice Radiation Hardness Assurance (RHA) levels reflected PIN. device class user cautioned assure that device appropriate application environment. PIN. shown following example: 5962
96758
Federal stock class designator
designator (see 1.2.1) Drawing number
Device type (see 1.2.2)
Device class designator (see 1.2.3)
Case outline (see 1.2.4)
Lead finish (see 1.2.5)
1.2.1 designator. Device classes marked devices meet MIL-PRF-38535 specified levels marked with appropriate designator. Device class marked devices meet MIL-PRF-38535, appendix specified levels marked with appropriate designator. dash indicates non-RHA device. 1.2.2 Device type(s). device type(s) identify circuit function follows: Device type Generic number TVP3026 Circuit function MHz, 64-bit, video interface palette
1.2.3 Device class designator. device class designator single letter identifying product assurance level follows: Device class Device requirements documentation Vendor self-certification requirements MIL-STD-883 compliant, non-JAN class level microcircuits accordance with MIL-PRF-38535, appendix Certification qualification MIL-PRF-38535 with traditional performance environment Certification qualification MIL-PRF-38535
1.2.4 Case outline(s). case outline(s) designated MIL-STD-1835 follows: Outline letter Descriptive designator CQCC2-F164 Terminals Package style Quad ceramic flat pack with non-conductive Plastic quad flat pack
figure
device outside traditional performance environment; e.g., operating temperature range -55C +125C which requires hermetic packaging.
SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
DESC FORM 193A
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1.2.5 Lead finish. lead finish specified MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class Absolute maximum ratings. Supply voltage range (VDD) +7.0 input voltage range (VIN) -0.5 Analog output short-circuit duration power supply common ground Unlimited Storage temperature range (TSTG) -65C +150C Junction temperature (TJ) +175C Case temperature seconds (HFG package) +260°C Lead temperature (1.6 (1/16 inch) from case seconds) +260C Thermal resistance, junction case JC): Case outline 0.84C/W (heat slug) Case outline 10.3C/W Thermal resistance, junction ambient JA): Case outline 36C/W Case outline 41.4C/W
Recommended operating conditions. Supply voltage range (AVDD, DVDD) Reference voltage,(VREF) High level input voltage range (VIH) Maximum level input voltage (VIL) Ambient operating free-air temperature (TA) APPLICABLE DOCUMENTS Government specification, standards, handbooks. following specification, standards, handbooks form part this drawing extent specified herein. Unless otherwise specified, issues these documents those listed issue Department Defense Index Specifications Standards (DoDISS) supplement thereto, cited solicitation. SPECIFICATION MILITARY MIL-PRF-38535 Integrated Circuits, Manufacturing, General Specification for. +4.75 +5.25 +1.1 +1.3 +2.4 +0.8 -55C +125C
Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability. Unless otherwise noted, voltages referenced GND. limits parameters specified herein shall apply over full specified range ambient temperature range -55C +125C. Unused inputs must held high low. input negative voltage rating exceeded provided that input clamp current rating observed.
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STANDARDS MILITARY MIL-STD-883 Test Methods Procedures Microelectronics. MIL-STD-973 Configuration Management. MIL-STD-1835 Microcircuit Case Outlines.
HANDBOOKS MILITARY MIL-HDBK-103 List Standard Microcircuit Drawings (SMD's). MIL-HDBK-780 Standard Microcircuit Drawings. (Unless otherwise indicated, copies specification, standards, handbooks available from Standardization Document Order Desk, Robbins Avenue, Building Philadelphia, 19111-5094.)
Order precedence. event conflict between text this drawing references cited herein, text this drawing takes precedence. Nothing this document, however, supersedes applicable laws regulations unless specific exemption been obtained. REQUIREMENTS Item requirements. individual item requirements device classes shall accordance with MIL-PRF38535 specified herein modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. individual item requirements device class shall accordance with MIL-PRF-38535, appendix non-JAN class level devices specified herein. Design, construction, physical dimensions. design, construction, physical dimensions shall specified MIL-PRF-38535 herein device classes MIL-PRF-38535, appendix herein device class 3.2.1 Case outline(s). case outline(s) shall accordance with 1.2.4 herein figure 3.2.2 Terminal connections. terminal connections shall specified figure 3.2.3 Truth table(s). truth table(s) shall specified figure 3.2.4 Logic diagram(s). logic diagram(s) shall specified figure 3.2.5 Switching waveform(s). switching waveform(s) shall specified figure 3.2.6 Clock diagram. clock diagram shall specified figure Electrical performance characteristics postirradiation parameter limits. Unless otherwise specified herein, electrical performance characteristics postirradiation parameter limits specified table shall apply over full ambient operating temperature range. Electrical test requirements. electrical test requirements shall subgroups specified table electrical tests each subgroup defined table
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Marking. part shall marked with listed herein. Marking device class shall accordance with MIL-STD-883 (see herein). addition, manufacturer's also marked listed MIL-BUL-103. Marking device classes shall accordance with MIL-PRF-38535. class devices only, date code format modified traceable date code lieu inspection date code case outline 3.5.1 Certification/compliance mark. compliance mark device class shall required MIL-STD-883 (see herein). certification mark device classes shall "QML" required MIL-PRF-38535. Certificate compliance. device classes certificate compliance shall required from QML-38535 listed manufacturer order supply requirements this drawing (see 6.6.1 herein). device class certificate compliance shall required from manufacturer order listed approved source supply MIL-HDBK-103 (see 6.6.2 herein). certificate compliance submitted DSCC-VA prior listing approved source supply this drawing shall affirm that manufacturer's product meets, device classes requirements MIL-PRF-38535 herein device class requirements MIL-PRF-38535, appendix herein. Certificate conformance. certificate conformance required device classes MIL-PRF-38535 device class MIL-PRF-38535, appendix shall provided with each microcircuits delivered this drawing. Notification change device class device class notification DSCC-VA change product (see herein) involving devices acquired this drawing required change defined MIL-STD-973. Verification review device class device class DSCC, DSCC's agent, acquiring activity retain option review manufacturer's facility applicable required documentation. Offshore documentation shall made available onshore option reviewer. 3.10 Microcircuit group assignment device class Device class devices covered this drawing shall microcircuit group number (see MIL-PRF-38535, appendix QUALITY ASSURANCE PROVISIONS Sampling inspection. device classes sampling inspection procedures shall accordance with MIL-PRF-38535 modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. device class sampling inspection procedures shall accordance with MIL-PRF-38535, appendix
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TABLE Electrical performance characteristics. Test MIL-STD-883 test method High level output voltage 3006 level output voltage 3007 Symbol Test conditions -55C +125C +4.75 +5.25 unless otherwise specified inputs affecting output under -800 inputs affecting output under test test, Group subgroups 1,2,3 Limits Unit
4.75 5.25 4.75 5.25
D(7-0),GI/O(4-0),VCLK, ENSE, PCLKOUT, MCLK, HSYNCOUT,VSYNCOUT SCLK,
1,2,3
4.75 5.25 4.75 5.25 4.75 5.25 1,2,3 1,2,3 1,2,3 4.75 5.25 1,2,3
Input current high 3010 Input current 3009 Supply current
input under test input under test Psuedo True color Direct
inputs, inputs,
inputs, inputs,
High impedance-state output current 3021 Differential input voltage Common-mode input voltage End-point linearity error (each DAC) Differential linearity error (each DAC) Gray scale error
inputs
4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25
1,2,3
inputs
1,2,3
2.85
0.25
high
1,2,3
high
1,2,3
0.25
1,2,3
footnotes table.
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TABLE Electrical performance characteristics Continued. Test MIL-STD-883 test method Output current Symbol Test conditions -55C +125C +4.75 +5.25 unless otherwise specified White level relative blank White level relative black (7.5 only) Black level relative blank (7.5 only) Blank level IOR, Blank level (with SYNC enabled) Sync level (with SYNC enabled) DAC-to-DAC matching 4.75 5.25 4.75 5.25 4.75 5.25 4.4.1c, inputs MHz, 4.4.1c, inputs MHz, Output capacitance COUT 4.4.1c, MHz, IOUT 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 1,2,3 Group subgroups 1,2,3 Limits 17.69 16.74 0.95 6.29 20.4 18.5 8.96 Unit
IOUT
4.75 5.25
Output compliance voltage Voltage reference output voltage Input capacitance
1,2,3
VREFO
1,2,3
13.0
Functional test
4.4.1b
DOTCLK frequency
9,10,11
Pixel clock frequency MCLK frequency
Internal frequency PCLKOUT frequency
9,10,11
9,10,11
frequency, pixel clock PLL, MCLK PLL, loop clock
fVCO
9,10,11
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TABLE Electrical performance characteristics Continued. Test MIL-STD-883 test method CLK0 frequency mode Clock cycle time Symbol Test conditions -55C +125C +4.75 +5.25 unless otherwise specified Group subgroups 9,10,11 Limits Unit
fVGA
4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25
tcyc
9,10,11
Delay time, RCLK LCLK Hold time, RS(3-0) valid before Hold time, RS(3-0) valid after Setup time, D(7-0) valid before Hold time, D(7-0) valid after Setup time, VGA(7-0) VGAHS, VGAVS, VGABL valid before CLK0> Hold time, VGA(7-0) VGAHS, VGAVS, VGABL valid After CLK0> Setup time, P(63-0), VGA(7-0), PSEL valid before LCLK> Hold time, P(63-0), VGA(7-0), PSEL valid after LCLK> Setup time, valid before LCLK> Hold time, valid after LCLK> footnotes table.
9,10,11
RCLK periods
tsu1
9,10,11
9,10,11
tsu2
9,10,11
9,10,11
tsu3
9,10,11
9,10,11
tsu4
9,10,11
9,10,11
tsu5
9,10,11
9,10,11
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TABLE Electrical performance characteristics Continued. Test MIL-STD-883 test method Setup time, valid before LCLK> Hold time, valid after LCLK> Pulse duration, Pulse duration, high Pulse duration, clock high Pulse duration, clock SCLK/RCLK frequency VCLK frequency Symbol Test conditions -55C +125C +4.75 +5.25 unless otherwise specified Group subgroups 9,10,11 Limits Unit
tsu6
4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
Enable time, D(7-0) valid Disable time, high D(7-0) disabled Valid time, D(7-0) valid after high Delay time, D(7-0) starting turn Delay time, SCLK high/low RCLK high/low Analog output skew
ten1
figure
4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25
9,10,11
tdis1
figure
9,10,11
figure
9,10,11
figure
9,10,11
figure
9,10,11
9,10,11
footnotes table.
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TABLE Electrical performance characteristics Continued. tests listed referenced MIL-STD-883 (e.g. IDD), utilize general test procedure MIL-STD-883 under conditions listed herein. Each input/output, applicable, shall tested specified temperature, specified limits, tests table herein. Output terminals designated shall high level logic, level logic, open, except test, where output terminals shall open. When performing these tests, current meter shall placed circuit such that current flows through meter. input terminals designated, device class only, subgroup (-55C) test limits guaranteed tested. Test conditions RS343-A video signals (unless otherwise specified): recommended using external voltage reference VREF 1.235 RSET When using internal voltage reference, RSET need adjusted order meet these limits.
Unless otherwise specified, input signals with less than rise/fall time between levels input signals VDD-1.8 VDD-0.8 with less than rise/fall time between levels. input output signals, timing reference points signal levels. Analog output loads less than D(0-7) output loads less than Unless otherwise specified, other output loads less than figures This parameter only applies when SCLK used VRAM shift clock. When SCLK used, delay much required system logic (assuming loop clock used compensate system delay). SCLK drive output capacitive load worst-case transition time between levels less than (typical ns). RCLK VCLK drive output capacitive loads with worst-case transition times between levels less than (typical ns). figure SCLK delay time RCLK depends load that signals drive. This parameter measured with VCLK RCLK load SCLK load SCLK mode, RCLK delayed from SCLK such that when RCLK connected LCLK. This parameter applies when SCLK used.
Screening. device classes screening shall accordance with MIL-PRF-38535, shall conducted devices prior qualification technology conformance inspection. device class screening shall accordance with method 5004 MIL-STD-883, shall conducted devices prior quality conformance inspection. 4.2.1 Additional criteria device class Burn-in test, method 1015 MIL-STD-883. Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1015. +125C, minimum. Interim final electrical test parameters shall specified table herein. Additional screening device class beyond requirements device class shall specified MIL-PRF-38535, appendix
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FIGURE Case outline
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Symbol
Dimensions Millimeters 4.07 3.67 -31.45 28.10 31.45 28.10 0.65 0.65 0.95
Notes
Notes
-3.17 0.25 0.30 0.16 30.95 27.90 30.95 27.90
NOTES: Controlling dimension: millimeter. Index area: notch identification mark shall located adjacent one. manufacturer's identification shall used identification mark. maximum number terminal positions.
FIGURE Case outline Continued.
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Device type Case outline Terminal number Terminal symbol PLLSEL0 DVDD DVDD VDDD VDDD Terminal number Terminal symbol DVDD GI/O0 GI/O1 GI/O2 GI/O3 GI/O4 RESET SENSE DVDD HSYNCOUT VSYNCOUT ADJUST COMP1 COMP2 AVDD
Terminal number Terminal symbol AVDD AVDD AVDD VGA0 VGA1 VGA2 VGA3 VGA4 VGA5 VGA6 VGA7 PSEL SYSHS SYSVS SYSBL VGAHS VGAVS VGABL SFLAG CLK0 CLK1 CLK2 DVDD XTAL1 XTAL2 Terminal number Terminal symbol MCLK ODD/ EVEN LCLK RCLK VCLK SCLK DVDD PLLGND PLLVDD PCLKOUT PLLVDD PLLSEL1
FIGURE Terminal connection.
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Device type Case outline Terminal number Terminal symbol PLLSEL0 DVDD DVDD VDDD VDDD Terminal number Terminal symbol DVDD GI/O0 GI/O1 GI/O2 GI/O3 GI/O4 RESET SENSE DVDD HSYNCOUT VSYNCOUT ADJUST COMP1 COMP2 AVDD
Terminal number Terminal symbol AVDD AVDD AVDD VGA0 VGA1 VGA2 VGA3 VGA4 VGA5 VGA6 VGA7 PSEL SYSHS SYSVS SYSBL VGAHS VGAVS VGABL SFLAG CLK0 CLK1 CLK2 DVDD XTAL1 XTAL2 MCLK ODD/EVEN LCLK Terminal number Terminal symbol RCLK VCLK SCLK DVDD PLLGND PLLVDD PCLKOUT PLLVDD PLLSEL1
FIGURE Terminal connection Continued.
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Direct register
Register addressed Palette/cursor write address/ index register Palette data Pixel read-mask Palette/cursor read address Cursor/overscan color write address Cursor/overscan color data Reserved Cursor/overscan color read address Reserved Direct cursor control Indexes data Cursor data Cursor-position Cursor-position Cursor-position Cursor-position
Default (Hex)
FIGURE Truth table.
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Indirect register (extended registers) Index 0x00 0x01 0x02-0x05 0x06 0x07-0x0E 0x0F 0x10-0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F-0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x00 0x00 0x00 0x80 0x98 0x07 0x06 0x00 0x00 Default Register addressed index register Reserved Silicon revision Reserved Indirect cursor control Reserved Latch control Reserved True color control Multiplex control Clock selection Reserved Palette page General control Miscellaneous control Reserved General-purpose control General-purpose data address Pixel clock data Memory clock data Loop clock data Color-key overlay Color-key overlay high Color-key Color-key high Color-key green Color-key green high Color-key blue Color-key blue high
FIGURE Truth table Continued.
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Indirect register (extended registers) Continued
Index 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0xFF
Default 0x00 0x18 0x00 0x26
Register addressed index register Color-key control MCLK/Loop clock control Sense test Test mode data remainder remainder select Software reset
FIGURE Truth table Continued.
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FIGURE Logic diagram.
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interface
FIGURE Switching waveforms.
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Video input/output
FIGURE Switching waveforms Continued.
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FIGURE Clocking diagram.
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4.2.2 Additional criteria device classes burn-in test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. burn-in test circuit shall maintained under document revision level control device manufacturer's Technology Review Board (TRB) accordance with MIL-PRF-38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1015 MILSTD-883. Interim final electrical test parameters shall specified table herein. Additional screening device class beyond requirements device class shall specified MIL-PRF-38535, appendix
Qualification inspection device classes Qualification inspection device classes shall accordance with MIL-PRF-38535. Inspections performed shall those specified MIL-PRF-38535 herein groups inspections (see 4.4.1 through 4.4.4). Conformance inspection. Technology conformance inspection classes shall accordance with MILPRF-38535 including groups inspections specified herein except where option MIL-PRF-38535 permits alternate in-line control testing. Quality conformance inspection device class shall accordance with MIL-PRF-38535, appendix specified herein. Inspections performed device class shall those specified method 5005 MIL-STD-883 herein groups inspections (see 4.4.1 through 4.4.4). 4.4.1 Group inspection. Tests shall specified table herein. device class subgroups tests shall sufficient verify truth table figure herein. test vectors used verify truth table shall, minimum, test functions each input output. possible input output logic patterns function shall guaranteed, tested, truth table figure herein. device classes subgroups shall include verifying functionality device. COUT shall measured only initial qualification after process design changes which affect capacitance. COUT shall measured between designated terminal frequency MHz. This test performed guaranteed, tested, MHz. bias under test (VBIAS) COUT test applicable pins five devices with zero failures. COUT device manufacturer qualify devices functional groups. specific functional group shall composed function types, that design, will yield same capacitance values when tested accordance with table herein. device manufacturer shall function group limit COUT tests. device manufacturer then test device functional group, limits conditions specified herein. other device functions that particular functional group shall guaranteed, tested, limits test conditions specified table herein. device manufacturers shall submit DSCC-VA device functions listed each functional group test results each device tested.
4.4.2 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.2.1 Additional criteria device class Steady-state life test conditions, method 1005 MIL-STD-883: Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1005 MILSTD-883. +125C, minimum. Test duration: 1,000 hours, except permitted method 1005 MIL-STD-883.
4.4.2.2 Additional criteria device classes steady-state life test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. test circuit shall maintained under document revision level control device manufacturer's accordance with MIL-PRF38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1005 MIL-STD-883. SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
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TABLE Electrical test requirements. Test requirements Subgroups accordance with MIL-STD-883, method 5005, table Device class Interim electrical parameters (see 4.2) Final electrical parameters (see 4.2) Group test requirements (see 4.4) Group end-point electrical parameters (see 4.4) Group end-point electrical parameters (see 4.4) Group end-point electrical parameters (see 4.4) Device class -1,2,3 7,8,9,10,11 1,2,3,4,7,8, 9,10,11 -Subgroups accordance with MIL-PRF-38535, table III)
Device class
Device class
applies subgroup applies subgroups
4.4.3 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.4 Group inspection. Group inspection required only parts intended marked radiation hardness assured (see herein). End-point electrical parameters shall specified table herein. device classes devices test vehicle shall subjected radiation hardness assured tests specified MIL-PRF-38535 level being tested. device class devices shall subjected radiation hardness assured tests specified MIL-PRF-38535, appendix level being tested. device classes must meet postirradiation end-point electrical parameter limits defined table +25C ±5C, after exposure, subgroups specified table herein. When specified purchase order contract, copy delta limits shall supplied.
PACKAGING Packaging requirements. requirements packaging shall accordance with MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class NOTES Intended use. Microcircuits conforming this drawing intended Government microcircuit applications (original equipment), design applications, logistics purposes.
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6.1.1 Replaceability. Microcircuits covered this drawing will replace same generic device covered contractor-prepared specification drawing. 6.1.2 Substitutability. Device class devices will replace device class devices. Configuration control SMD's. proposed changes existing SMD's will coordinated with users record individual documents. This coordination will accomplished accordance with MIL-STD-973 using Form 1692, Engineering Change Proposal. Record users. Military industrial users should inform Defense Supply Center Columbus when system application requires configuration control which SMD's applicable that system. DSCC will maintain record users this list will used coordination distribution changes drawings. Users drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0525. Comments. Comments this drawing should directed DSCC-VA, Columbus, Ohio 43216-5000, telephone (614) 692-0674. Abbreviations, symbols, definitions. Terminal symbol AVDD CLK0 Description Analog power. AVDD terminals must connected. separate cutout DVDD plane should made AVDD. DVDD AVDD planes should connected only single point through ferrite bead close where power enters board. clock input. CLK0 selected drive clock frequencies MHz. When using port, maximum frequency MHz. CLK0 selected latch clock video controls. (power default) clock input. CLK1 selected drive clock frequencies MHz. Dual-mode clock input. These inputs ECL-compatible inputs. Alternately, CLK2 used individual clock inputs. Programming clock selection register selects chosen configuration. These inputs selected clock device limit while mode mode. Compensation. COMP1 COMP2 provide compensation internal reference amplifier. ceramic capacitor required between COMP1 COMP2. This capacitor must close device possible avoid noise pickup. Digital power. DVDD terminals must connected digital power plane with sufficient decoupling capacitors near device. interface data bus. These terminals used transfer data register map, palette RAM, cursor RAM. Full-scale adjustment. resistor connected between this terminal ground controls full-scale range DAC's. Ground. terminals must connected. common ground plane should used. Horizontal vertical sync outputs. These outputs pipeline delayed versions selected sync inputs. Output polarity inversion independently selected using general control register bits GCR(1,0). Analog current outputs. These outputs drive 37.5 load directly (doubly terminated line), thus eliminating requirement external buffering
CLK1 CLK2,
COMP1, COMP2 DVDD ADJUST HSYNCOUT, VSYNCOUT IOR, IOG,
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SHEET
Terminal symbol LCLK
Description Latch clock input. LCLK used latch pixel-bus-input data sytem video controls. data also latched with LCLK selected. LCLK deleayed version RCLK provided that linear phase changes RCLK cause corresponding linear phase changes LCLK. Memory clock output. MCLK output independently programmable frequency synthesizer. frequency range MHz. clock output this terminal while MCLK frquency reprogrammed. Pixel clock output. PCLKOUT buffered version pixel clock output mainly test purposes. This output independent clock source selected clock selection register. Ground supplies. Decoupling capacitors should connected between PLLVDD PLLGND. PLLGND should connected system ground through ferrite bead. power supply. PLLVDD must well regulated power supply voltage. Decoupling capacitors should connected between PLLVDD PLLGND. Terminal supplies power pixel clock PLL. Terminal supplies power MCLK loop clock PLL.
MCLK
PCLKOUT
PLLGND PLLVDD
ODD/ EVEN PLLSEL0, PLLSEL1 PSEL
Overscan input. used control display custom screen borders. used, should connected GND. even field disply. ODD/ indicates even field during interlaced display EVEN cursor operation. Pixel clock frequency selection. Selects among fixed frequencies programmed frequency pixel clock PLL. Port select. PSEL provides capability switching between direct color true color overlay. Multiple true color overlay windows displayed using PSEL control. Since PSEL sampled with LCLK, granularity switching depends number pixels loaded LCLK. PSEL used, should connected GND. Pixel input port. port used various modes. Unused terminals should allowed float. Reference Clock output. Voltage reference DACs. internal voltage reference nominally 1.235 provided, which requires external ceramic capacitor between analog GND. However, internal reference voltagecan overdriven externally supplied reference voltage. Master reset. registers assume their default state after reset. default state mode (CLK0 latching data video controls). Read strobe input. logic this terminal initiates read from register map. Read transfer data enabled onto when low.
P63-P0 RCLK
SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
DESC FORM 193A
REVISION LEVEL
5962-96758
SHEET
Terminal symbol RS3-RS0 SCLK
Description Register select inputs. These terminals specify location direct register that acessed. Shift clock output. SCLK gated version loop clock output gated during blank. SCLK used drive VRAM shift clock directly. This intended designs which graphics controller does supply VRAM shift clock. Test mode comparator output signal. This terminal more output analog levels above internal comparator reference Split shift register transfer flag. high pulse this terminal during blank passed directly SCLK terminal. This operation available meet special serial clocking requirements some VRAM devices. SFLAG used, SFLAG should connected GND. System blank input. active low. This should selected modes other than mode This signal pipeline delayed before being passed DACs. System horizontal vertical sync inputs. These signals should selected modes other than mode These siganals pipelined delayed each inverted before being passed HSYNCOUT VSYNCOUT terminals. General control register bits GCR(1,0) control parity inversion. used generate sync level green current, must active input device. Progammable auxiliary clock output. VCLK derived from internal clock using programmable divide ratio does utilize loop clock synchronization. Since pixel data video controls always referenced RCLK LCLK CLK0), VCLK frame buffer interface video timing recommended. blank input. active low. This should selected when mode (CLK0 latching data video controls). pipeline delayed before being passed DACs. horizontal vertical sync inputs. These signals should used when mode (CLK0 latching data video controls). These signals pipelined delayed each inverted before being passed HSYNCOUT VSYNCOUT terminals. General control register bits GCR(1,0) control polarity inversion. used generate sync level green current output, VGAHS VGAVS must active input device. port. This selected pixel input modes, does allow mutiplexing. Write strobe input. logic this terminal initiates write register map. Write transfer data latched from D(7-0) with rising edge Connection quartz crystal resonator reference frequency synthesis PLLs. XTA2 used reference clock input, which case XTAL1 left unconnected. resolution selection. This terminal used select data width bits) DACs provided downward compatibility.
SFLAG
VCLK
VGAHS, VGAVS
VGA7 VGA0 XTAL1, XTAL2
SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
DESC FORM 193A
REVISION LEVEL
5962-96758
SHEET
Terminal symbol COUT
Ground zero voltage potential Quiescent supply current Input current Input current high Ambient temperature Positive supply voltage Input terminal ground capacitance Output terminal ground capacitance Negative input clamp voltage
Description
Sources supply. 6.6.1 Sources supply device classes Sources supply device classes listed QML-38535. vendors listed QML-38535 have submitted certificate compliance (see herein) DSCC-VA have agreed this drawing. 6.6.2 Approved sources supply device class Approved sources supply class listed MIL-HDBK-103. vendors listed MIL-HDBK-103 have agreed this drawing certificate compliance (see herein) been submitted accepted DSCC-VA.
SIZE STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
DESC FORM 193A
REVISION LEVEL
5962-96758
SHEET
STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN DATE: 96-08-16 Approved sources supply 5962-96758 listed below immediate acquisition only shall added MIL-HDBK-103 QML-38535 during next revision. MIL-HDBK-103 QML-38535 will revised include addition deletion sources. vendors listed below have agreed this drawing certificate compliance been submitted accepted DSCC-VA. This bulletin superseded next dated revision MIL-HDBK103 QML-38535.
Standard microcircuit drawing 5962-9675801NYB 5962-9675801QXA
Vendor CAGE number 01295 01295
Vendor similar TVP3026-175MPCE TVP3026-175MHFGB
lead finish shown each representing hermetic package most readily available from manufacturer listed that part. device manufacturers listed herein authorized supply alternate lead finishes "A", "B", their discretion. Contact listed approved source supply further information. Caution. this number item acquisition. Items acquired this number satisfy performance requirements this drawing.
Vendor CAGE number 01295
Vendor name address Texas Instruments Incorporated 13500 Central Expressway P.O. 655303 Dallas, 75265 Point contact: I-20 1788 Midland, 79711-0448
information contained herein disseminated convenience only Government assumes liability whatsoever inaccuracies information bulletin.

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