SDRAM SMALL-OUTLINE DIMM 200-pin, small-outline, dual in-line mem

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SDRAM SMALL-OUTLINE DIMM 200-pin, small-outline, dual in-line mem

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128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
SDRAM SMALL-OUTLINE DIMM
200-pin, small-outline, dual in-line memory module (SODIMM) ECC, 1-bit error detection correction Fast data transfer rates: PC1600, PC2100, PC2700 Utilizes MT/s, MT/s, MT/s SDRAM components MT9VDDT1672PH 72); MT9VDDT3272PH 72); MT18VDDT6472PH 72); MT9VDDT6472PH stacked); MT18VDDT12872PH stacked) VDDQ +2.5V VDDSPD +2.3V +3.6V 2.5V (SSTL_2 compatible) Commands entered each positive edge edge-aligned with data READs; centeraligned with data WRITEs
OPTIONS MARKING
MT9VDDT1672PH(I) 128MB, MT9VDDT3272PH(I) 256MB, MT18VDDT6472PH(I) 512MB, MT9VDDT6472PH(I) 512MB, MT18VDDT12872PH(I)
lastest data sheet, please refer site: www.micron.com/moduleds.
Figure 200-Pin SODIMM (MO-224)
Standard: 1.50in. (38.10mm)
Profile: 1.25in. (31.75mm)
Operating Temperature Range Commercial (0°C +70°C) Industrial (-40°C +85°C) Package 200-pin SODIMM (standard) 200-pin SODIMM (lead-free) Clock Frequency/CAS Latency 6ns, (333 MT/s) 2.51 7.5ns, (266 MT/s)/ 7.5ns, (266 MT/s)/ 7.5ns, (266 MT/s)/ 10ns, (200 MT/s)/ Standard: 1.5in. (38.10mm) Low-Profile: 1.25in. (31.75mm)
NOTE:
None -3352 -262 -26A -265 -202
Device (READ) Latency. -335 -262 speed grades available singlerank module only. Consult Micron availability; industrial temperature option available -265 speed only.
Internal, pipelined double data rate (DDR) architecture; data accesses clock cycle Four internal device banks concurrent operation Programmable burst lengths: Auto precharge option Auto Refresh Self Refresh Modes 15.625µs (MT9VDDT1672PH), 7.8125µs (MT9VDDT3272PH, MT18VDDT6472PH, MT9VDDT6472PH, MT18VDDT12872PH) maximum average periodic refresh interval Serial Presence Detect (SPD) with EEPROM Programmable READ latency Gold edge contacts Bidirectional data strobe (DQS) transmitted/received with data-i.e., source-synchronous data capture Differential clock inputs
Table
Address Table
MT9VDDT1672PH MT9VDDT3272PH MT18VDDT6472PH MT9VDDT6472PH MT18VDDT12872PH Refresh Count (A0-A11) (A0-A12) (A0-A12) (A0-A12) (A0-A12) Addressing (BA0, BA1) (BA0, BA1) (BA0, BA1) (BA0, BA1) (BA0, BA1) DeviceBankAddressing Base Device Configuration (A0-A9) (A0-A9) (A0-A9) (A0-A9, A11) (A0-A9, A11) Column Addressing (S0#) (S0#) (S0#, S1#) (S0#) (S0#, S1#) Module Rank Addressing
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
©2003 Micron Technology, Inc. rights reserved.
PRODUCTS SPECIFICATIONS DISCUSSED HEREIN SUBJECT CHANGE MICRON WITHOUT NOTICE.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Part Numbers Timing Parameters
MODULE DENSITY 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB CONFIGURATION MODULE BANDWIDTH GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s MEMORY CLOCK/ DATA RATE 6ns, MT/s 6ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 10ns, MT/s 10ns, MT/s 6ns, MT/s 6ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 10ns, MT/s 10ns, MT/s 6ns, MT/s 6ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 10ns, MT/s 10ns, MT/s 6ns, MT/s 6ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 10ns, MT/s 10ns, MT/s 6ns, MT/s 6ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 10ns, MT/s 10ns, MT/s CLOCK LATENCY tRCD tRP) 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2
PART NUMBER MT9VDDT1672PHG-335_ MT9VDDT1672PHY-335_ MT9VDDT1672PHG-262_ MT9VDDT1672PHY-262_ MT9VDDT1672PHG-26A_ MT9VDDT1672PHY-26A_ MT9VDDT1672PH(I)G-265_ MT9VDDT1672PH(I)Y-265_ MT9VDDT1672PHG-202_ MT9VDDT1672PHY-202_ MT9VDDT3272PHG-335_ MT9VDDT3272PHY-335_ MT9VDDT3272PHG-262_ MT9VDDT3272PHY-262_ MT9VDDT3272PHG-26A_ MT9VDDT3272PHY-26A_ MT9VDDT3272PH(I)G-265_ MT9VDDT3272PH(I)Y-265_ MT9VDDT3272PHG-202_ MT9VDDT3272PHY-202_ MT18VDDT6472PHG-335_ MT18VDDT6472PHY-335_ MT18VDDT6472PHG-262_ MT18VDDT6472PHY-262_ MT18VDDT6472PHG-26A_ MT18VDDT6472PHY-26A_ MT18VDDT6472PH(I)G-265_ MT18VDDT6472PH(I)Y-265_ MT18VDDT6472PHG-202_ MT18VDDT6472PHY-202_ MT9VDDT6472PHG-335_ MT9VDDT6472PHY-335_ MT9VDDT6472PHG-262_ MT9VDDT6472PHY-262_ MT9VDDT6472PHG-26A_ MT9VDDT6472PHY-26A_ MT9VDDT6472PH(I)G-265_ MT9VDDT6472PH(I)Y-265_ MT9VDDT6472PHG-202_ MT9VDDT6472PHY-202_ MT18VDDT12872PHG-335_ MT18VDDT12872PHY-335_ MT18VDDT12872PHG-262_ MT18VDDT12872PHY-262_ MT18VDDT12872PHG-26A_ MT18VDDT12872PHY-26A_ MT18VDDT12872PH(I)G-265_ MT18VDDT12872PH(I)Y-265_ MT18VDDT12872PHG-202_ MT18VDDT12872PHY-202_
NOTE:
part numbers with two-place code (not shown), designating component revisions. Consult factory current revision codes. Example: MT9VDDT3272PHG-265A1.
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Assignment (200-Pin SODIMM Front)
DQ19 DQ24 DQ25 DQS3 DQ26 DQ27 DQS8 CKE1 NC/A12 DQ42 DQ43 DQ48 A10/AP DQ49 DQS6 DQ50 DQ51 DQ32 DQ56 DQ33 DQ57 DQS4 DQS7 DQ34 DQ58 DQ35 DQ59 DQ40 DQ41 DQS5 VDDSPD
Table
Assignment (200-Pin SODIMM Back)
DQ23 DQ28 DQ29 DQ30 DQ31 CKE0 RAS# CAS# DQ36 DQ37 DQ38 DQ39 DQ44 DQ45 DQ46 DQ47 DQ52 DQ53 DQ54 DQ55 DQ60 DQ61 DQ62 DQ63
SYMBOL SYMBOL SYMBOL SYMBOL
NOTE:
SYMBOL SYMBOL SYMBOL SYMBOL VREF DQ12 DQ13 DQ14 DQ15 DQ20 DQ21 DQ22
VREF DQS0 DQS1 DQ10 DQ11 CK0# DQ16 DQ17 DQS2 DQ18
Connect MT9VDDT1672PH module, other modules.
Figure Module Layout
Standard: 1.50in. (38.10mm)
Front View
Profile: 1.25 (31.75mm)
Front View
(all pins)
(all pins)
Back View Back View
(all pins)
(all even pins)
Indicates VDDQ
Indicates
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Descriptions
SYMBOL WE#, CAS#, RAS# CK0, CK0# TYPE Input Input DESCRIPTION Command Inputs: RAS#, CAS#, (along with define command being entered. Clock: differential clock inputs distributed through on-board devices. address control input signals sampled crossing positive edge negative edge CK#. Output data DQS) referenced crossings CK#. Clock Enable: HIGH activates deactivates internal clock, input buffers.and output drivers. Taking provides PRECHARGE POWER- DOWN SELF REFRESH operations (all device banks idle), ACTIVE POWER-DOWN (row ACTIVE device bank). synchronous POWER-DOWN entry exit, SELF REFRESH entry. asynchronous SELF REFRESH exit disabling outputs. must maintained HIGH throughout read write accesses. Input buffers (excluding CKE) disabled during POWER-DOWN. Input buffers (excluding CKE) disabled during SELF REFRESH. SSTL_2 input will detect LVCMOS level after applied. Chip Select: enables (registered LOW) disables (registered HIGH) command decoder. com- mands masked when registered HIGH. considered part command code. Bank Address: BA0, define which device bank ACTIVE, READ, WRITE, PRECHARGE command being applied. Address Inputs: A0-A11/A12 provide address ACTIVE commands, column address, auto precharge (A10) READ/WRITE commands, select location memory array respective device bank. sampled during PRECHARGE command determines whether PRECHARGE applies device bank (A10 LOW, device bank selected BA0, BA1) device banks (A10 HIGH). address inputs also provide op-code during MODE REGISTER command. define which mode register (mode register extended mode register) loaded during LOAD MODE REGISTER command. Data Strobe: Output with READ data, input with WRITE data. edge-aligned with READ data, centered WRITE data. Used capture data. Data Mask: input mask signal write data. Input data masked when sampled HIGH along with that input data during WRITE access. sampled both edges DQS. Although pins input-only, loading designed match that pins. Check Bits: 1-bit error detection correction. Refer Assignment Tables page number symbol correlation. NUMBERS 118, 119,
CKE0, CKE1
Input
121,
S0#,
Input
117, (A12), 100, 101,102, 105, 106, 107, 108, 109, 110, 111, 112,
BA0, A0-A11 MT9VDDT1672PH A0-A12 MT9VDDT3272PH, MT18VDDT6472PH, MT9VDDT6472PH, MT18VDDT12872PH
Input Input
133, 147,169, 134, 148, 170,
DQS0-DQS8
Input/ Output Input
DM0-DM8
CB0-CB7
Input/ Output
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Descriptions
SYMBOL DQ0-DQ63 TYPE Input/ Output Data I/Os: Data bus. DESCRIPTION Refer Assignment Tables page number symbol correlation. NUMBERS 127, 128, 129, 130, 135, 136, 139, 140, 141, 142, 145, 146, 151, 152, 153, 154, 163, 164, 165, 166, 171, 172, 175, 176, 177, 181, 182, 187, 188, 189, 194, 196,
SA0-SA2
Input Input Input/ Output Input Supply
113, 114, 131, 132, 143, 144, 155, 156, 157, 167, 168, 179, 180, 191, 103, 104, 125, 126, 137, 138, 149, 150, 159, 161, 162, 173, 174, 185, (MT9VDDT1672PH), 123, 124, 158, 160,
VREF
Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module. Presence-Detect Address Inputs: These pins used configure presence-detect device. Serial Presence-Detect Data: bidirectional used transfer addresses data into presence-detect portion module. SSTL_2 reference voltage. Power Supply: +2.5V ±0.2V.
Supply
Ground.
VDDSPD
Supply
Serial EEPROM positive power supply: +2.3V +3.6V. Connect: These pins should left unconnected.
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Figure Functional Block Diagram MT9VDDT1672PH, MT9VDDT3272PH, MT9VDDT6472PH
DQS0 DQS1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 BA0, A0-A113 A0-A124 RAS# CAS# CKE0 BA0, BA1: SDRAMS A0-A11: SDRAMS A0-A12: SDRMAS RAS#: SDRAMS CAS#: SDRAMS CKE0: SDRAMS WE#: SDRAMS VREF VDDSPD SDRAMS SDRAMS SDRAMS CK0# SDRAM SDRAM SDRAM SDRAM SDRAM DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
SERIAL
NOTE:
resistor values unless otherwise specified. industry standard, Micron modules utilize various component speed grades, referenced module part numbering guide www.micron.com/numberguide. MT9VDDT1672PH MT9VDDT3272PH, MT9VDDT6472PH
SDRAMs MT46V16M8TG MT9VDDT1672PH SDRAMs MT46V32M8TG MT9VDDT3272PH SDRAMs MT46V64M8TG MT9VDDT6472PH Contact Micron information modules.
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Figure Functional Block Diagram MT18VDDT6472PH MT18VDDT12872PH
DQS0 DQS1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 BA0, A0-A12 RAS# CAS# CKE0 CKE1 CK0# SDRAM SDRAM SDRAM SDRAM SDRAM DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
SERIAL
BA0, BA1: SDRAMs A0-A12: SDRAMs RAS#: SDRAMs CAS#: SDRAMs CKE0: SDRAMs U1b-U9b CKE1: SDRAMs U1t-U9t WE#: SDRAMs VDDSPD VREF
SDRAMs SDRAMs SDRAMs
NOTE:
resistor values unless otherwise specified. bottom portion stacked SDRAM, portion stacked SDRAM. industry standard, Micron modules utilize various component speed grades, referenced module part numbering guide www.micron.com/numberguide.
SDRAMs MT46V32M8TG MT18VDDT6472PH SDRAMs MT46V64M8TG MT18VDDT12872PH Contact Micron information modules.
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
General Description
Micron MT9VDDT1672PH, MT9VDDT3272PH, MT18VDDT6472PH, MT9VDDT6472PH, MT18VDDT12872PH high-speed CMOS, dynamic random-access, 128MB, 256MB, 512MB, memory modules organized (ECC) configuration. SDRAM modules internally configured quad-bank SDRAM devices. SDRAM modules double data rate architecture achieve high-speed operation. double data rate architecture essentially 2n-prefetch architecture with interface designed transfer data words clock cycle pins. single read write access SDRAM module effectively consists single 2n-bit wide, one-clock-cycle data transfer internal DRAM core corresponding n-bit wide, one-half-clock-cycle data transfers pins. bidirectional data strobe (DQS) transmitted externally, along with data, data capture receiver. intermittent strobe transmitted SDRAM device during READs memory controller during WRITEs. edgealigned with data READs center-aligned with data WRITEs. SDRAM modules operate from differential clock inputs CK#); crossing going HIGH going will referred positive edge Commands (address control signals) registered every positive edge Input data registered both edges DQS, output data referenced both edges DQS, well both edges phase-lock loop (PLL) device module used redrive differential clock signals SDRAM devices minimize system clock loading. Read write accesses SDRAM modules burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed (BA0, select device bank; A0-A11 select device module MT9VDDT1672PH A0-A12 select MT9VDDT3272PH, device modules MT18VDDT6472PH, MT9VDDT6472PH, MT18VDDT12872PH). address bits registered coincident with READ WRITE command used select device bank starting device column location burst access. SDRAM modules provide programmable read write burst lengths locations. auto precharge function enabled provide self-timed precharge that initiated burst access. pipelined, multibank architecture SDRAM modules allows concurrent operation, thereby providing high effective bandwidth hiding precharge activation time. auto refresh mode provided, along with power-saving power-down mode. inputs compatible with JEDEC Standard SSTL_2. outputs SSTL_2, Class compatible. more information regarding SDRAM operation, refer 128Mb, 256Mb, 512Mb SDRAM data sheets.
Operation
phase-lock loop (PLL) module used redrive differential clock signals SDRAM devices minimize system clock loading.
Serial Presence-Detect Operation
These SDRAM modules incorporate serial presence-detect (SPD). function implemented using 2,048-bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters. remaining bytes storage available customer. System READ/ WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals, together with SA(2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) tied ground module, permanently disabling hardware write protect.
Mode Register Definition
mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency operating mode, shown Mode Register Diagram. mode register programmed MODE REGISTER command (with will retain stored information until programmed again device loses power (except which self-clearing).
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Reprogramming mode register will alter contents memory, provided performed correctly. mode register must loaded (reloaded) when device banks idle bursts progress, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation. Mode register bits A0-A2 specify burst length, specifies type burst (sequential interleaved), A4-A6 specify latency, A7-A11 (for MT9VDDT1672PH) A7-A12 (for MT9VDDT3272PH, MT18VDDT6472PH, MT9VDDT6472PH, MT18VDDT12872PH) specify operating mode.
Read Latency
READ latency delay, clock cycles, between registration READ command availability first output data. latency clocks, shown Figure Latency Diagram, page
Figure Mode Register Definition Diagram
MT9VDDT1672PH Module Address
Address
Burst Length
Read write accesses SDRAM burst oriented, with burst length being programmable, shown Mode Register Diagram. burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached. block uniquely selected A1-Ai when burst length two, A2-Ai when burst length four A3-Ai when burst length eight (where most significant column address given configuration; note Table Burst Definition Table, page 10). remaining (least significant) address bit(s) (are) used select starting location within block. programmed burst length applies both read write bursts.
Operating Mode Latency Burst Length (BA1and BA0) must select base mode register (vs. extended mode register).
Mode Register (Mx)
MT9VDDT3272PH; MT18VDDT6472PH; MT9VDDT6472PH, MT18VDDT12872PH Module Address
Address
Operating Mode (BA1 BA0) must select base mode register (vs. extended mode register).
Latency Burst Length
Mode Register (Mx)
Burst Length Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved Reserved
Burst Type
Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Table Burst Definition Table, page
M6-M0 Valid Valid
Operating Mode Normal Operation Normal Operation/Reset other states reserved
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Burst Definition Table
STARTING COLUMN ADDRESS ORDER ACCESSES WITHIN BURST TYPE TYPE SEQUENTIAL INTERLEAVED 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
Figure Latency Diagram
COMMAND
READ
BURST LENGTH
COMMAND
READ
Burst Length cases shown Shown with nominal tAC, tDQSCK, tDQSQ TRANSITIONING DATA DON'T CARE
NOTE:
burst length two, A1-Ai select two- dataelement block; selects first access within block. burst length four, A2-Ai select four- dataelement block; A0-A1 select first access within block. burst length eight, A3-Ai select eightdata-element block; A0-A2 select first access within block. Whenever boundary block reached within given sequence above, following access wraps within block. MT9VDDT1672PH, MT9VDDT3272PH, MT18VDDT6472PH MT9VDDT6472PH, MT18VDDT12872PH
READ command registered clock edge latency clocks, data will available nominally coincident with clock edge Table Latency (CL) Table, page indicates operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result.
Operating Mode
normal operating mode selected issuing MODE REGISTER command with bits A7-A11 (for MT9VDDT1672PH), A7-A12 (for MT9VDDT3272PH, MT18VDDT6472PH, MT9VDDT6472PH, MT18VDDT12872PH) each zero, bits A0-A6 desired values. reset initiated issuing MODE REGISTER command with bits A9-A11 (for MT9VDDT1672PH), A9-A12 (for MT9VDDT3272PH, MT18VDDT6472PH, MT9VDDT6472PH, MT18VDDT12872PH) each zero, one, bits A0-A6 desired values. Although required Micron device, JEDEC specifications recommend when LOAD MODE REGISTER command issued reset DLL, should always followed LOAD MODE REGISTER command select normal operating mode.
Table
Latency (CL) Table
ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ)
SPEED -335 -262 -26A -265 -202
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
other combinations values A7-A11, reserved future and/or test modes. Test modes reserved states should used because unknown operation incompatibility with future versions result.
Figure Extended Mode Register Definition Diagram
MT9VDDT1672PH Module Address
Address
Extended Mode Register
extended mode register controls functions beyond those controlled mode register; these additional functions enable/disable output drive strength. These functions controlled bits shown Extended Mode Register Definition Diagram. extended mode register programmed LOAD MODE REGISTER command mode register (with will retain stored information until programmed again device loses power. enabling should always followed LOAD MODE REGISTER command mode register (BA0, /BA1 both low) reset DLL. extended mode register must loaded when device banks idle bursts progress, controller must wait specified time before initiating subsequent operation. Violating either these requirements could result unspecified operation.
Operating Mode
Extended Mode Register (Ex)
MT9VDDT3272PH; MT18VDDT6472PH; MT9VDDT6472PH, MT18VDDT12872PH Module Address
Address
Operating Mode
Extended Mode Register (Ex)
Valid
Enable Disable Drive Strength Normal
Operating Mode Reserved Reserved
Enable/Disable
must enabled normal operation. enable required during power-up initialization upon returning normal operation after having disabled purpose debug evaluation. (When device exits self refresh mode, enabled automatically.) time enabled, clock cycles must occur before READ command issued.
NOTE:
(MT9VDDT3272PH), (MT9VDDT6472PH, MT18VDDT6472PH, MT9VDDT6472PH, MT18VDDT12872PH) (BA1 BA0) must select Extended Mode Register (vs. base Mode Register). QFC# option supported.
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Commands
Table Commands Truth Table, Table Operation Truth Table, provide general reference available commands. more detailed description commands operations, refer Micron 128Mb, 256Mb, 512Mb SDRAM component data sheets.
Table
Commands Truth Table
RAS# CAS# ADDR Bank/Row Bank/Col Bank/Col Code Op-Code NOTES
HIGH commands shown except SELF REFRESH NAME (FUNCTION) DESELECT (NOP) OPERATION (NOP) ACTIVE (Select device bank activate row) READ (Select device bank column, start READ burst) WRITE (Select device bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate device bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER
NOTE:
DESELECT functionally interchangeable. BA0-BA1 provide device bank address A0-A11 (MT9VDDT1672PH) A0-A12 (MT9VDDT3272PH, MT9VDDT6472PH, MT18VDDT6472PH, MT18VDDT12872PH) provide address. BA0-BA1 provide device bank address; A0-A8 (MT9VDDT1672PH) A0-A9 (MT9VDDT3272PH, MT9VDDT6472PH, MT18VDDT6472PH, MT18VDDT12872PH), provide column address; HIGH enables auto precharge feature (nonpersistent), disables auto precharge feature. Applies only read bursts with auto precharge disabled; this command undefined (and should used) READ bursts with auto precharge enabled WRITE bursts. LOW: BA0-BA1 determine which device bank precharged. HIGH: device banks precharged BA0- "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. BA0-BA1 select either mode register extended mode register (BA0 select mode register; select extended mode register; other combinations BA0-BA1 reserved). A0-A11 (MT9VDDT1672PH) A0-A12 (MT9VDDT3272PH, MT18VDDT6472PH, MT9VDDT6472PH, MT18VDDT12872PH) provide op-code written selected mode register.
Table
Operation Truth Table
Valid
Used mask write data; provided coincident with corresponding data NAME (FUNCTION) Write Enable Write Inhibit
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Absolute Maximum Ratings
Stresses greater than those listed cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operaVDD Supply Voltage Relative +3.6V VDDQ Supply Voltage Relative +3.6V VREF Inputs Voltage Relative +3.6V Pins Voltage Relative -0.5V VddQ +0.5V Operating Temperature, (commercial). .0°C +70°C (industrial) .-40°C +85°C tional sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Storage Temperature (plastic) -55°C +150°C Power Dissipation Single-Rank Module Dual-Rank Module Short Circuit Output Current. 50mA
Table Electrical Characteristics Operating Conditions (MT9VDDT1672PH, MT9VDDT3272PH, MT9VDDT6472PH)
Notes: 1-5, notes appear pages 24-27; +70°C PARAMETER/CONDITION SYMBOL VDDQ VREF VIH(DC) VIL(DC) 0.49 VDDQ VREF 0.04 VREF 0.15 -0.3 0.51 VDDQ VREF 0.04 VREF 0.15 UNITS NOTES
Supply Voltage
Supply Voltage Reference Voltage Termination Voltage (system) Input High (Logic Voltage Input (Logic Voltage INPUT LEAKAGE CURRENT input VDD, VREF 1.35V (All other pins under test
Command/Address, RAS#, CAS#, WE#, CKE,
-16.8 16.8
OUTPUT LEAKAGE CURRENT DQS, (DQs disabled; VOUT VDDQ) OUTPUT LEVELS: High Current (VOUT VDDQ-0.373V, minimum VREF, minimum VTT) Current (VOUT 0.373V, maximum VREF, maximum VTT)
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Electrical Characteristics Operating Conditions (MT18VDDT6472PH, MT18VDDT12872PH)
Notes: 1-5, notes appear pages 24-27; +70°C; VDDQ +2.5V ±0.2V PARAMETER/CONDITION Supply Voltage Supply Voltage Reference Voltage Termination Voltage (system) Input High (Logic Voltage Input (Logic Voltage INPUT LEAKAGE CURRENT input VDD, VREF 1.35V (All other pins under test SYMBOL VDDQ VREF VIH(DC) VIL(DC) UNITS NOTES
OUTPUT LEAKAGE CURRENT disabled; VOUT VDDQ) OUTPUT LEVELS: High Current (VOUT VDDQ-0.373V, minimum VREF, minimum VTT) Current (VOUT 0.373V, maximum VREF, maximum VTT)
Command/Address, RAS#, CAS#, WE#, CK,CK# DQS,
0.49 0.51 VDDQ VDDQ VREF 0.04 VREF 0.04 VREF 0.15 -0.3 VREF 0.15
-16.8 16.8
Table Input Operating Conditions
Notes: 1-5, notes appear pages 24-27; +70°C; VDDQ +2.5V ±0.2V PARAMETER/CONDITION Input High (Logic Voltage Input (Logic Voltage Reference Voltage SYMBOL VIH(AC) VIL(AC) VREF(AC) VREF 0.310 0.49 VDDQ VREF 0.310 0.51 VDDQ UNITS NOTES
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Specifications Conditions (MT9VDDT1672PH)
SDRAM components only; Notes: 1-5, notes appear pages 24-27; +70°C; VDDQ +2.5V ±0.2V PARAMETER/CONDITION OPERATING CURRENT: device bank; Active-Precharge; (MIN); (MIN); inputs changing once clock cyle; Address control inputs changing once every clock cycles OPERATING CURRENT: device bank; Active-ReadPrecharge; Burst (MIN); (MIN); IOUT 0mA; Address control inputs changing once clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: device banks idle; Power-down mode; (MIN); (LOW) IDLE STANDBY CURRENT: HIGH; device banks idle; MIN; HIGH; Address other control inputs changing once clock cycle. VREF DQS, ACTIVE POWER-DOWN STANDBY CURRENT: device bank active; Power-down mode; (MIN); ACTIVE STANDBY CURRENT: HIGH; HIGH; device bank; Active-Precharge; (MAX); (MIN); inputs changing twice clock cycle; Address other control inputs changing once clock cycle OPERATING CURRENT: Burst Reads; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); IOUT OPERATING CURRENT: Burst Writes; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); inputs changing twice clock cycle AUTO REFRESH CURRENT tRFC (MIN)
SYMBOL IDD0
-335 1,125
-26A/-265
-202
UNITS NOTES
IDD1
1,215
1,080
1,080
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
1,260
1,125
1,125
IDD4W
1,260
1,080
1,080
IDD5 IDD5A IDD6 IDD7
2,385 3,195
1,980 2,925
1,980 2,925
15.625µs
SELF REFRESH CURRENT: 0.2V OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge with, (MIN); (MIN); Address control inputs change only during Active READ, WRITE commands
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Specifications Conditions (MT9VDDT3272PH)
SDRAM components only; Notes: 1-5, notes appear pages 24-27 +70°C; VDDQ +2.5V ±0.2V PARAMETER/CONDITION OPERATING CURRENT: device bank; Active-Precharge; (MIN); (MIN); inputs changing once clock cyle; Address control inputs changing once every clock cycles OPERATING CURRENT: device bank; Active-ReadPrecharge; Burst (MIN); (MIN); IOUT 0mA; Address control inputs changing once clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: device banks idle; Power-down mode; (MIN); (LOW) IDLE STANDBY CURRENT: HIGH; device banks idle; MIN; HIGH; Address other control inputs changing once clock cycle. VREF DQS, ACTIVE POWER-DOWN STANDBY CURRENT: device bank active; Power-down mode; (MIN); ACTIVE STANDBY CURRENT: HIGH; HIGH; device bank; Active-Precharge; (MAX); (MIN); inputs changing twice clock cycle; Address other control inputs changing once clock cycle OPERATING CURRENT: Burst Reads; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); IOUT OPERATING CURRENT: Burst Writes; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); inputs changing twice clock cycle AUTO REFRESH CURRENT tRFC (MIN)
SYMBOL IDD0
-335 1,125
-26A/-265
-202 1,080
UNITS
NOTES
IDD1
1,530
1,305
1,395
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
1,575
1,350
1,575
IDD4W
1,395
1,215
1,710
IDD5 IDD5A IDD6 IDD7
2,295 3,645
2,115 3,150
2,205 3,285
7.8125µs
SELF REFRESH CURRENT: 0.2V OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge with, (MIN); (MIN); Address control inputs change only during Active READ, WRITE commands
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Specifications Conditions (MT9VDDT6472PH)
SDRAM components only; Notes: 1-5, notes appear pages 24-27; +70°C; VDDQ +2.5V ±0.2V PARAMETER/CONDITION OPERATING CURRENT: device bank; Active-Precharge; (MIN); (MIN); inputs changing once clock cyle; Address control inputs changing once every clock cycles OPERATING CURRENT: device bank; Active-Read-Precharge; Burst (MIN); (MIN); IOUT 0mA; Address control inputs changing once clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: device banks idle; Power-down mode; (MIN); (LOW)
SYMBOL IDD0
-335 1,170
-26A/-265 1,305
-202 1,305
UNITS
NOTES
IDD1
1,440
1,305
1,305
IDD2P IDD2F
IDLE STANDBY CURRENT: HIGH; device banks idle; MIN; HIGH; Address other control inputs changing once clock cycle. VREF DQS, ACTIVE POWER-DOWN STANDBY CURRENT: device bank active; Power-down mode; (MIN); ACTIVE STANDBY CURRENT: HIGH; HIGH; device bank; Active-Precharge; (MAX); (MIN); inputs changing twice clock cycle; Address other control inputs changing once clock cycle OPERATING CURRENT: Burst Reads; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); IOUT OPERATING CURRENT: Burst Writes; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); inputs changing twice clock cycle AUTO REFRESH CURRENT tRFC (MIN)
IDD3P IDD3N
IDD4R
1,485
1,305
1,305
IDD4W
1,395
1,215
1,215
IDD5 IDD5A IDD6 IDD7
2,610 3,645
2,520 3,150
2,520 3,150
7.8125µs
SELF REFRESH CURRENT: 0.2V OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge with, (MIN); (MIN); Address control inputs change only during Active READ, WRITE commands
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Specifications Conditions (MT18VDDT6472PH)
SDRAM components only; Notes: 1-5, notes appear pages 24-27; +70°C; VDDQ +2.5V ±0.2V PARAMETER/CONDITION OPERATING CURRENT: device bank; Active-Precharge; (MIN); (MIN); inputs changing once clock cyle; Address control inputs changing once every clock cycles OPERATING CURRENT: device bank; Active-Read-Precharge; Burst (MIN); (MIN); IOUT 0mA; Address control inputs changing once clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: device banks idle; Power-down mode; (MIN); (LOW)
SYMBOL IDD0
-26A/-265
UNITS
NOTES
IDD1a
1,341
IDD2Pb IDD2Fb
IDLE STANDBY CURRENT: HIGH; device banks idle; MIN; HIGH; Address other control inputs changing once clock cycle. VREF DQS, ACTIVE POWER-DOWN STANDBY CURRENT: device bank active; Power-down mode; (MIN); ACTIVE STANDBY CURRENT: HIGH; HIGH; device bank; Active-Precharge; (MAX); (MIN); inputs changing twice clock cycle; Address other control inputs changing once clock cycle OPERATING CURRENT: Burst Reads; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); IOUT OPERATING CURRENT: Burst Writes; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); inputs changing twice clock cycle AUTO REFRESH CURRENT tRFC (MIN)
IDD3Pb IDD3Nb
IDD4Ra
1,386
IDD4Wa
1,251
IDD5b IDD5Ab IDD6b
DD7a
4,230 3,186
7.8125µs
SELF REFRESH CURRENT: 0.2V OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge with, (MIN); (MIN); Address control inputs change only during Active READ, WRITE commands
NOTE:
Value calculated module rank this operating condition, other module ranks IDD2P (CKE LOW) Mode. Value calculated reflects module ranks this operating condition.
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Specifications Conditions (MT18VDDT12872PH)
SDRAM components only; Notes: 1-5, notes appear pages 24-27; +70°C; VDDQ +2.5V ±0.2V PARAMETER/CONDITION OPERATING CURRENT: device bank; Active-Precharge; (MIN); (MIN); inputs changing once clock cyle; Address control inputs changing once every clock cycles OPERATING CURRENT: device bank; Active-Read-Precharge; Burst (MIN); (MIN); IOUT 0mA; Address control inputs changing once clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: device banks idle; Power-down mode; (MIN); (LOW) IDLE STANDBY CURRENT: HIGH; device banks idle; MIN; HIGH; Address other control inputs changing once clock cycle. VREF DQS, ACTIVE POWER-DOWN STANDBY CURRENT: device bank active; Power-down mode; (MIN); ACTIVE STANDBY CURRENT: HIGH; HIGH; device bank; Active-Precharge; (MAX); (MIN); inputs changing twice clock cycle; Address other control inputs changing once clock cycle OPERATING CURRENT: Burst Reads; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); IOUT OPERATING CURRENT: Burst Writes; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); inputs changing twice clock cycle AUTO REFRESH CURRENT tRFC (MIN)
SYMBOL IDD0
-26A/-265 1,080
UNITS
NOTES
IDD1a
1,350
IDD2Pb IDD2Fb
IDD3Pb IDD3Nb
IDD4Ra
1,350
IDD4Wa
1,260
IDD5b IDD5A
5,040 3,195
7.8125µs
SELF REFRESH CURRENT: 0.2V OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge with, (MIN); (MIN); Address control inputs change only during Active READ, WRITE commands
NOTE:
DD6b
IDD7a
Value calculated module rank this operating condition, other module ranks IDD2P (CKE LOW) Mode. Value calculated reflects module ranks this operating condition.
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Capacitance (MT9VDDT1672PH, MT9VDDT3272PH, MT9VDDT6472PH)
Note: notes appear pages 24-27 PARAMETER Input/Output Capacitance: DQS, Input Capacitance: Command Address Input Capacitance: Input Capacitance: Input Capacitance: SYMBOL 18.0 18.0 18.0 27.0 27.0 27.0 UNITS
Table Capacitance (MT18VDDT6472PH MT18VDDT12872PH)
Note: notes appear pages 24-27 PARAMETER Input/Output Capacitance: DQS, Input Capacitance: Command Address Input Capacitance: Input Capacitance: Input Capacitance: SYMBOL 36.0 18.0 18.0 10.0 54.0 27.0 27.0 UNITS
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Electrical Characteristics Recommended Operating Conditions (-335 -262)
SDRAM components only; notes appear pages 24-27 Notes: 1-5, 12-15, +70°C; VDDQ +2.5V ±0.2V CHARACTERISTICS PARAMETER Access window from CK/CK# high-level width low-level width Clock cycle time input hold time relative input setup time relative input pulse width (for each input) Access window from CK/CK# input high pulse width input pulse width DQS-DQ skew, last valid, group, access Write command first latching transition falling edge rising setup time falling edge from rising hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address control input hold time (slow slew rate) Address control input setup time (slow slew rate) Address Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, first non-valid, access Data Hold Skew Factor ACTIVE PRECHARGE command ACTIVE READ with Auto precharge command ACTIVE ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE READ WRITE delay PRECHARGE command period read preamble read postamble ACTIVE bank ACTIVE bank command write preamble
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
-335 SYMBOL
-262 +0.7 0.55 0.55 -0.75 0.45 0.45 1.75 +0.75 0.55 0.55 UNITS
-0.7 0.45 0.45 0.45 0.45 1.75 -0.60 0.35 0.35
NOTES
(2.5)
DIPW
+0.75
DQSCK DQSH DQSL
+0.60
-0.75 0.35 0.35
DQSQ DQSS
0.45 0.75
0.75 1.25
1.25
+0.70
+0.75
-0.70 0.75 0.75 0.80
-0.75 0.90 0.90
0.50 70,000
0.75 120,000
RPRE RPST
WPRE
0.25
0.25
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Electrical Characteristics Recommended Operating Conditions (-335 -262) (Continued)
SDRAM components only; notes appear pages 24-27 Notes: 1-5, 12-15, +70°C; VDDQ +2.5V ±0.2V CHARACTERISTICS PARAMETER write preamble setup time write postamble Write recovery time Internal WRITE READ command delay Data valid output window (DVW) REFRESH REFRESH command interval MT9VDDT1672PH MT9VDDT3272PH MT9VDDT6472PH MT9VDDT1672PH Average periodic refresh interval MT9VDDT3272PH MT9VDDT6472PH Terminating voltage delay Exit SELF REFRESH non-READ command Exit SELF REFRESH READ command
-335 SYMBOL
-262 UNITS
NOTES
WPRES
WPST
REFC
DQSQ 140.6 70.3 15.6
DQSQ 140.6 70.3 15.6
REFI
XSNR XSRD
Table Electrical Characteristics Recommended Operating Conditions (-26A, -265, -202)
SDRAM components only; notes appear pages 24-27 Notes: 1-5, 12-15, +70°C; VDDQ +2.5V ±0.2V CHARACTERISTICS PARAMETER Access window from CK/CK# high-level width low-level width Clock cycle time input hold time relative input setup time relative input pulse width (for each input) Access window from CK/CK# input high pulse width input pulse width DQS-DQ skew, last valid, group, access Write command first latching transition falling edge rising setup time falling edge from rising hold time Half clock period
-26A/-265 SYMBOL
-202 -0.8 0.45 0.45 +0.8 0.55 0.55 UNITS
-0.75 0.45 0.45 1.75 -0.75 0.35 0.35
+0.75 0.55 0.55
NOTES
(2.5)
DIPW
DQSCK DQSH DQSL
+0.75
-0.8 0.35 0.35
+0.8
DQSQ DQSS
0.75
0.75
1.25
1.25
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Table Electrical Characteristics Recommended Operating Conditions (-26A, -265, -202) (Continued)
SDRAM components only; notes appear pages 24-27 Notes: 1-5, 12-15, +70°C; VDDQ +2.5V ±0.2V CHARACTERISTICS PARAMETER Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address control input hold time (slow slew rate) Address control input setup time (slow slew rate) Address Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, first non-valid, access Data Hold Skew Factor ACTIVE PRECHARGE command ACTIVE READ with Auto precharge command ACTIVE ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE READ WRITE delay PRECHARGE command period read preamble read postamble ACTIVE bank ACTIVE bank command write preamble write preamble setup time write postamble Write recovery time Internal WRITE READ command delay Data valid output window (DVW) REFRESH REFRESH command MT9VDDT1672PH interval others Average periodic refresh MT9VDDT1672PH interval others Terminating voltage delay Exit SELF REFRESH non-READ command Exit SELF REFRESH READ command
-26A/-265 SYMBOL
-202 -0.8 +0.8 UNITS
-0.75
+0.75
NOTES
0.75
0.25
120,000
120,000
RPRE RPST
0.25
WPRE WPST
WPRES
REFC REFI
tVTD
DQSQ 140.6 70.3 15.6
DQSQ 140.6 70.3 15.6
XSNR XSRD
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc. rights reserved.
128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
Notes
voltages referenced VSS. Tests timing, IDD, electrical characteristics conducted nominal reference/supply voltage levels, related specifications device operation guaranteed full voltage range specified. Outputs measured with equivalent load:
Reference Point 30pF
Output (VOUT)
timing tests VIL-to-VIH swing 1.5V test environment, input timing still referenced VREF crossing point CK/CK#), parameter specifications guaranteed specified input levels under normal conditions. minimum slew rate input signals used test device 1V/ns range between VIL(AC) VIH(AC). input level specifications defined SSTL_2 Standard (i.e., receiver will effectively switch result signal crossing input level, will remain that state long signal does ring back above [below] input [HIGH] level). VREF expected equal VDDQ/2 transmitting device track variations level same. Peak-to-peak noise (non-common mode) Vref exceed percent value. Thus, from VDDQ/2, Vref allowed ±25mV error additional ±25mV noise. This measurement taken nearest VREF bypass capacitor. applied directly device. system supply signal termination resistors, expected equal VREF must track variations level VREF. dependent output loading cycle rates. Specified values obtained with minimum cycle time -26A -202, -335 -265 with outputs open. Enables on-chip refresh address counters. specifications tested after device properly initialized, averaged defined cycle rate. This parameter sampled. +2.5V ±0.2V, VDDQ +2.5V ±0.2V, VREF VSS, MHz, 25°C, VOUT(DC) VDDQ/2, VOUT (peak peak)
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
0.2V. input grouped with pins, reflecting fact that they matched loading. Command/Address input slew rate 0.5V/ns. -262, -26A -265 with slew rates 1V/ns faster, reduced 900ps; -335 with slew rates V/ns faster, reduced 750ps. slew rate less than 0.5V/ timing must derated: additional 50ps each mV/ns reduction slew rate from /ns, while remains constant. slew rate exceeds 4.5V/ns, functionality uncertain. CK/CK# input reference level (for timing referenced CK/CK#) point which cross; input reference level signals other than CK/CK# VREF. Inputs recognized valid until VREF stabilizes. Exception: during period before VREF stabilizes, VDDQ recognized LOW. output timing reference level, measured timing reference point indicated Note VTT. transitions occur same access time windows data valid transitions. These parameters referenced specific voltage level, specify when device output longer driving (HZ) begins driving (LZ). intent Don't Care state after completion postamble DQS-driven signal should either high, low, high-Z that signal transition within input switching region must follow valid input requirements. That transitions high [above VIHDC (MIN)] then must transition (below VIHDC) prior tDQSH (MIN). This device limit. device will operate with negative value, system performance could degraded turnaround. recommended that valid (HIGH LOW) before WRITE command. case shown (DQS going from High-Z logic LOW) applies when WRITEs were previously progress bus. previous WRITE progress, could HIGH during this time, depending tDQSS. (tRC tRFC) measurements smallest multiple that meets minimum absolute value respective parameter. tRAS (MAX) measurements largest multi-
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128MB, 256MB, 512MB, (x72, ECC, PLL) 200-PIN SDRAM SODIMM
that meets maximum absolute value tRAS. refresh period 64ms. This equates average refresh rate 15.625µs (MT9VDDT1672PH), 7.8251µs (MT9VDDT3272PH, MT18VDDT6472PH, MT9VDDT6472PH, MT18VDDT12872PH). However, AUTO REFRESH command must asserted least once every 140.6µs (MT9VDDT1672PH) 70.3µs (MT9VDDT3272PH, MT18VDDT6472PH, MT9VDDT6472PH, MT18VDDT12872PH); burst refreshing posting DRAM controller greater than eight refresh cycles allowed. valid data window derived achieving other specifications: (tCK/2), tDQSQ, (tQH tQHS). data valid window derates direct porportion with clock duty cycle practical data valid window derived, shown Figure Derating Data Valid Window. clock allowed maximum duty cycle variation 45/55 beyond which functionality uncertain. data valid window derating curves provided below duty cycles ranging between 50/50 45/55. Each byte lane corresponding DQS. This limit actually nominal value does result fail value. HIGH during REFRESH command period (tRFC [MIN]) else (i.e., during standby). maintain valid level, transitioning edge input must: Sustain constant slew rate from current level through target level, VIL(AC) VIH(AC). Reach least target level. After target level reached, continue maintain least target level, VIL(DC) VIH(DC). JEDEC specifies input slew rate must 1V/ns (2V/ns differentially). input slew rates must deviate from more than percent. DQ/DM/ slew rate less than 0.5V/ns, timing must derated: 50ps must added each 100mv/ns reduction slew rate. slew rate exceeds 4V/ns, functionality uncertain. must vary more than percent active while bank active. clock allowed ±150ps jitter. Each timing parameter allowed vary same amount.
Figure Derating Data Valid Window
(tQH tDQSQ)
3.750 3.400 3.700
3.650
3.600
3.550 3.500 3.450 3.400 3.200 3.150 3.100 3.350 3.300
3.350
3.300 3.250
-26A/-265 10ns -202 10ns -262/-26A/-265 7.5ns -202 -335
3.250
3.050 3.000 2.950 2.900
2.500
2.463
2.425
2.388
2.350
2.313
2.275
2.238
2.200
2.163
2.125
50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 Clock Duty Cycle 47/53 46.5/54.5 46/54 45.5/55.5 45/55
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
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lesser minimum ttCH minimum actually applied device inputs, collectively during bank active. READs WRITEs with auto precharge allowed issued until tRAS(min) satisfied prior internal precharge command being issued. positive glitch must less than clock more than +400mV 2.9V, whichever less. negative glitch must less than clock cycle exceed either 300mV 2.2V, whichever more positive. Normal Output Drive Curves: full variation driver pull-down current from minimum maximum process, temperature voltage will within outer bounding lines curve Figure Pull-Down Characteristics. variation driver pull-down current within nominal limits voltage temperature expected, guaranteed, within inner bounding lines curve Figure Pull-Down Characteristics. full variation driver pull-up current from minimum maximum process, temperature voltage will within outer bounding lines curve Figure Pull-Up Characteristics variation driver pull-up current within nominal limits voltage temperature expected, guaranteed, within inner bounding lines curve Figure Pull-Up Characteristics. full variation ratio maximum minimum pull-up pull-down current should between 0.71 1.4, device drain-to-source voltages from 0.1V 1.0V, same voltage temperature. full variation ratio nominal pull-up pull-down current should unity percent, device drain-to-source voltages from 0.1V 1.0V. voltage levels used derived from minimum level referenced test load. practice, voltage levels obtained from properly terminated will provide significantly different voltage values. overshoot: VIH(MAX) VDDQ 1.5V pulse width pulse width greater than cycle rate. undershoot: VIL(MIN) -1.5V pulse width pulse width greater than cycle rate. VDDQ must track each other. This maximum value derived from referenced test load. practice, values obtained typical terminated design reflect 310ps less tHZ(MAX) last DVW. HZ(MAX) will prevail over tDQSCK(MAX) RPST(MAX) condition. tLZ(MIN) will prevail over DQSCK(MIN) tRPRE(MAX) condition. slew rates greater than 1V/ns (LZ) transition will start about 310ps earlier. During initialization, VDDQ, VTT, VREF must equal less than 0.3V. Alternatively, 1.35V maximum during power even VDD/VDDQ 0Vs, provided minimum series resistance used between supply input pin. current Micron part operates below slowest JEDEC operating frequency MHz. such, future reflect this option.
Figure Pull-Down Characteristics
Figure Pull-Up Characteristics
Maxim
Maximum
Nominal high
high Nominal
IOUT (mA)
IOUT (mA)
-100 -120 -140 -160
Nominal
inal
Minimum
-180 -200
VOUT
VDDQ VOUT
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
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-335, -262, -26A, -265, -202 modules, IDD3N specified 35mA SDRAM device MHz. Random addressing changing percent data changing every transfer. Random addressing changing percent data changing every transfer. must active (high) during entire time refresh command executed. That from time AUTO REFRESH command registered, must active each rising clock edge, until later. IDD2N specifies DQS, driven valid high logic level. IDD2Q similar IDD2F except IDD2Q specifies address control inputs remain stable. Although IDD2F, IDD2N, IDD2Q similar, IDD2F "worst case." Whenever operating frequency altered, including jitter, required reset. This followed clock cycles. Leakage number reflects worst case leakage possible through module pin, what each memory device contributes. When input signal HIGH LOW, defined steady state logic HIGH LOW.
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Table Clock Driver Timing Requirements Switching Characteristics
Note: 2.5V 0.2V PARAMETER Operating Clock Frequency Input Duty Cycle Stabilization Time Cycle Cycle Jitter Static Phase Offset Output Clock Skew Period Jitter Half-Period Jitter Input Clock Slew Rate Output Clock Slew Rate
NOTE:
SYMBOL
-100
NOMINAL
UNITS V/ns V/ns
NOTES
STAB JITCC
JITPER
JITHPER
timing switching specifications listed above critical proper operation SDRAM Registered DIMMs. These meant subset parameters specific device used module. Detailed information this available JEDEC Standard JESD82. must able handle spread spectrum induced skew. Operating clock frequency indicates range over which must able lock, which required meet other timing parameters. (Used low-speed system debug.) Stabilization time time required integrated circuit obtain phase lock feedback signal reference signal after power Static Phase Offset does include Jitter. Period Jitter Half-Period Jitter specifications separate specifications that must independently each other. Output Slew Rate determined from IBIS model:
CDCV857
R=60
R=60
VDD/2
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Clock Data Conventions
Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions shown Figure Data Validity, Figure Definition Start Stop).
Acknowledge
Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data shown Figure Acknowledge Response from Receiver). device will always respond with acknowledge after recognition start condition slave address. both device WRITE operation have been selected, device will respond with acknowledge after receipt each subsequent eight-bit word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
Start Condition
commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met.
Stop Condition
communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode.
Figure Data Validity
Figure Definition Start Stop
DATA STABLE DATA CHANGE DATA STABLE
START
STOP
Figure Acknowledge Response from Receiver
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
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Table EEPROM Device Select Code
Most significant (b7) sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code DEVICE TYPE IDENTIFIER CHIP ENABLE
Table EEPROM Operating Modes
MODE Current Address Read Random Address Read Sequential Read Byte Write Page Write BYTES INITIAL SEQUENCE START, Device Select, START, Device Select, `0', Address reSTART, Device Select, Similar Current Random Address Read START, Device Select, START, Device Select,
Figure EEPROM Timing Diagram
HIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
UNDEFINED
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Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; VDDSPD +2.3V +3.6V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs POWER SUPPLY CURRENT: clock frequency SYMBOL UNITS
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; VDDSPD +2.3V +3.6V PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time
NOTE:
SYMBOL HD:DAT HD:STA HIGH SU:DAT SU:STA SU:STO
UNITS
NOTES
avoid spurious START STOP conditions, minimum delay placed between falling rising edge SDA. This parameter sampled. reSTART condition, following WRITE cycle. EEPROM WRITE cycle time (tWRC) time from valid stop condition write sequence EEPROM internal erase/program cycle. During WRITE cycle, EEPROM interface circuit disabled, remains HIGH pull-up resistor, EEPROM does respond slave address.
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Table Serial Presence-Detect Matrix (MT9VDDT1672PH, MT9VDDT3272PH, MT9VDDT6472PH)
"1"/"0": Serial Data, "driven HIGH"/"driven LOW" BYTE DESCRIPTION Number Bytes Used Micron Total Number Bytes Device Fundamental Memory Type Number Addresses Assembly Number Column Addresses Assembly Number Physical Ranks DIMM Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, (CAS Latency 2.5) (See note SDRAM Access from Clock, (CAS Latency 2.5) (See note Module Configuration Type Refresh Rate/ Type SDRAM Device Width (Primary SDRAM) Error-checking SDRAM Data Width Minimum Clock Delay, Back-to-Back Random Column Access Burst Lengths Supported Number Banks SDRAM Device Latencies Supported Latency Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, (CAS Latency (See note SDRAM Access from (CAS Latency (See note SDRAM Cycle Time, (CAS Latency 1.5) SDRAM Access from (CAS Latency 1.5) ENTRY(VERSION) MT9VDDT1672PH MT9VDDT3272PH MT9VDDT6472PH SDRAM or13 SSTL 2.5V (-335) (-262/-26A) 7.5ns (-265) (-202) 0.7ns (-335) 0.75ns (-262/-26A/265) 0.8ns (-202) 15.6µs 7.8µs/SELF clock Unbuffered, Diff CLK, Fast/concurrent auto precharge 7.5ns (-335/-262/-26A) 10ns (-202/-265) 0.7ns (-335) 0.75ns (-265/-26A) 0.8ns (-202)
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
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Table Serial Presence-Detect Matrix (MT9VDDT1672PH, MT9VDDT3272PH, MT9VDDT6472PH) (Continued)
"1"/"0": Serial Data, "driven HIGH"/"driven LOW" BYTE DESCRIPTION Minimum Precharge Time, ENTRY(VERSION) MT9VDDT1672PH MT9VDDT3272PH MT9VDDT6472PH 18ns (-335) 15ns (-262) 20ns (-26A/-265/-202) 12ns (-335) 15ns (-262/-26A/-265/-202) 18ns (-335) 15ns (-262) 20ns (-26A/-265/-202) 42ns (-335) 45ns (-262/-26A/-265) 40ns (-202) 128MB 256MB 0.8ns (-335) 1.0ns (-262/-26A/-265) 1.1ns (-202) 0.8ns (-335) 1.0ns (-262/-26A/-265) 1.1ns (-202) 0.45ns (-335 0.5ns (-262/-26A/-265) 0.6ns (-202) 0.45ns (-335 0.5ns (-262/-26A/-265) 0.6ns (-202)
Minimum Active Active, Minimum RAS# CAS# Delay, tRCD
Minimum RAS# Pulse Width, tRAS (See note Module Rank Density Address Command Setup Time, (see note Address Command Hold Time, (see note Data/Data Mask Input Setup Time,
Data/ Data Mask Input Hold Time,
60ns (-335/-262) 65ns (-26A/-265) 70ns (-202) 72ns (-335) Minimum Auto Refresh Active/Auto 75ns (-262/-26A/-265) Refresh Command Period, tRFC 80ns (-202) SDRAM Device Cycle Time, 12ns (-335) 13ns (-262/-26A/-265/-202) SDRAM Device DQS-DQ Skew Time, 0.45ns (-335) 0.5ns (-262/-26A/-265) DQSQ 0.6ns (-202) SDRAM Device Read Data Hold 0.6ns (-335) 0.75ns (-262/-26A/-265) Skew Factor (-202) Reserved DIMM Height 48-61 Reserved Revision Initial Release Checksum Bytes 0-62 -335 -262 -26A -265 -202
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
36-40 Reserved Active Refresh Time
11/01 11/01 11/01 2A/1A (see note 4D/3D (see note 8E/7E (see note FD/ED (see note E0/D0 (see note 21/11 (see note 2A/1A (see note 0D/FD (see note 4E/3E (see note 5A/4A (see note 3D/2D (see note 80/6E (see note F5/E5 (see note D8/C8 (see note 19/09 (see note
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Table Serial Presence-Detect Matrix (MT9VDDT1672PH, MT9VDDT3272PH, MT9VDDT6472PH) (Continued)
"1"/"0": Serial Data, "driven HIGH"/"driven LOW" BYTE DESCRIPTION ENTRY(VERSION) MT9VDDT1672PH MT9VDDT3272PH MT9VDDT6472PH MICRON 01-0C Variable Data 01-09 Variable Data Variable Data Variable Data 01-0C Variable Data 01-09 Variable Data Variable Data Variable Data 01-0C Variable Data 01-09 Variable Data Variable Data Variable Data
Manufacturer's JEDEC Code 65-71 Manufacturer's JEDEC Code (continued) Manufacturing Location 73-90 Module Part Number (ASCII) Identification Code Identification Code (Continued) Year Manufacture Week Manufacture 95-98 Module Serial Number Manufacturer-Specific Data RSVD)
NOTE:
01-12
Device latencies used values. Value -262/-26A (0x70) optimum BIOS compatibility. Actual device spec. value 7.5ns. value tRAS used -265 modules calculated from tRP. Actual device spec value 40ns. JEDEC specification allows fast slow slew rate values these bytes. worst-case (slow slew rate) value represented here. Systems requiring fast slew rate setup hold values supported, provided faster minimum slew rate met. Values given format "standard DIMM Height checksum low-profile DIMM height checksum."
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Table Serial Presence- Detect Matrix (MT18VDDT6472PH MT18VDDT12872PH)
"1"/"0": Serial Data, "driven HIGH"/"driven LOW" BYTE DESCRIPTION Number Bytes Used Micron Total Number Bytes Device Fundamental Memory Type Number Addresses Assembly Number Column Addresses Assembly Number Physical Ranks DIMM Module Data Width Module Data Width (Continued) Module Voltage Interface Levels ENTRY(VERSION) MT18VDDT6472PH MT18VDDT12872PH
SDRAM SSTL 2.5V (-335) SDRAM Cycle Time, (CAS Latency 2.5) (-262/-26A) (See note 7.5ns (-265) (-202) 0.7ns (-335) SDRAM Access from Clock, (CAS Latency 0.75ns (-262/-26A/-265) 2.5) 0.8ns (-202) (See note Module Configuration Type Refresh Rate/ Type SDRAM Device Width (Primary SDRAM) Error-checking SDRAM Data Width Minimum Clock Delay, Back-to-Back Random Column Access Burst Lengths Supported Number Banks SDRAM Device Latencies Supported Latency Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, (CAS Latency (See note 7.8µs/SELF clock Unbuffered, Diff CLK, Fast/concurrent auto precharge 7.5ns (-335/-26A/-262) 10ns (-265/-202)
0.7ns (-335) SDRAM Access from (CAS Latency 0.75ns (-262/-26A/-265) (See note 0.8ns (-202) SDRAM Cycle Time, (CAS Latency 1.5) SDRAM Access from (CAS Latency 1.5) Minimum Precharge Time, 18ns (-335) 15ns (-262) 20ns (-202/-265/-26A) 12ns (-335) 15ns (-262/-26A/-265/-202)
Minimum Active Active, tRRD
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Table Serial Presence- Detect Matrix (MT18VDDT6472PH MT18VDDT12872PH) (Continued)
"1"/"0": Serial Data, "driven HIGH"/"driven LOW" BYTE DESCRIPTION Minimum RAS# CAS# Delay, tRCD ENTRY(VERSION) MT18VDDT6472PH MT18VDDT12872PH 11/01 4E/3E (see note E1/D1 (see note 0E/FE (see note 3E/2E (see note D9/C9 (see note 01-0B Variable Data 11/01 8F/7F (see note 2C/12 (see note 4F/3F (see note 7F/6F (see note 1A/0A (see note 01-0C Variable Data
36-40
48-61
65-71 73-90
18ns (-335) 15ns (-262) 20ns (-26A/-265/-202) 42ns (-335) Minimum RAS# Pulse Width, tRAS (See note 45ns (-262/-26A/-265) 40ns (-202) 512MB Module Rank Density 0.8ns (-335) Address Command Setup Time, 1.0ns (-262/-26A/-265) (see note 1.1ns (-202) 0.8ns (-335) Address Command Hold Time, 1.0ns (-262/-26A/-265) (see note 1.1ns (-202) 0.45ns (-335 Data/Data Mask Input Setup Time, 0.5ns (-262/-26A/-265) 0.6ns (-202) 0.45ns (-335 Data/ Data Mask Input Hold Time, 0.5ns (-262/-26A/-265) 0.6ns (-202) Reserved 60ns (-335/-262) Active Refresh Time 65ns (-265/-26A) 70ns (-202) 72ns (-335) Minimum Auto Refresh Active/Auto 75ns (-262/-26A/-265) Refresh Command Period, tRFC 80ns (-202) 12ns (-335) SDRAM Device Cycle Time, CKMAX 13ns (-262/-26A/-265/202) 0.45ns (-335) SDRAM Device DQS-DQ Skew Time, 0.5ns (-262/-26A/-265) DQSQ 0.6ns (-202) 0.6ns (-335) SDRAM Device Read Data Hold Skew 0.75ns (-262/-26A/-265) Factor (-202) Reserved Standard/Low Profile DIMM Height Reserved Initial Release Revision -335 Checksum Bytes 0-62 -262 -26A -265 -202 MICRON Manufacturer's JEDEC Code Manufacturer's JEDEC Code (continued) 01-12 Manufacturing Location Module Part Number (ASCII)
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
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Table Serial Presence- Detect Matrix (MT18VDDT6472PH MT18VDDT12872PH) (Continued)
"1"/"0": Serial Data, "driven HIGH"/"driven LOW" BYTE 95-98 99-127
NOTE:
DESCRIPTION Identification Code Identification Code (Continued) Year Manufacture Week Manufacture Module Serial Number Manufacturer-Specific Data RSVD)
ENTRY(VERSION)
MT18VDDT6472PH MT18VDDT12872PH 01-09 Variable Data Variable Data Variable Data 01-09 Variable Data Variable Data Variable Data
Device latencies used values. Value -26A (0x70) optimum BIOS compatibility. Actual device spec. value 7.5ns. value tRAS used -265 modules calculated from tRP. Actual device spec value 40ns. JEDEC specification allows fast slow slew rate values these bytes. worst-case (slow slew rate) value represented here. Systems requiring fast slew rate setup hold values supported, provided faster minimum slew rate met. Values given format "standard DIMM Height checksum low-profile DIMM height checksum."
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Figure Standard 200-Pin SODIMM Dimensions
FRONT VIEW
2.666 (67.72) 2.656 (67.45)
Single Rank Modules
0.150 (3.80)
0.079 (2.00) (2X)
0.071 (1.80) (2X)
1.405 (35.69) 1.395 (35.43) 0.787 (20.00)
0.236 (6.00) 0.096 (2.44) 0.043 (1.10) 0.035 (0.90) 0.039 (0.99) 0.018 (0.46) 0.024 (0.61)
0.079 (2.00)
2.504 (63.60)
Dual Rank Modules
0.320 (8.13)
BACK VIEW
0.043 (1.10) 0.035 (0.90)
NOTE:
dimensions inches (millimeters), typical where noted.
09005aef808ffdc7 DD9_18C16_32_64_128X72PHG_E.fm Rev. 7/03
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Figure Low-Profile 200-Pin SODIMM Dimensions
FRONT VIEW
2.667 (67.75) 2.656 (67.45)
0.150 (3.80)
0.079 (2.00) (2X)
0.071 (1.80) (2X)
1.244 (31.60) 1.256 (31.90) 0.787 (20.00)
0.236 (6.00) 0.096 (2.44) 0.043 (1.10) 0.035 (0.90) 0.039 (0.99) 0.018 (0.46) 0.024 (0.61)
0.079 (2.00)
2.504 (63.60)
Dual Rank Modules
.320 (8.13)
BACK VIEW
NOTE:
.043 (1.10) .035 (0.90)
dimensions inches (millimeters), typical where noted.
Data Sheet Designation
Released: This data sheet contains minimum maximum limits specified over complete power supply temperature range production devices. Although considered final, these specifications subject change, further product development data characterization sometimes occur.
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SDRAM SMALL-OUTLINE DIMM 200-pin, small-outline, dual in-line mem

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