14-Pin FLASH-Based 8-Bit CMOS Microcontrollers with nanoWatt Technolog
|
|
|
Top Searches for this datasheet
PIC16F684 Data Sheet
14-Pin FLASH-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology
2003 Microchip Technology Inc.
DS41202A
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like intended through suggestion only superseded updates. your responsibility ensure that your application meets with your specifications. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights.
Trademarks Microchip name logo, Microchip logo, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, MATE PowerSmart registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Accuron, Application Maestro, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, InCircuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel Total Endurance trademarks Microchip Technology Incorporated U.S.A. other countries. Serialized Quick Turn Programming (SQTP) service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2003, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved.
Printed recycled paper. Microchip received QS-9000 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona July 1999 Mountain View, California March 2002. Company's quality system processes procedures QS-9000 compliant PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001 certified.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
14-Pin FLASH-Based 8-Bit CMOS Microcontroller
High Performance RISC
Only instructions learn single-cycle instructions except branches Operating speed: oscillator/clock input instruction cycle Interrupt capability 8-level deep hardware stack Direct, Indirect Relative Addressing modes
Power Features
Standby Current: 2.0V, typical Operating Current: kHz, 2.0V, typical MHz, 2.0V, typical Watchdog Timer Current: 2.0V, typical
Peripheral Features Special Microcontroller Features
Precision Internal Oscillator Factory calibrated Software selectable frequency range Software adjustable Two-Speed Start-up mode Crystal fail detect critical applications Clock mode switching during operation power operation Power saving SLEEP mode Wide operating voltage range. (2.0V 5.5V) Industrial Extended Temperature range Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Brown-out Detect (BOD) with software control option Enhanced Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal seconds with full prescaler) with software enable Multiplexed Master Clear with pull-up/Input Programmable code protection High Endurance FLASH/EEPROM cell 100,000 write FLASH endurance 1,000,000 write EEPROM endurance FLASH/Data EEPROM Retention: years pins with individual direction control High current source/sink direct drive Interrupt-on-pin change Individually programmable weak pull-ups Ultra Power Wake-up Analog comparator module with: analog comparators Programmable on-chip voltage reference (CVREF) module VDD) Comparator inputs outputs externally accessible Converter 10-bit resolution channels Timer0: 8-bit timer/counter with 8-bit programmable prescaler Enhanced Timer1 16-bit timer/counter with prescaler External Gate Input mode Option OSC1 OSC2 mode Timer1 oscillator, INTOSC mode selected Timer2: 8-bit timer/counter with 8-bit period register, prescaler postscaler Enhanced Capture, Compare, module 16-bit Capture, resolution 12.5 Compare, resolution 10-bit with output channels, programmable "dead time", frequency In-Circuit Serial Programming(ICSPTM) pins
Device
Program Memory FLASH (words) 2048
Data Memory SRAM (bytes) EEPROM (bytes) 10-bit (ch) Comparators
Timers 8/16-bit
PIC16F684
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
Diagram
14-pin PDIP, SOIC, TSSOP
RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5/CCP1/P1A RC4/C2OUT/P1B RC3/AN7/P1C
RA0/AN0/C1IN+/ICSPDAT RA1/AN1/C1IN-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RC1/AN5/C2INRC2/AN6/P1D
DS41202A-page
PIC16F684
2003 Microchip Technology Inc.
PIC16F684
Table Contents
Device Overview Memory Organization Oscillator Configurations Ports Timer0 Module Timer1 Module with Gate Control. Timer2 Module Enhanced Capture/Compare/PWM (ECCP) Module. Comparator Module. 10.0 Analog-to-Digital Converter (A/D) Module. 11.0 Data EEPROM Memory 12.0 Special Features CPU. 13.0 Instruction Summary 14.0 Development Support. 15.0 Electrical Specifications. 16.0 Packaging Information. Appendix Data Sheet Revision History. Appendix Migrating from other PICmicro® Devices Index On-Line Support. Systems Information Upgrade Line Reader Response Product Identification System
VALUED CUSTOMERS
intention provide valued customers with best documentation possible ensure successful your Microchip products. this end, will continue improve publications better suit your needs. publications will refined enhanced volumes updates introduced. have questions comments regarding this publication, please contact Marketing Communications Department E-mail docerrors@mail.microchip.com Reader Response Form back this data sheet (480) 792-4150. welcome your feedback.
Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting sales office literature center, please specify which device, revision silicon data sheet (include literature number) using.
Customer Notification System
Register site www.microchip.com/cn receive most current information products.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
NOTES:
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
DEVICE OVERVIEW
This document contains device specific information PIC16F684. Additional information found PICmicroMid-Range Reference Manual (DS33023), which obtained from your local Microchip Sales Representative downloaded from Microchip site. Reference Manual should considered complementary document this Data Sheet highly recommended reading better understanding device architecture operation peripheral modules. PIC16F684 covered this Data Sheet. available 14-pin PDIP, SOIC TSSOP packages. Figure shows block diagram PIC16F684 device. Table shows pinout description.
FIGURE 1-1:
PIC16F684 BLOCK DIAGRAM
CONFIGURATION PROGRAM COUNTER FLASH PROGRAM MEMORY DATA PORTA 8-LEVEL STACK (13-BIT) BYTES FILE REGISTERS ADDR
PROGRAM
INSTRUCTION DIRECT ADDR
ADDR INDIRECT ADDR PORTC POWER-UP TIMER
STATUS
INSTRUCTION DECODE CONTROL TIMING GENERATION
OSCILLATOR START-UP TIMER POWER-ON RESET WATCHDOG TIMER BROWN-OUT DETECT
OSC1/CLKIN OSC2/CLKOUT
INTERNAL OSCILLATOR BLOCK T1CKI TIMER0 T0CKI TIMER1 TIMER2 MCLR
CCP1/P1A
ECCP
ANALOG-TO-DIGITAL CONVERTER
ANALOG COMPARATORS REFERENCE
EEDATA BYTES DATA EEPROM EEADDR
VREF
C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
TABLE 1-1: PIC16F684 PINOUT DESCRIPTION
Function
C1IN+ ICSPDAT RA1/AN1/C1IN-/VREF/ICSPCLK C1INVREF ICSPCLK T0CKI C1OUT MCLR OSC2 CLKOUT T1CKI OSC1 CLKIN C2IN+ C2INRC2 C2OUT CCP1
Name
RA0/AN0/C1IN+/ICSPDAT
Input Type
XTAL Power Power
Output Type
CMOS CMOS CMOS CMOS CMOS CMOS XTAL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Description
PORTA prog pull-up, Interrupt-on-change Ultra Power Wake-up Channel input Comparator input Serial Programming Data PORTA prog pull-up Interrupt-on-change Channel input Comparator input External Voltage Reference Serial Programming Clock PORTA prog pull-up Interrupt-on-change Channel input Timer0 clock input External Interrupt Comparator output PORTA input with Interrupt-on-change Master Clear internal pull-up Programming voltage PORTA prog pull-up Interrupt-on-change Channel input Timer1 gate Crystal/Resonator FOSC/4 output PORTA prog pull-up Interrupt-on-change Timer1 clock Crystal/Resonator External clock input/RC oscillator connection PORTC Channel input Comparator input PORTC Channel input Comparator input PORTC Channel input output PORTC Channel input output PORTC Comparator output output PORTC Capture input/Compare output output Ground reference Positive supply
RA2/AN2/T0CKI/INT/C1OUT
RA3/MCLR/VPP
RA4/AN3/T1G/OSC2/CLKOUT
RA5/T1CKI/OSC1/CLKIN
RC0/AN4/C2IN+
RC1/AN5/C2IN-
RC2/AN6/P1D
RC3/AN7/P1C
RC4/C2OUT/P1B
RC5/CCP1/P1A
Legend:
input buffer Schmitt Trigger input buffer Analog input
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
MEMORY ORGANIZATION
Program Memory Organization
Data Memory Organization
PIC16F684 13-bit program counter capable addressing program memory space. Only first (0000h 07FFh) PIC16F684 physically implemented. Accessing location above these boundaries will cause wrap around within first space. RESET vector 0000h interrupt vector 0004h (see Figure 2-1).
data memory (see Figure 2-2) partitioned into banks, which contain general purpose registers Special Function Registers (SFR). Special Function Registers located first locations each bank. Register locations 20h-7Fh Bank A0h-BFh Bank general purpose registers, implemented static RAM. Register locations F0hFFh Bank point addresses 70h-7Fh Bank other unimplemented returns when read. (STATUS<5>) bank select bit. Bank selected Bank selected Note: bits STATUS<7:6> reserved should always maintained `0's.
FIGURE 2-1:
PROGRAM MEMORY STACK PIC16F684
PC<12:0>
CALL, RETURN RETFIE, RETLW
2.2.1
STACK LEVEL STACK LEVEL
GENERAL PURPOSE REGISTER FILE
STACK LEVEL RESET VECTOR
register file organized PIC16F684. Each register accessed, either directly indirectly through File Select Register (see Section Indirect Addressing, INDF Registers).
000H
INTERRUPT VECTOR
0004 0005
ON-CHIP PROGRAM MEMORY 07FFH 0800H
1FFFH
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
2.2.2 SPECIAL FUNCTION REGISTERS FIGURE 2-2:
Special Function Registers registers used peripheral functions controlling desired operation device (see Table 2-1). These registers static RAM. special registers classified into sets: core peripheral. Special Function Registers associated with "core" described this section. Those related operation peripheral features described section that peripheral feature.
DATA MEMORY PIC16F684
FILE ADDRESS FILE ADDRESS INDIRECT ADDR.(1) OPTION_REG STATUS TRISA TRISC PCLATH INTCON PIE1 PCON OSCCON OSCTUNE ANSEL PIR2 WPUA IOCA VRCON EEDAT EEADR EECON1 EECON2(1) ADRESL ADCON1 GENERAL PURPOSE REGISTERS BYTES
INDIRECT ADDR.(1) TMR0 STATUS PORTA PORTC PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON PWM1CON ECCPAS WDTCON CMCON0 CMCON1 ADRESH ADCON0
GENERAL PURPOSE REGISTERS BYTES
BANK
ACCESSES 70H-7FH BANK
Unimplemented data memory locations, read '0'. Note physical register.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
TABLE 2-1:
Addr
Bank INDF TMR0 STATUS PORTA PORTC PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON PWM1CON ECCPAS WDTCON CMCON0 CMCON1 ADRESH ADCON0 Addressing this location uses contents address data memory (not physical register) Timer0 Module's Register Program Counter's (PC) Least Significant Byte
PIC16F684 SPECIAL REGISTERS SUMMARY BANK
Value POR,
xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xxxx Control Registers xxxx PEIE ADIF T0IE CCP1IF Write buffer upper bits program counter INTE C2IF RAIE C1IF T0IF OSFIF INTF TMR2IF RAIF TMR1IF 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx T1SYNC TMR2ON TMR1CS T2CKPS1 TMR1ON T2CKPS0 0000 0000 0000 0000 TOUTPS2 TOUTPS1 TOUTPS0 -000 0000 xxxx xxxx xxxx xxxx CCP1M3 PDC3 PSSAC1 WDTPS2 CCP1M2 PDC2 PSSAC0 WDTPS1 CCP1M1 PDC1 PSSBD1 WDTPS0 T1GSS CCP1M0 PDC0 PSSBD0 SWDTEN C2SYNC 0000 0000 0000 0000 0000 0000
Name
Page
18,102 47,102 17,102 11,102 18,102 35,102 43,102 17,102 13,102 15,102 50,102 50,102 52,102 54,102 54,102 57,102 57,102 57,102 67,102 68,102
Indirect data memory address pointer Unimplemented Unimplemented Unimplemented EEIF Unimplemented Holding register Least Significant Byte 16-bit TMR1 Holding register Most Significant Byte 16-bit TMR1 T1GINV T1GE TOUTPS3 T1CKPS1 T1CKPS0 T1OSCEN Timer2 Module Register Capture/Compare/PWM Register1 Byte Capture/Compare/PWM Register1 High Byte P1M1 PRSEN ECCPASE C2OUT Unimplemented Unimplemented Unimplemented Most Significant bits left shifted result bits right shifted result ADFM VCFG CHS2 CHS1 CHS0 GO/DONE ADON P1M0 PDC6 ECCPAS2 C1OUT DC1B1 PDC5 ECCPAS1 C2INV DC1B0 PDC4 ECCPAS0 WDTPS3 C1INV Control Registers
1000 109,102 0000 0000 xxxx xxxx 00-0 0000 73,102 77,102 83,102 84,102
Legend: Note
Unimplemented locations read `0', unchanged, unknown, value depends condition shaded unimplemented bits reserved, always maintain these bits clear.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
TABLE 2-2:
Addr
Bank INDF Addressing this location uses contents address data memory (not physical register) INTEDG T0CS OPTION_REG RAPU T0SE STATUS TRISA TRISC PCLATH INTCON PIE1 PCON OSCCON OSCTUNE ANSEL WPUA(3) IOCA VRCON EEDAT EEADR EECON1 EECON2 ADRESL ADCON1 Program Counter's (PC) Least Significant Byte RP1(1) IRP(1) Indirect data memory address pointer Unimplemented Unimplemented Unimplemented PEIE T0IE CCP1IE ULPWUE IRCF1 ANS5 Write buffer upper bits program counter INTE RAIE T0IF INTF C2IE SBODEN IRCF0 TUN4 ANS4 C1IE OSTS(2) TUN3 ANS3 OSFIE TUN2 ANS2 TMR2IE TUN1 ANS1 RAIF TMR1IE TUN0 ANS0 TRISA5 TRISC5 TRISA4 TRISC4 TRISA3 TRISC3 TRISA2 TRISC2 TRISA1 TRISC1 TRISA0 TRISC0 xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx 1111 1111 0000 0000 0000 0000 0000 -110 x000 0000 1111 1111 1111 1111 WPUA4 IOCA4 IOCA3 WPUA2 IOCA2 WPUA1 IOCA1 WPUA0 IOCA0 -111 0000 0-0- 0000 0000 0000 0000 0000 WREN x000 -xxxx xxxx -000 -18,102 12,102 17,102 11,102 18,102 36,102 46,102 17,102 13,102 14,102 16,102 24,103 22,103 83,103 54,103 36,103 37,103 80,103 89,103 89,103 90,103 90,103 83,103 83,103
PIC16F684 SPECIAL FUNCTION REGISTERS SUMMARY BANK
Value POR, Page
Name
EEIE ADIE Unimplemented ANS7 IRCF2 ANS6
Timer2 Module Period Register Unimplemented Unimplemented Unimplemented Unimplemented VREN EEPROM data register EEPROM address register WRERR EEPROM control register (not physical register) WPUA5 IOCA5
Least Significant bits left shifted result bits right shifted result ADCS2 ADCS1 ADCS0
Legend: Note
Unimplemented locations read `0', unchanged, unknown, value depends condition, shaded unimplemented bits reserved, always maintain these bits clear. OSCCON<OSTS> reset with Dual Speed Start-up selected oscillator. pull-up enabled when MCLRE configuration word.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
2.2.2.1 STATUS Register
STATUS register, shown Register 2-1, contains: arithmetic status RESET status bank select bits data memory (SRAM) STATUS register destination instruction, like other register. STATUS register destination instruction that affects bits, then write these three bits disabled. These bits cleared according device logic. Furthermore, bits writable. Therefore, result instruction with STATUS register destination different than intended. example, CLRF STATUS will clear upper three bits bit. This leaves STATUS register 000u u1uu (where unchanged). recommended, therefore, that only BCF, BSF, SWAPF MOVWF instructions used alter STATUS register, because these instructions affect STATUS bits. other instructions affecting STATUS bits, "Instruction Summary". Note Bits (STATUS<7:6>) used PIC16F684 should maintained clear. these bits recommended, since this affect upward compatibility with future products. bits operate Borrow Digit Borrow bit, respectively, subtraction. SUBLW SUBWF instructions examples.
REGISTER 2-1:
STATUS STATUS REGISTER (ADDRESS: 83h)
Reserved Reserved R/W-0 R/W-x R/W-x R/W-x
IRP: This reserved should maintained RP1: This reserved should maintained RP0: Register Bank Select (used direct addressing) Bank (80h FFh) Bank (00h 7Fh) Time-out After power-up, CLRWDT instruction, SLEEP instruction time-out occurred Power-down After power-up CLRWDT instruction execution SLEEP instruction Zero result arithmetic logic operation zero result arithmetic logic operation zero Digit carry/borrow (ADDWF, ADDLW,SUBLW,SUBWF instructions) borrow, polarity reversed. carry-out from order result occurred carry-out from order result Carry/borrow (ADDWF, ADDLW, SUBLW, SUBWF instructions) carry-out from Most Significant result occurred carry-out from Most Significant result occurred Note borrow polarity reversed. subtraction executed adding two's complement second operand. rotate (RRF, RLF) instructions, this loaded with either high order source register.
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
2.2.2.2 OPTION Register
Note: achieve prescaler assignment TMR0, assign prescaler setting (OPTION<3>). Section Prescaler. OPTION register readable writable register, which contains various control bits configure: TMR0/WDT prescaler External RA2/INT interrupt TMR0 Weak pull-ups PORTA
REGISTER 2-2:
OPTION_REG OPTION REGISTER (ADDRESS: 81h)
R/W-1 RAPU R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 R/W-1 R/W-1 R/W-1
RAPU: PORTA Pull-up Enable PORTA pull-ups disabled PORTA pull-ups enabled individual port latch values INTEDG: Interrupt Edge Select Interrupt rising edge RA2/INT Interrupt falling edge RA2/INT T0CS: TMR0 Clock Source Select Transition RA2/T0CKI Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select Increment high-to-low transition RA2/T0CKI Increment low-to-high transition RA2/T0CKI PSA: Prescaler Assignment Prescaler assigned Prescaler assigned Timer0 module PS2:PS0: Prescaler Rate Select bits
VALUE TMR0 RATE RATE
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
2.2.2.3 INTCON Register
Note: Interrupt flag bits when interrupt condition occurs, regardless state corresponding enable global enable bit, (INTCON<7>). User software should ensure appropriate interrupt flag bits clear prior enabling interrupt. INTCON register readable writable register, which contains various enable flag bits TMR0 register overflow, PORTA change external RA2/INT interrupts.
REGISTER 2-3:
INTCON INTERRUPT CONTROL REGISTER (ADDRESS: 8Bh)
R/W-0 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RAIE R/W-0 T0IF R/W-0 INTF R/W-0 RAIF
GIE: Global Interrupt Enable Enables unmasked interrupts Disables interrupts PEIE: Peripheral Interrupt Enable Enables unmasked peripheral interrupts Disables peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable Enables TMR0 interrupt Disables TMR0 interrupt INTE: RA2/INT External Interrupt Enable Enables RA2/INT external interrupt Disables RA2/INT external interrupt RAIE: PORTChange Interrupt Enable bit(1) Enables PORTA change interrupt Disables PORTA change interrupt T0IF: TMR0 Overflow Interrupt Flag bit(2) TMR0 register overflowed (must cleared software) TMR0 register overflow INTF: RA2/INT External Interrupt Flag RA2/INT external interrupt occurred (must cleared software) RA2/INT external interrupt occur RAIF: PORTChange Interrupt Flag When least PORTA <5:0> pins changed state (must cleared software) None PORTA <5:0> pins have changed state Note IOCA register must also enabled. T0IF when Timer0 rolls over. Timer0 unchanged RESET should initialized before clearing T0IF bit.
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
2.2.2.4 PIE1 Register
Note: PEIE (INTCON<6>) must enable peripheral interrupt. PIE1 register contains interrupt enable bits, shown Register 2-4.
REGISTER 2-4:
PIE1 PERIPHERAL INTERRUPT ENABLE REGISTER (ADDRESS: 8Ch)
R/W-0 EEIE R/W-0 ADIE R/W-0 CCP1IE R/W-0 C2IE R/W-0 C1IE R/W-0 OSFIE R/W-0 TMR2IE R/W-0 TMR1IE
EEIE: Write Complete Interrupt Enable Enables write complete interrupt Disables write complete interrupt ADIE: Converter Interrupt Enable Enables converter interrupt Disables converter interrupt CCP1IE: CCP1 Interrupt Enable Enables CCP1 interrupt Disables CCP1 interrupt C2IE: Comparator Interrupt Enable Enables Comparator interrupt Disables Comparator interrupt C1IE: Comparator Interrupt Enable Enables Comparator interrupt Disables Comparator interrupt OSFIE: Oscillator Fail Interrupt Enable Enables Oscillator Fail interrupt Disables Oscillator Fail interrupt TMR2IE: Timer Match Interrupt Enable Enables Timer match interrupt Disables Timer match interrupt TMR1IE: Timer Overflow Interrupt Enable Enables Timer overflow interrupt Disables Timer overflow interrupt Legend: Readable Value Writable Unimplemented bit, read cleared unknown
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
2.2.2.5 PIR1 Register
Note: Interrupt flag bits when interrupt condition occurs, regardless state corresponding enable global enable bit, (INTCON<7>). User software should ensure appropriate interrupt flag bits clear prior enabling interrupt. PIR1 register contains interrupt flag bits, shown Register 2-5.
REGISTER 2-5:
PIR1 PERIPHERAL INTERRUPT REGISTER (ADDRESS: 0Ch)
R/W-0 EEIF R/W-0 ADIF R/W-0 CCP1IF R/W-0 C2IF R/W-0 C1IF R/W-0 OSFIF R/W-0 TMR2IF R/W-0 TMR1IF
EEIF: EEPROM Write Operation Interrupt Flag write operation completed (must cleared software) write operation completed been started ADIF: Interrupt Flag conversion complete conversion completed been started CCP1IF: CCP1 Interrupt Flag Capture mode: TMR1 register capture occurred (must cleared software) TMR1 register capture occurred Compare mode: TMR1 register compare match occurred (must cleared software) TMR1 register compare match occurred mode: Unused this mode C2IF: Comparator Interrupt Flag Comparator output changed (must cleared software) Comparator output changed C1IF: Comparator Interrupt Flag Comparator output changed (must cleared software) Comparator output changed OSFIF: Oscillator Fail Interrupt Flag System oscillator failed, clock input changed INTOSC (must cleared software) System clock operating TMR2IF: Timer Match Interrupt Flag Timer match occurred (must cleared software) Timer match occurred TMR1IF: Timer Overflow Interrupt Flag Timer register overflowed (must cleared software) Timer overflowed Legend: Readable Value Writable Unimplemented bit, read cleared unknown
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
2.2.2.6 PCON Register
Power Control (PCON) register contains flag bits differentiate between Power-on Reset (POR) Brown-out Detect (BOD) Watchdog Timer Reset (WDT) External MCLR Reset
PCON register also controls Ultra Power Wake-up software enable BOD. PCON register bits shown Register 2-6.
REGISTER 2-6:
PCON POWER CONTROL REGISTER (ADDRESS: 8Eh)
R/W-0 ULPWUE R/W-1 SBODEN R/W-0 R/W-x
Unimplemented: Read ULPWUE: Ultra Power Wake-up Enable Ultra Power Wake-up enabled Ultra Power Wake-up disabled SBODEN: Software Enable bit(1) enabled disabled Unimplemented: Read POR: Power-on Reset STATUS Power-on Reset occurred Power-on Reset occurred (must software after Power-on Reset occurs) BOD: Brown-out Detect STATUS Brown-out Detect occurred Brown-out Detect occurred (must software after Brown-out Detect occurs) Note Legend: Readable Value Writable Unimplemented bit, read cleared unknown BODEN<1:0> Configuration Word this control BOD.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
PCLATH
2.3.2 STACK
program counter (PC) 13-bits wide. byte comes from register, which readable writable register. high byte (PC<12:8>) directly readable writable comes from PCLATH. RESET, cleared. Figure shows situations loading upper example Figure shows loaded write (PCLATH<4:0> PCH). lower example Figure shows loaded during CALL GOTO instruction (PCLATH<4:3> PCH). PIC16F684 family 8-level 13-bit wide hardware stack (see Figure 2-1). stack space part either program data space stack pointer readable writable. PUSHed onto stack when CALL instruction executed interrupt causes branch. stack POPed event RETURN, RETLW RETFIE instruction execution. PCLATH affected PUSH operation. stack operates circular buffer. This means that after stack been PUSHed eight times, ninth push overwrites value that stored from first push. tenth push overwrites second push (and on). Note There STATUS bits indicate stack overflow stack underflow conditions. There instructions/mnemonics called PUSH POP. These actions that occur from execution CALL, RETURN, RETLW RETFIE instructions vectoring interrupt address.
FIGURE 2-3:
LOADING DIFFERENT SITUATIONS
INSTRUCTION WITH DESTINATION RESULT
PCLATH<4:0>
PCLATH PCLATH<4:3> OPCODE <10:0> GOTO, CALL
PCLATH
2.3.1
COMPUTED GOTO
computed GOTO accomplished adding offset program counter (ADDWF PCL). When performing table read using computed GOTO method, care should exercised table location crosses memory boundary (each 256-byte block). Refer Application Note "Implementing Table Read" (AN556).
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
Indirect Addressing, INDF Registers
simple program clear location 20h-2Fh using indirect addressing shown Example 2-1. INDF register physical register. Addressing INDF register will cause indirect addressing. Indirect addressing possible using INDF register. instruction using INDF register actually accesses data pointed File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing INDF register indirectly results operation (although STATUS bits affected). effective 9-bit address obtained concatenating 8-bit register (STATUS<7>), shown Figure 2-4.
EXAMPLE 2-1:
movlw movwf clrf incf btfss goto
INDIRECT ADDRESSING
0x20 INDF FSR,4 NEXT ;initialize pointer ;clear INDF register ;inc pointer ;all done? clear next ;yes continue
NEXT
CONTINUE
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING PIC16F684
DIRECT ADDRESSING INDIRECT ADDRESSING IRP(1) REGISTER
RP1(1)
FROM OPCODE
BANK SELECT
LOCATION SELECT
BANK SELECT 180H
LOCATION SELECT
DATA MEMORY
USED
BANK BANK BANK BANK
1FFH
memory detail Figure 2-2. Note bits reserved; always maintain these bits clear.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
OSCILLATOR CONFIGURATIONS
Oscillator Types
TABLE 3-1:
CAPACITOR SELECTION CRYSTAL OSCILLATOR (FOR DESIGN GUIDANCE ONLY)
Crystal Freq Typical Capacitor Values Tested:
PIC16F684 operated eight different oscillator modes. user program three configuration bits (FOSC2:FOSC0) select these eight modes: Power Crystal Crystal/Resonator High Speed Crystal/Resonator External Resistor/Capacitor with FOSC/4 output RCIO External Resistor/Capacitor with INTOSC Internal Oscillator with FOSC/4 output INTOSCIO Internal Oscillator with External Clock with
Type
Capacitor values design guidance only. Different capacitor values required produce acceptable oscillator operation. user should test performance oscillator over expected temperature range application. notes following this table additional information. Note Higher capacitance increases stability oscillator, also increases startup time. Since each crystal characteristics, user should consult crystal manufacturer appropriate values external components. required mode, well mode, avoid overdriving crystals with drive level specification. Always verify oscillator performance over temperature range that expected application.
Crystal Oscillator/Ceramic Resonators
modes, crystal ceramic resonator connected OSC1/CLKI OSC2/CLKO pins establish oscillation (see Figure Figure 3-2). PIC16F684 oscillator design requires parallel crystal. series crystal give frequency crystal manufacturers specifications.
FIGURE 3-1:
CRYSTAL OPERATION (HS, CONFIGURATION)
OSC1
PIC16F684
C1(1) XTAL OSC2 C2(1) RS(2) Internal Logic RF(3) SLEEP
Note
Table typical values series resistor (RS) required strip crystals. varies with crystal chosen (typically between
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
FIGURE 3-2: CERAMIC RESONATOR OPERATION CONFIGURATION)
OSC1 C1(1) OSC2 C2(1) RS(2) Internal Logic RF(3) SLEEP
Oscillator
PIC16F684
Note Table typical values series resistor (RS) required. varies with resonator chosen (typically between
timing insensitive applications, "RC" "RCIO" device options offer additional cost savings. oscillator frequency function supply voltage, resistor (REXT) capacitor (CEXT) values operating temperature. addition this, oscillator frequency will vary from unit unit normal manufacturing variation. Furthermore, difference lead frame capacitance between package types will also affect oscillation frequency, especially CEXT values. user also needs take into account variation tolerance external components used. Figure shows combination connected. Oscillator mode, oscillator frequency divided available OSC2 pin. This signal used test purposes synchronize other logic.
FIGURE 3-4: TABLE 3-2: CERAMIC RESONATORS (FOR DESIGN GUIDANCE ONLY)
Freq 16.0 OSC1 OSC2
REXT
OSCILLATOR MODE
Typical Capacitor Values Used: Mode
CEXT
OSC1
Internal Clock PIC16F684
OSC2/CLKOUT FOSC/4 Recommended values: REXT CEXT
Capacitor values design guidance only. Different capacitor values required produce acceptable oscillator operation. user should test performance oscillator over expected temperature range application.
RCIO Oscillator mode (Figure 3-5) functions like mode, except that OSC2 becomes additional general purpose pin. becomes PORTA (RA4).
FIGURE 3-5:
REXT
RCIO OSCILLATOR MODE
External Clock Input
Oscillator mode requires external clock source connected OSC1 pin. There oscillator start-up time required after Power-on Reset, after exit from SLEEP mode. Oscillator mode, OSC2 becomes additional general purpose pin. becomes PORTA (RA4). Figure shows connections Oscillator mode.
OSC1 CEXT (OSC2)
Internal Clock
PIC16F684
Recommended values: REXT CEXT
FIGURE 3-3:
EXTERNAL CLOCK INPUT OPERATION CONFIGURATION)
OSC1/CLKIN PIC16F684 (OSC2)
Clock from Ext. System
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
Internal Oscillator Block
3.5.2 INTOSC CALIBRATION
PIC16F684 includes oscillator block with independent internal oscillators; calibrated INTOSC MHz) uncalibrated INTRC kHz). INTOSC also drives INTOSC postscaler, which provide range clock frequencies from MHz. Therefore, oscillator block provide following frequencies system clock: kHz, kHz, kHz, kHz, MHz, MHz, MHz. INTRC kHz) oscillator enabled selecting INTRC system clock source, when following enabled: Power-up Timer Watchdog Timer Two-Speed Start-up Fail-Safe Clock Monitor PIC16F684 internal oscillators. INTOSC INTRC oscillator. INTOSC factory calibrated. Section 15.0 Electrical Specifications, information variation over voltage temperature. INTRC uncalibrated. PIC16F684 stores INTOSC calibration values fuses located calibration word (2008h). calibration word erased using specified bulk erase sequence PIC16F684 Programming Specification does require reprogramming. Note: Address 2008h beyond user program memory space. belongs special Configuration Memory space (2000h 3FFFh), which accessed only during programming. PIC16F684 Programming Specification more information.
INTOSC MHz) oscillator enabled selecting INTOSC system clock source, when TwoSpeed Start-up enabled. These features discussed greater detail Section 12.0 Special Features CPU. clock source frequency (INTOSC direct, INTRC direct, INTOSC postscaler) selected configuring IRCF bits OSCCON register. Note: Throughout this data sheet, when referring specifically generic clock source, term "INTOSC" also used refer Clock modes using internal oscillator block. This regardless whether actual frequency used INTOSC MHz), INTOSC postscaler kHz), INTRC kHz).
3.5.3
OSCTUNE REGISTER
internal oscillator's output been calibrated factory, adjusted application. This done writing OSCTUNE register (Register 3-1). OSCTUNE register tuning range ±12%. process variation, monotonicity frequency step specified. When OSCTUNE register modified, INTOSC frequency will begin shifting frequency. OSCTUNE does affect INTRC frequency. INTOSC clock will stabilize within Code execution continues during this shift. There indication that shift occurred. Operation features that depend INTRC clock source frequency, such WDT, Fail-Safe Clock Monitor peripherals, will affected change frequency.
3.5.1
INTOSC MODES
Using internal oscillator clock source eliminate need external oscillator pins, after which used digital I/O. distinct configurations available: INTOSC mode, OSC2 outputs FOSC/4, while OSC1 functions digital input output. INTOSCIO mode, OSC1 functions OSC2 functions RA4, both digital input output.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
REGISTER 3-1: OSCTUNE OSCILLATOR TUNING REGISTER (ADDRESS 90h)
R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0
Unimplemented: Read TUN<4:0>: Frequency Tuning bits 01111 Maximum frequency 01110 00001 00000 Center frequency. Oscillator Module running calibrated frequency. 11111 10000 Minimum frequency Legend: Readable Value
Writable
Unimplemented bit, read cleared unknown
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
Clock Sources Oscillator Switching
3.6.1 OSCCON REGISTER
PIC16F684 includes feature that allows system clock source switched between main oscillator internal clock source. Essentially, there clock sources this device: Primary oscillators Secondary oscillator (i.e., internal oscillator block INTOSC INTRC) Primary Oscillators include external Crystal Resonator modes, external modes, External Clock mode internal oscillator block. mode defined contents configuration word. clock sources PIC16F684 shown Figure 3-6. Section 12.0 Special Features configuration word details. Secondary Oscillator internal oscillator block which comprised independent internal oscillators; uncalibrated INTRC calibrated INTOSC with dedicated postscaler. Note: PIC16F684 uses factory calibrated internal oscillator (INTOSC) postscaler provide system clock frequencies. OSCCON register (Register 3-2) controls several aspects system clock's operation. System Clock Select bit, (SCS) (OSCCON<0>), selects clock source that used. When cleared, system clock source comes from primary oscillator selected FOSC2:FOSC0 bits configuration word. When set, system clock source provided internal oscillator block. After RESET, always cleared. automatic clock switch which occur from Two-Speed Start-up Fail-Safe Clock Monitor does update bit. user monitor OSTS (OSCCON<3>) determine current system clock source. internal oscillator select bits IRCF2:IRCF0 (OSCCON<6:4>) select frequency output internal oscillator block that used drive system clock. choices INTRC source kHz), INTOSC source MHz), frequencies derived from INTOSC postscaler (125 MHz). Note: Following RESET, IRCF bits `110' frequency selection forced MHz. user modify IRCF bits select different frequency.
OSTS, (OSCCON<2>) (OSCCON<1>) bits indicate status primary oscillator, INTOSC INTRC; these bits when their respective oscillators stable. particular, OSTS indicates that Oscillator Start-up Timer timed out.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
REGISTER 3-2: OSCCON OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)
R/W-1 IRCF2 R/W-1 IRCF1 R/W-0 IRCF0 OSTS(1) R/W-0
Unimplemented: Read IRCF<2:0>: Internal Oscillator Frequency Select bits OSTS: Oscillator Start-up Time-out STATUS Device running from primary system clock (FOSC<2:0>) Device running from secondary system clock (INTOSC INTRC) HTS: INTOSC (High Frequency kHz) STATUS INTOSC stable INTOSC stable LTS: INTRC (Low Frequency kHz) Stable INTRC stable INTRC stable SCS: Oscillator Mode Select bits Internal oscillator used system clock Oscillator mode defined FOSC<2:0> Note resets with Two-Speed Start-up selected, Oscillator mode Fail-Safe mode enabled.
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
3.6.2 CLOCK SWITCHING 3.6.3 CLOCK TRANSITION
Clock switching will occur following reasons: Fail-Safe Clock Monitor enabled, device running from primary oscillator (i.e., oscillator defined FOSC<2:0>), primary oscillator fails. clock source will switch secondary clock source, INTOSC. wake-up RESET POR, device configured Two-Speed Start-up Fail-Safe Clock Monitor. device will switch from secondary clock source primary after stabilized. wake-up from SLEEP occurs interrupt wake-up, Two-Speed Start-up FailSafe Clock Monitor enabled, primary clock (OSCCON<0>) clear. clock will switch from secondary primary system clock after Oscillator Startup Timer expires 1024 clocks. modified. IRCF bits modified. more information, Section 12.6.3 Two-Speed Clock Start-up Mode Section 12.6.4 Fail-Safe Clock Monitor. When clock switching performed primary oscillator Watchdog Timer available while Oscillator Start-up Timer active (1024 clocks). This Watchdog Timer Oscillator Start-up Timer sharing same ripple counter. Once clock transition complete, Watchdog Counter re-enabled with Counter Reset. This allows user synchronize Watchdog Timer start execution clock frequency.
Note:
Clock switching will occur primary system clock already configured INTOSC. cleared RESET, therefore, clock switching will occur RESET unless Two-Speed Start-up Fail-Safe Clock Monitor enabled, primary clock
Note:
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
FIGURE 3-6:
OSC2 SLEEP OSC1 Peripherals
PIC16F684 CLOCK DIAGRAM
Primary Oscillator FOSC2:FOSC0,
OSCCON<6:4> Internal Oscillator Block Postscaler Source INTOSC Source INTRC Internal Oscillator
Power-up Timer, WDT, Fail-Safe Clock Monitor
3.6.4
MODIFYING IRCF BITS
IRCF bits modified time, regardless which clock source currently being used system clock. internal oscillator allows users change frequency during time. This achieved modifying IRCF bits OSCCON register. sequence events that occur after IRCF bits modified dependent upon initial final value IRCF bits.
enabled INTRC will already active. INTOSC disabled conserve power cleared.
3.6.4.3
Switch within
different INTOSC frequency selected, there need delay. INTOSC frequency will already stable switch will occur next falling edge frequency. Note: Caution must taken when modifying IRCF bits using instructions. possible modify IRCF bits frequency that specification range; example, 2.0V IRCF MHz).
3.6.4.1
Switch from MHz:
INTRC (IRCF<2:0> 000) running INTOSC (IRCF<2:0> 000) selected, clock switch delay enabled before will set. This delay allows INTOSC start stabilize. switch will occur next falling edge after timer expires. Fail-Safe Clock Monitor disabled, INTRC will disabled conserve power (OSCCON<1>) cleared. Time sensitive code should wait (OSCCON<2>) become before continuing. This monitored ensure that frequency stable before using system clock time critical applications.
3.6.5
CLOCK TRANSITION SEQUENCE
following sequence performed when IRCF bits changed system clock internal oscillator. IRCF bits modified. clock switching circuitry waits falling edge current clock, which point CLKOUT held low. clock switching circuitry then waits next falling edge requested clock, after which switches this clock source updates HTS/LTS appropriate. Oscillator switchover complete.
3.6.4.2
Switch from down
INTOSC (IRCF<2:0> 000) running INTRC (IRCF<2:0> 000) requested, delay enabled before will indicating INTRC stable. switch will occur next falling edge after timer expires. delay will occur Fail-Safe Clock Monitor
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
3.6.6 OSCILLATOR DELAY UPON POWER-UP WAKE-UP
Oscillator Start-up Timer (OST) used ensure that stable system clock provided device. activated following wake-up from SLEEP mode system clock configured Table shows examples where oscillator delay invoked.
TABLE 3-3:
OSCILLATOR DELAY EXAMPLES
Frequency Oscillator Delay Comments INTRC INTOSC INTOSC
Switch From Switch SLEEP/POR SLEEP INTRC kHz) SLEEP/POR INTRC kHz) Note
Following wake-up from SLEEP mode (approx.) POR, start-up invoked allow Start-up become ready code execution. 1024 Clock Cycles (OST) (approx.) Refer Section 3.6.4 Modifying IRCF Bits further details.
start-up delay based System Clock.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
3.6.7 PRIMARY SECONDARY OSCILLATOR SWITCH
When (OSCCON<0>) cleared, clock transition generated system clock already using INTOSC. event will clear OSTS bit, switch system clock from primary system clock determined FOSC<2:0> configuration word, secondary clock, INTOSC, shut down primary system clock conserve power. After changed, frequency stable immediately. appropriate HTS/LTS will when INTOSC/INTRC stable, after approximately There will delay device switches INTRC kHz) Fail-Safe Clock Monitor enabled. After clock switch been executed, OSTS cleared, indicating Power mode, device does from primary system clock. internal clocks held state until next falling edge after INTOSC stable. After delay, clock input clocks released operation resumes (see Figure 3-7).
FIGURE 3-7:
PRIMARY (XT, EXTRC) SECONDARY OSCILLATOR SWITCH
TOSC
OSC1
TINT TSCS
INTOSC
SYSTEM_CLOCK
TDLY
PROGRAM COUNTER Note
TINT maximum. TOSC minimum. TSCS TINT. TDLY TINT.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
3.6.8 SECONDARY PRIMARY OSCILLATOR SWITCH 3.6.8.1 Returning Primary Oscillator Source Sequence
When switching from secondary back primary system clock clearing (OSCCON<0>), sequence events that take place will depend upon value FOSC bits configuration word. primary clock source configured crystal (HS, LP), then transition will take place after 1024 clock cycles. This allows time crystal oscillator power-up stabilize prior switchover. During Oscillator Start-up Time, system clock comes from secondary clock source, INTOSC. OSTS (OSCCON<3>) monitored indicate when switchover complete. Following oscillator start-up time, internal clocks held state until next falling edge clock primary system clock. clock input clocks then released, operation resumes with primary system clock determined FOSC bits (see Figure 3-8). Note: primary system clock either internal delay timer will suspend operation after exiting Secondary Oscillator mode allow stabilize prior code execution. Changing from secondary primary clock source accomplished clearing bit. This sequence events that follows: primary system clock configured then time-out skipped. Skip step primary system clock configured external oscillator (HS, LP), then will active, waiting 1024 clocks primary system clock. device will INTOSC system clock during this time. following device holds system clock device stays until next falling edge primary system clock. Once switch over complete, device begins from primary oscillator. INTOSC INTRC required, unused oscillator will shut down save current. INTRC will disabled being used other function, such WDT, Fail-Safe Clock Monitoring.
FIGURE 3-8:
SECONDARY PRIMARY OSCILLATOR (XT, SWITCH
TINT
INTOSC TOST OSC1 1022 1023 TOSC OSC2 PROGRAM COUNTER SYSTEM CLOCK TSCS
Note TINT maximum. TOSC minimum. TSCS TINT.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
3.6.8.2 Returning Primary Oscillator with RESET
RESET will clear bit. sequence starting primary oscillator following RESET same forms RESET including POR. There transition sequence from secondary primary oscillator. Instead, device will reset state OSCCON register default primary oscillator. sequence events that take place after this will depend upon value FOSC bits configuration register. external oscillator configured crystal (HS, LP), will held state until 1024 clock cycles have transpired primary clock. This necessary because crystal oscillator been powered down (see Figure 3-9). During oscillator start-up time, system clock does come from secondary oscillator, INTOSC. Instruction execution and/or peripheral operation suspended INTOSC disabled. Note: Two-Speed Clock Start-up Fail-Safe Clock Monitor enabled, INTOSC will system clock until Oscillator Start-up Timer timed out. internal delay timer will suspend operation after RESET allow become ready code execution. peripheral clock will held first following exit from low-power. clocks will released next falling edge input system clock. will advance system clock into state following rising edges incoming clock OSC1. extra clock transition required following RESET allow system clock synchronize asynchronous nature RESET source (see Figure 3-10). sequence events follows: device RESET asserted from many sources (WDT, BOR, MCLR, etc.). device resets start-up timer enabled SLEEP mode. device held RESET until start-up time-out complete. primary system clock configured external oscillator (HS, LP), then will active waiting 1024 clocks primary system clock. While waiting device will held RESET. start-up timers parallel. After both start-up timers have timed out, device will wait additional clock cycle instruction execution will begin.
primary system clock either INTOSC, will begin operating first cycle following wake-up event. This means that there oscillator start-up time required because primary clock already stable; however, there delay between wake-up event following
FIGURE 3-9:
INTOSC OSC1
PRIMARY OSCILLATOR AFTER RESET (HS,
TINT
TOST OSC2 TEPU Start-up System Clock Peripheral Clock RESET SLEEP OSTS Program Counter 0000h 0001h 0003h 0004h 0005h TOSC
Note TINT maximum TOSC minimum TEPU
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
FIGURE 3-10:
INTOSC OSC1 OSC2 Start-up System Clock TCPU(2)
PRIMARY OSCILLATOR AFTER RESET (EC, INTOSC)
TINT
MCLR
OSTS Program Counter 0000h 0001h 0002h 0003h 0004h
Note TINT maximum TCPU
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
TABLE 3-4:
Current System Clock
CLOCK SWITCHING MODES
Modified (INTOSC) Delay Next falling edge INTOSC OSTS HTS/LTS 1(1) System Clock INTRC INTOSC INTOSC Postscaler During 1024 clocks, program execution clocked from secondary oscillator until primary oscillator becomes stable. When RESET occurs, there clock transition sequence. Instruction execution and/or peripheral operation suspended unless TwoSpeed Start-up Fail-Safe Clock Monitor enabled, after which INTOSC will system clock until timer expired. Comments INTOSC oscillator frequency dependent upon IRCF bits.
INTOSC
FOSC<2:0> FOSC<2:0> FOSC<2:0>
Next falling edge 1024 Clocks (OST)
INTOSC
(Due RESET)
1024 Clocks (OST)
Note
IRCF<2:0> bits select kHz, will after INTRC stable. IRCF<2:0> bits select MHz, will after INTOSC stable.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
3.6.8.3 Exiting SLEEP
(OSCCON<0>) unaffected SLEEP command. clock source used after exit from SLEEP determined bit. Refer Section 12.6.3 Two-Speed Clock Start-up Mode Section 12.6.4 Fail-Safe Clock Monitor details. Note: user changes just before entering SLEEP mode, system clock used when exiting SLEEP mode could different than system clock used when entering SLEEP mode. example, system clock following instructions executed: SLEEP then clock change event executed. core will continue INTOSC execute SLEEP command. When SLEEP exited, part will resume operation with primary oscillator after expired. OSCCON,SCS
3.6.8.4
`0':
Sequence Events
device held SLEEP until startup time-out complete. primary system clock configured external oscillator (HS, LP), then will active waiting 1024 clocks primary system clock. While waiting OST, device will held SLEEP unless TwoSpeed Start-up Fail-Safe Clock Monitor enabled. start-up timers parallel. After both start-up timers have timed out, device will exit SLEEP begin instruction execution with primary clock defined FOSC bits. device held SLEEP until startup time-out complete. After start-up timer timed out, device will exit SLEEP begin instruction execution with secondary oscillator, INTOSC.
`1':
TABLE 3-5:
Address
2007h(1)
SUMMARY REGISTERS ASSOCIATED WITH OSCILLATORS
Name
EEIF EEIE
ADIF ADIE IRCF2
CCP1IF CCP1IE IRCF1 MCLRE
C2IF C2IE IRCF0 TUN4 PWRTE
C1IF C1IE OSTS(4) TUN3 WDTE
OSFIF OSFIE TUN2 FOSC2
TMR2IF TMR2IE TUN1 F0SC1
TMR1IF TMR1IE TUN0 F0SC0
Value POR,
0000 0000 0000 0000 -110 x000 0000
Value other RESETS
0000 0000 0000 0000 -110 x000 uuuu
PIR1 PIE1 OSCCON OSCTUNE Config bits
Legend: Note
unknown, unchanged, unimplemented locations read '0'. Shaded cells used oscillators. Register 12-1 operation these bits.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
NOTES:
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
PORTS
There many twelve general purpose pins available. Depending which peripherals enabled, some pins available general purpose I/O. general, when peripheral enabled, associated used general purpose pin. Note: Additional information ports found PICmicroMid-Range Reference Manual (DS33023). register maintained when using them analog inputs. pins configured analog input always read `0'. Note: ANSEL (91h) CMCON0 (19h) registers must initialized configure analog channel digital input. Pins configured analog inputs will read `0'.
EXAMPLE 4-1:
clrf movlw movwf clrf movlw movwf STATUS,RP0 PORTA CMCON0 STATUS,RP0 ANSEL TRISA STATUS,RP0
INITIALIZING PORTA
;Bank ;Init PORTA ;Set RA<2:0> ;digital ;Bank ;digital ;Set RA<3:2> inputs ;and RA<5:4,1:0> outputs ;Bank
PORTA TRISA Registers
PORTA 6-bit wide, bidirectional port. corresponding data direction register TRISA. Setting TRISA will make corresponding PORTA input (i.e., corresponding output driver Hi-impedance mode). Clearing TRISA will make corresponding PORTA output (i.e., contents output latch selected pin). exception RA3, which input only TRIS will always read `1'. Example shows initialize PORTA. Reading PORTA register reads status pins, whereas writing will write port latch. write operations read-modify-write operations. Therefore, write port implies that port pins read, this value modified then written port data latch. reads when MCLRE TRISA register controls direction PORTA pins, even when they being used analog inputs. user must ensure bits TRISA
Additional Functions
Every PORTA PIC16F684 interrupton-change option weak pull-up option. Ultra Power Wake-up option. next three sections describe these functions.
4.2.1
WEAK PULL-UPS
Each PORTA pins, except RA3, individually configurable weak internal pull-up. Control bits WPUAx enable disable each pull-up. Refer Register 4-3. Each weak pull-up automatically turned when port configured output. pull-ups disabled Power-on Reset RAPU (OPTION<7>). weak pull-up automatically enabled when configured MCLR disabled when I/O. There software control MCLR pull-up.
REGISTER 4-1:
PORTA PORTA REGISTER (ADDRESS: 05h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
7-6: 5-0:
Unimplemented: Read as'0' PORTA<5:0>: PORTA Port >VIH Port <VIL Legend: Readable Value Writable Unimplemented bit, read cleared unknown
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
REGISTER 4-2: TRISA PORTA TRISTATE REGISTER (ADDRESS: 85h)
7-6: 5-0: Unimplemented: Read TRISA<5:0>: PORTA Tri-State Control PORTA configured input (tri-stated) PORTA configured output Note Legend: Readable Value Writable Unimplemented bit, read cleared unknown TRISA<3> always reads R/W-1 TRISA5 R/W-1 TRISA4 TRISA3 R/W-1 TRISA2 R/W-1 TRISA1 R/W-1 TRISA0
REGISTER 4-3:
WPUA WEAK PULL-UP REGISTER (ADDRESS: 95h)
R/W-1 WPUA5 R/W-1 WPUA4 R/W-1 WPUA2 R/W-1 WPUA1 R/W-1 WPUA0
Unimplemented: Read WPUA<5:4>: Weak Pull-up Register Pull-up enabled Pull-up disabled Unimplemented: Read WPUA<2:0>: Weak Pull-up Register Pull-up enabled Pull-up disabled Note Global RAPU must enabled individual pull-ups enabled. weak pull-up device automatically disabled Output mode (TRISA pull-up enabled when configured MCLR disabled configuration word.
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
4.2.2 INTERRUPT-ON-CHANGE
Each PORTA pins individually configurable interrupt-on-change pin. Control bits IOCAx enable disable interrupt function each pin. Refer Register 4-4. interrupt-on-change disabled Power-on Reset. enabled interrupt-on-change pins, values compared with value latched last read PORTA. `mismatch' outputs last read OR'd together set, PORTA Change Interrupt flag (RAIF) INTCON register. This interrupt wake device from SLEEP. user, Interrupt Service Routine, clear interrupt following manner: read write PORTA. This will mismatch condition. Clear flag RAIF.
mismatch condition will continue flag RAIF. Reading PORTA will mismatch condition allow flag RAIF cleared. latch holding last read value affected MCLR Reset. After these resets, RAIF flag will continue mismatch present. Note: change should occur when read operation being executed (start cycle), then RAIF interrupt flag set.
REGISTER 4-4:
IOCA INTERRUPT-ON-CHANGE PORTA REGISTER (ADDRESS: 96h)
R/W-0 IOCA5 R/W-0 IOCA4 R/W-0 IOCA3 R/W-0 IOCA2 R/W-0 IOCA1 R/W-0 IOCA0
Unimplemented: Read IOCA<5:0>: Interrupt-on-Change PORTA Control Interrupt-on-change enabled Interrupt-on-change disabled Note Global interrupt enable (GIE) must enabled individual interrupts recognized.
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
4.2.3 ULTRA POWER WAKE-UP EXAMPLE 4-2:
Ultra Power Wake-up allows slow falling voltage generate Interrupt-on-change without excess current consumption. mode selected setting ULPWUE (PCON<5>). This enables small current sink which used discharge capacitor RA0. this feature, configured output charge capacitor, Interrupt-on-change enabled, configured input. ULPWUE begin discharge SLEEP instruction performed. When voltage drops below VIL, interrupt will generated which will cause device wake-up. Depending state (INTCON<7>), device will either jump interrupt vector (0004h) execute next instruction when interrupt event occurs. Section 4.2.2 Interrupt-on-change Section 12.4.3 PORTA Interrupt more information. This feature provides power technique periodically waking device from SLEEP. time-out dependent discharge time circuit RA0. Example initializing Ultra Power Wake-up module. series resistor provides over-current protection capacitor allow software calibration time-out. Figure 4-1. timer used measure charge time discharge time capacitor. charge time then adjusted provide desired interrupt delay. This technique will compensate affects temperature, voltage component accuracy. Ultra Power Wake-up peripheral also configured simple Programmable Voltage Detect temperature sensor.
ULTRA POWER WAKE-UP INITIALIZATION
;Bank ;Set data latch ;Turn comparators ;Bank ;RA0 digital ;Output high charge capacitor ;Enable Wake-up ;Select ;RA0 input ;Enable interrupt clear flag ;Wait
movlw movwf call movlw movwf sleep
STATUS,RP0 PORTA,0 H'7' CMCON0 STATUS,RP0 ANSEL,0 TRISA,0 CapDelay PCON,ULPWUE IOCA,0 TRISA,0 B'10001000' INTCON
FIGURE 4-1:
ULTRA POWER WAKE-UP CIRCUIT
PIC16F684
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
4.2.4 DESCRIPTIONS DIAGRAMS FIGURE 4-2: BLOCK DIAGRAM
ANALOG INPUT MODE WEAK RAPU
Each PORTA multiplexed with other functions. pins their combined functions briefly described here. specific information about individual functions such comparator A/D, refer appropriate section this Data Sheet.
DATA WPUA WPUA
4.2.4.1
RA0/AN0/C1IN+/ICSPDAT
Figure shows diagram this pin. configurable function following: general purpose analog input analog input comparator In-Circuit Serial Programming data
PORTA ANALOG INPUT MODE TRISA TRISA PORTA IOCA IOCA
4.2.4.2
RA1/AN1/C1IN-/VREF/ICSPCLK
Figure shows diagram this pin. configurable function following: general purpose analog input analog input comparator voltage reference input In-Circuit Serial Programming clock
INTERRUPT-ONCHANGE PORTA COMPARATOR CONVERTER
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
4.2.4.3 RA2/AN2/T0CKI/INT/C1OUT 4.2.4.4 RA3/MCLR/VPP
Figure shows diagram this pin. configurable function following: general purpose analog input clock input TMR0 external edge triggered interrupt digital output from comparator Figure shows diagram this pin. configurable function following: general purpose input Master Clear Reset weak pull-up
FIGURE 4-4:
BLOCK DIAGRAM
MCLRE WEAK
FIGURE 4-3:
DATA WPUA WPUA
BLOCK DIAGRAM
ANALOG INPUT MODE WEAK RAPU COUT ENABLE ANALOG INPUT MODE TRISA PORTA IOCA IOCA INTERRUPT-ONCHANGE ANALOG INPUT MODE DATA
RESET
MCLRE
INPUT
MCLRE
PORTA
COUT
TRISA TRISA PORTA IOCA IOCA
PORTA
INTERRUPT-ONCHANGE
PORTA
TMR0 CONVERTER
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
4.2.4.5 RA4/AN3/T1G/OSC2/CLKOUT 4.2.4.6 RA5/T1CKI/OSC1/CLKIN
Figure shows diagram this pin. configurable function following: general purpose analog input TMR1 gate input crystal/resonator connection clock output Figure shows diagram this pin. configurable function following: general purpose TMR1 clock input crystal/resonator connection clock input
FIGURE 4-6: FIGURE 4-5: BLOCK DIAGRAM
ANALOG INPUT MODE DATA WPUA WPUA
BLOCK DIAGRAM
INTOSC MODE
CLK(1) MODES WEAK
DATA WPUA WPUA
TMR1LPEN(1) WEAK
RAPU OSCILLATOR CIRCUIT OSC2
RAPU OSCILLATOR CIRCUIT OSC1 CLKOUT ENABLE CLKOUT ENABLE FOSC/4
PORTA TRISA TRISA PORTA
PORTA
INTOSC MODE
INTOSC/ RC/EC(2) CLKOUT ENABLE ANALOG INPUT MODE
TRISA TRISA PORTA
IOCA
IOCA IOCA
IOCA
INTERRUPT-ONCHANGE
INTERRUPT-ONCHANGE CONVERTER
PORTA PORTA TMR1 CLKGEN
Note modes LPTMR1 CLKOUT Enable. With CLKOUT option.
Note
Timer1 Oscillator enabled. When using Timer1 with oscillator, Schmitt Trigger bypassed.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
TABLE 4-1: SUMMARY REGISTERS ASSOCIATED WITH PORTA
Value POR,
xxxx 0000 0000 0000 0000 1111 1111 1111 1111 1111 -111 0000
Addr
Name
Value other RESETS
uuuu 0000 0000 0000 0000 1111 1111 1111 1111 1111 -111 0000
0Bh/8Bh
PORTA INTCON CMCON0 OPTION_REG TRISA ANSEL WPUA IOCA
C2OUT RAPU ANS7
PEIE C1OUT INTEDG ANS6
T0IE C2INV T0CS TRISA5 ANS5 WPUA5 IOCA5
INTE C1INV T0SE TRISA4 ANS4 WPUA4 IOCA4
RAIE TRISA3 ANS3 IOCA3
T0IF TRISA2 ANS2 WPUA2 IOCA2
INTF TRISA1 ANS1 WPUA1 IOCA1
RAIF TRISA0 ANS0 WPUA0 IOCA0
Legend: unknown, unchanged, unimplemented locations read '0'. Shaded cells used PORTA.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
PORTC
4.3.1 RC0/AN4/C2IN+
PORTC general purpose port consisting bidirectional pins. pins configured either digital analog input converter comparator. specific information about individual functions such Enhanced A/D, refer appropriate section this Data Sheet. Note: ANSEL (91h) CMCON0 (19h) registers must initialized configure analog channel digital input. Pins configured analog inputs will read `0'. configurable function following: general purpose analog input Converter analog input comparator
4.3.2
RC1/AN5/C2IN-
configurable function following: general purpose analog input Converter analog input comparator
EXAMPLE 4-3:
clrf movlw movwf clrf movlw movwf STATUS,RP0 PORTC CMCON0 STATUS,RP0 ANSEL TRISC STATUS,RP0
INITIALIZING PORTC
;Bank ;Init PORTC ;Set RC<4,1:0> ;digital ;Bank ;digital ;Set RC<3:2> inputs ;and RC<5:4,1:0> outputs ;Bank
FIGURE 4-7:
DATA
BLOCK DIAGRAM
PORTC
TRISC TRISC PORTC COMPARATORS CONVERTER ANALOG INPUT MODE
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
4.3.3 RC2/AN6/P1D 4.3.5 RC4/C2OUT/P1B
configurable function following: general purpose analog input Converter digital output from Enhanced configurable function following: general purpose digital output from comparator digital output from Enhanced Note: Enabling both C2OUT will cause conflict create unpredictable results. Therefore, C2OUT enabled, ECCP used Half-Bridge Full-Bridge mode vise-versa.
4.3.4
RC3/AN7/P1C
configurable function following: general purpose analog input Converter digital output from Enhanced
FIGURE 4-9:
BLOCK DIAGRAM
FIGURE 4-8:
DATA
BLOCK DIAGRAM
PWMOUT ENABLE ANALOG INPUT MODE
PORT/PERIPHERAL SELECT(1) PERIPHERAL SELECT
DATA PORTC TRISC TRISC PORTC
PORTC
PWMOUT
TRISC TRISC PORTC
ANALOG INPUT MODE
CONVERTER
Note
Port/Peripheral Select signals selects between port data peripheral output.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
4.3.6 RC5/CCP1/P1A
configurable function following: general purpose digital input/output Enhanced
FIGURE 4-10:
DATA
BLOCK DIAGRAM
CCP1OUT ENABLE ANALOG INPUT MODE
PORTC
CCP1OUT
TRISC TRISC PORTC
ANALOG INPUT MODE ENHANCED
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
REGISTER 4-5: PORTC PORTC REGISTER (ADDRESS: 07h)
7-6: 5-0: Unimplemented: Read PORTC<5:0>: General Purpose bits Port >VIH Port <VIL Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
REGISTER 4-6:
TRISC PORTC TRISTATE REGISTER (ADDRESS: 87h)
R/W-1 TRISC5 R/W-1 TRISC4 R/W-1 TRISC3 R/W-1 TRISC2 R/W-1 TRISC1 R/W-1 TRISC0
7-6: 5-0:
Unimplemented: Read TRISC<5:0>: PORTC Tri-State Control PORTC configured input (tri-stated) PORTC configured output Legend: Readable Value Writable Unimplemented bit, read cleared unknown
TABLE 4-2:
Address
SUMMARY REGISTERS ASSOCIATED WITH PORTC
Name
C2OUT ANS7
C1OUT ANS6
C2INV TRISC5 ANS5
C1INV TRISC4 ANS4
TRISC3 ANS3
TRISC2 ANS2
TRISC1 ANS1
TRISC0 ANS0
Value POR,
xxxx 0000 0000 1111 1111 1111
Value other RESETS
uuuu 0000 0000 1111 1111 1111
PORTC CMCON0 TRISC ANSEL
Legend: unknown, unchanged, unimplemented locations read '0'. Shaded cells used PORTC.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
TIMER0 MODULE
Timer0 module timer/counter following features: 8-bit timer/counter Readable writable 8-bit software programmable prescaler Internal external clock select Interrupt overflow from Edge select external clock Counter mode selected setting T0CS (OPTION_REG<5>). this mode, Timer0 module will increment either every rising falling edge RA2/T0CKI. incrementing edge determined source edge (T0SE) control (OPTION_REG<4>). Clearing T0SE selects rising edge. Note: Counter mode specific external clock requirements. Additional information these requirements available Mid-Range Reference PICmicroManual, (DS33023).
Figure block diagram Timer0 module prescaler shared with WDT. Note: Additional information Timer0 module available PICmicroMidRange Reference Manual, (DS33023).
Timer0 Interrupt
Timer0 Operation
Timer mode selected clearing T0CS (OPTION_REG<5>). Timer mode, Timer0 module will increment every instruction cycle (without prescaler). TMR0 written, increment inhibited following instruction cycles. user work around this writing adjusted value TMR0 register.
Timer0 interrupt generated when TMR0 register timer/counter overflows from 00h. This overflow sets T0IF (INTCON<2>). interrupt masked clearing T0IE (INTCON<5>). T0IF must cleared software Timer0 module Interrupt Service Routine before re-enabling this interrupt. Timer0 interrupt cannot wake processor from SLEEP since timer shut-off during SLEEP.
FIGURE 5-1:
CLKOUT FOSC/4)
BLOCK DIAGRAM TIMER0/WDT PRESCALER
Data SYNC Cycles 8-bit Prescaler Flag T0IF Overflow TMR0
T0CKI T0SE
T0CS
WDTE SWDTEN
PS0-PS2 16-bit Prescaler INTRC Watchdog Timer WDTPS<3:0>
Time-out
Note T0SE, T0CS, PSA, PS0-PS2 bits Option register, WDTPS<3:0> bits WDTCON register.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
Using Timer0 with External Clock
small delay least 2TOSC (and small delay ns). Refer electrical specification desired device. When prescaler used, external clock input same prescaler output. synchronization T0CKI, with internal phase clocks, accomplished sampling prescaler output cycles internal phase clocks. Therefore, necessary T0CKI high least 2TOSC (and
Note:
ANSEL (91h) CMCON0 (19h) registers must initialized configure analog channel digital input. Pins configured analog inputs will read `0'.
REGISTER 5-1:
OPTION_REG OPTION REGISTER (ADDRESS: 81h)
R/W-1 RAPU R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 R/W-1 R/W-1 R/W-1
RAPU: PORTA Pull-up Enable PORTA pull-ups disabled PORTA pull-ups enabled individual port latch values WPUA register INTEDG: Interrupt Edge Select Interrupt rising edge RA2/INT Interrupt falling edge RA2/INT T0CS: TMR0 Clock Source Select Transition RA2/T0CKI Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select Increment high-to-low transition RA2/T0CKI Increment low-to-high transition RA2/T0CKI PSA: Prescaler Assignment Prescaler assigned Prescaler assigned Timer0 module PS2:PS0: Prescaler Rate Select bits Value TMR0 Rate Rate(1) Note
dedicated 16-bit postscaler available PIC16F684. Section 12.6 Watchdog Timer (WDT) more information.
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
Prescaler
EXAMPLE 5-2:
8-bit counter available prescaler Timer0 module, postscaler Watchdog Timer. simplicity, this counter will referred "prescaler" throughout this Data Sheet. prescaler assignment controlled software control (OPTION_REG<3>). Clearing will assign prescaler Timer0. Prescale values selectable PS2:PS0 bits (OPTION_REG<2:0>). prescaler readable writable. When assigned Timer0 module, instructions writing TMR0 register (e.g., CLRF MOVWF x.etc.) will clear prescaler. When assigned WDT, CLRWDT instruction will clear prescaler along with Watchdog Timer.
CHANGING PRESCALER (TIMER0WDT)
;Bank ;Clear ;Clear TMR0 prescaler ;Bank
STATUS,RP0 clrwdt clrf TMR0 STATUS,RP0
movlw b'00101111' ;Required desired movwf OPTION_REG PS2:PS0 clrwdt movlw b'00101xxx' ;Set postscaler movwf OPTION_REG desired rate STATUS,RP0 ;Bank
5.4.1
SWITCHING PRESCALER ASSIGNMENT
prescaler assignment fully under software control (i.e., changed fly" during program execution). avoid unintended device RESET, following instruction sequence (Example Example 5-3) must executed when changing prescaler assignment from Timer0 WDT.
change prescaler from TMR0 module, sequence shown Example 5-3. This precaution must taken even disabled.
EXAMPLE 5-3:
clrwdt movlw
CHANGING PRESCALER (WDTTIMER0)
;Clear prescaler ;Bank
STATUS,RP0
movwf
b'xxxx0xxx' ;Select TMR0, prescale, clock source OPTION_REG STATUS,RP0 ;Bank
TABLE 5-1:
Address 0Bh/8Bh Legend:
REGISTERS ASSOCIATED WITH TIMER0
Name Value POR, Value other RESETS
TMR0 INTCON OPTION_REG TRISA
Timer0 Module Register RAPU PEIE INTEDG T0IE T0CS INTE T0SE RAIE T0IF INTF RAIF
xxxx xxxx uuuu uuuu 0000 0000 0000 0000 1111 1111 1111 1111
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111
Unimplemented locations, read `0', unchanged, unknown. Shaded cells used Timer0 module.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
TIMER1 MODULE WITH GATE CONTROL
Timer1 Control register (T1CON), shown Register 6-1, used enable/disable Timer1 select various features Timer1 module. Note: Additional information timer modules available PICmicroMid-Range Reference Manual, (DS33023).
PIC16F684 16-bit timer. Figure shows basic block diagram Timer1 module. Timer1 following features: 16-bit timer/counter (TMR1H:TMR1L) Readable writable Internal external clock selection Synchronous asynchronous operation Interrupt overflow from FFFFh 0000h Wake-up upon overflow (Asynchronous mode) Optional external enable input Selectable gate source; output (T1GSS) Selectable gate polarity (T1GINV) Optional oscillator
FIGURE 6-1:
TIMER1 PIC16F684 BLOCK DIAGRAM
TMR1ON TMR1GE TMR1ON TMR1GE TMR1(1) TMR1H OSCILLATOR TMR1L Comparator Module TMR1 Clock Fosc/4 Internal Clock T1SYNC Prescaler T1CKPS<1:0> TMR1CS T1GSS Synchronize SLEEP input Synchronized clock input T1GINV
flag TMR1IF Overflow
OSC1/T1CKI
OSC2/T1G INTOSC Without CLKOUT T1OSCEN
C2OUT Buffer power type when using osc, high speed type when using T1CKI. Note Timer increments rising edge.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
Timer1 Modes Operation Timer1 Prescaler
Timer1 operate three modes: 16-bit timer with prescaler 16-bit synchronous counter 16-bit asynchronous counter Timer mode, Timer1 incremented every instruction cycle. Counter mode, Timer1 incremented rising edge external clock input T1CKI. addition, Counter mode clock synchronized microcontroller system clock asynchronously. Counter Timer modules, counter/timer clock gated Timer gate, which selected either Comparator output. external clock oscillator needed (and microcontroller using INTOSC CLKOUT), Timer1 oscillator clock source. Note: Counter mode, falling edge must registered counter prior first incrementing rising edge. Timer1 four prescaler options allowing divisions clock input. T1CKPS bits (T1CON<5:4>) control prescale counter. prescale counter directly readable writable; however, prescaler counter cleared upon write TMR1H TMR1L.
Timer1 Gate
Timer1 gate source software configurable output Comparator This allows device directly time external events using analog events using Comparator CMCON1 (Register 9-2) selecting Timer1 gate source. This feature simplify software Delta-Sigma Converter many other applications. more information Delta-Sigma Converters, Microchip site (www.microchip.com). Note: TMR1GE (T1CON<6>) must either C2OUT Timer1 gate source. Register more information selecting Timer1 gate source.
Timer1 Interrupt
Timer1 register pair (TMR1H:TMR1L) increments FFFFh rolls over 0000h. When Timer1 rolls over, Timer1 interrupt flag (PIR1<0>) set. enable interrupt rollover, must these bits: Timer1 interrupt Enable (PIE1<0>) PEIE (INTCON<6>) (INTCON<7>). interrupt cleared clearing TMR1IF Interrupt Service Routine. Note: TMR1H:TTMR1L register pair TMR1IF should cleared before enabling interrupts.
Timer1 gate inverted using T1GINV (T1CON<7>), whether originates from Comparator output. This configures Timer1 measure either active high active time between events.
FIGURE 6-2:
T1CKI when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI when TMR1 Enabled Note Arrows indicate counter increments. Counter mode, falling edge must registered counter prior first incrementing rising edge clock.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
REGISTER 6-1: T1CON TIMER1 CONTROL REGISTER (ADDRESS: 10h)
R/W-0 T1GINV T1GINV: Timer1 Gate Invert Timer1 gate inverted Timer1 gate inverted TMR1GE: Timer1 Gate Enable TMR1ON This ignored TMR1ON Timer1 Timer1 gate active Timer1 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits Prescale Value Prescale Value Prescale Value Prescale Value T1OSCEN: Oscillator Enable Control INTOSC without CLKOUT oscillator active: oscillator enabled Timer1 clock oscillator Else: This ignored T1SYNC: Timer1 External Clock Input Synchronization Control TMR1CS synchronize external clock input Synchronize external clock input TMR1CS This ignored. Timer1 uses internal clock. TMR1CS: Timer1 Clock Source Select External clock from T1CKI rising edge) Internal clock (FOSC/4) TMR1ON: Timer1 Enables Timer1 Stops Timer1 Note T1GINV inverts Timer1 gate logic, regardless source. TMR1GE must either C2OUT, selected T1GSS (CMCON1<1>), Timer1 gate source. R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON TMR1GE T1CKPS1 T1CKPS0 T1OSCEN
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
Timer1 Operation Asynchronous Counter Mode Timer1 Oscillator
control T1SYNC (T1CON<2>) set, external clock input synchronized. timer continues increment asynchronous internal phase clocks. timer will continue during SLEEP generate interrupt overflow, which will wake-up processor. However, special precautions software needed read/write timer (Section 6.5.1 Reading Writing Timer1 Asynchronous Counter Mode). Note: ANSEL (91h) CMCON0 (19h) registers must initialized configure analog channel digital input. Pins configured analog inputs will read `0'. crystal oscillator circuit built-in between pins OSC1 (input) OSC2 (amplifier output). enabled setting control T1OSCEN (T1CON<3>). oscillator power oscillator rated kHz. will continue during SLEEP. primarily intended crystal. Table shows capacitor selection Timer1 oscillator. Timer1 oscillator shared with system oscillator. Thus, Timer1 this mode only when primary system clock derived from internal oscillator. with system oscillator, user must provide software time delay ensure proper oscillator start-up. TRISA5 TRISA4 bits when Timer1 oscillator enabled. read TRISA5 TRISA4 bits read `1'. Note: oscillator requires start-up stabilization time before use. Thus, T1OSCEN should suitable delay observed prior enabling Timer1.
6.5.1
READING WRITING TIMER1 ASYNCHRONOUS COUNTER MODE
Reading TMR1H TMR1L while timer running from external asynchronous clock will ensure valid read (taken care hardware). However, user should keep mind that reading 16-bit timer 8-bit values itself, poses certain problems, since timer overflow between reads. writes, recommended that user simply stop timer write desired values. write contention occur writing timer registers, while register incrementing. This produce unpredictable value timer register. Reading 16-bit value requires some care. Examples PICmicroMid-Range Family Reference Manual (DS33023) show read write Timer1 when running Asynchronous mode.
Timer1 Operation During SLEEP
Timer1 only operate during SLEEP when setup Asynchronous Counter mode. this mode, external crystal clock source used increment counter. setup timer wake device: Timer1 must (T1CON<0>) TMR1IE (PIE1<0>) must PEIE (INTCON<6>) must device will wake-up overflow. (INTCON<7>) set, device will wake-up jump Interrupt Service Routine (0004h) overflow. clear, execution will continue with next instruction.
TABLE 6-1:
Addr 0Bh/ Name INTCON PIR1 TMR1L TMR1H T1CON CMCON1 PIE1
REGISTERS ASSOCIATED WITH TIMER1
EEIF
PEIE
ADIF
T0IE
CCP1IF
INTE
C2IF
RAIE
C1IF
T0IF
OSFIF
INTF
TMR2IF
RAIF
TMR1IF
Value POR,
Value other RESETS
0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding Register Least Significant Byte 16-bit TMR1 Register Holding Register Most Significant Byte 16-bit TMR1 Register
EEIE
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
ADIE
CCP1IE
C2IE
C1IE
OSFIE
T1GSS
TMR2IE
C2SYNC
TMR1IE
0000 0000 0000 0000
Legend:
unknown, unchanged, unimplemented, read '0'. Shaded cells used Timer1 module.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
TIMER2 MODULE
Timer2 Operation
Timer2 module timer following features: 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 1:16) Interrupt TMR2 match with
Timer2 control register shown Register 7-1. TMR2 shut-off clearing control TMR2ON (T2CON<2>) minimize power consumption. Figure simplified block diagram Timer2 module. prescaler postscaler selection Timer2 controlled this register.
Timer2 used time-base mode ECCP module. TMR2 register readable writable, cleared device RESET. input clock (FOSC/4) prescale option 1:1, 1:16, selected control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). match output TMR2 goes through 4-bit postscaler (which gives 1:16 scaling inclusive) generate TMR2 interrupt (latched flag TMR2IF, (PIR1<1>)). prescaler postscaler counters cleared when following occurs: write TMR2 register write T2CON register device RESET (Power-on Reset, MCLR Reset, Watchdog Timer Reset, Brown-out Reset) TMR2 cleared when T2CON written.
REGISTER 7-1:
T2CON TIMER2 CONTROL REGISTER (ADDRESS: 12h)
R/W-0 TOUTPS3 R/W-0 TOUTPS2 R/W-0 TOUTPS1 R/W-0 R/W-0 R/W-0 R/W-0 T2CKPS0 TOUTPS0 TMR2ON T2CKPS1
Unimplemented: Read TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 =1:1 Postscale 0001 =1:2 Postscale 1111 =1:16 Postscale TMR2ON: Timer2 =Timer2 =Timer2 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits =Prescaler =Prescaler =Prescaler Legend: Readable Value Writable Unimplemented bit, read cleared unknown
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
Timer2 Interrupt
Timer2 module 8-bit period register, PR2. Timer2 increments from until matches then resets next increment cycle. readable writable register. register initialized upon RESET.
FIGURE 7-1:
TIMER2 BLOCK DIAGRAM
TMR2 Output Sets Flag TMR2IF
FOSC/4
Prescaler 1:1, 1:4, 1:16 T2CKPS1:T2CKPS0
TMR2 Comparator
RESET
Postscaler 1:16
TOUTPS3:TOUTPS0
TABLE 7-1:
Addr 0Bh/ Name INTCON PIR1 TMR2 T2CON PIE1
REGISTERS ASSOCIATED WITH TIMER2
EEIF
PEIE
ADIF
T0IE
CCP1IF
INTE
C2IF
RAIE
C1IF
T0IF
OSFIF
INTF
TMR2IF
RAIF
TMR1IF
Value POR,
Value other RESETS
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Holding Register 8-bit TMR2 Register
EEIE TOUTPS3 TOUTPS2 ADIE CCP1IE TOUTPS1 C2IE TOUTPS0 C1IE OSFIE TMR2IE TMR1IE
TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
0000 0000 0000 0000 1111 1111 1111 1111
Timer2 Module Period Register
Legend:
unknown, unchanged, unimplemented, read '0'. Shaded cells used Timer2 module.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
NOTES:
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE
controls operation ECCP. special event trigger generated compare match will clear both TMR1H TMR1L registers.
enhanced Capture/Compare/PWM (ECCP) module contains 16-bit register which operate 16-bit Capture register 16-bit Compare register Master/Slave Duty Cycle register Capture/Compare/PWM Register1 (CCPR1) comprised 8-bit registers: CCPR1L (low byte) CCPR1H (high byte). CCP1CON register
TABLE 8-1:
ECCP MODE TIMER RESOURCES REQUIRED
Timer Resource Timer1 Timer1 Timer2
ECCP Mode Capture Compare
REGISTER 8-1:
CCP1CON ENHANCED OPERATION REGISTER (ADDRESS: 15h)
R/W-0 P1M1 R/W-0 P1M0 R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0
P1M1:P1M0: Output Configuration bits CCP1M<3:2> assigned Capture/Compare input; P1B, P1C, assigned port pins CCP1M<3:2> Single output; modulated; P1B, P1C, assigned port pins Full-bridge output forward; modulated; active; P1B, inactive Half-bridge output; P1A, modulated with dead band control; P1C, assigned port pins Full-bridge output reverse; modulated; active; P1A, inactive DC1B1:DC1B0: Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused mode: These bits LSbs duty cycle. eight MSbs found CCPR1L. CCP1M3:CCP1M0: ECCP Mode Select bits 0000 Capture/Compare/PWM (resets ECCP module) 0001 Unused (reserved) 0010 Compare mode, toggle output match (CCP1IF set) 0011 Unused (reserved) 0100 Capture mode, every falling edge 0101 Capture mode, every rising edge 0110 Capture mode, every rising edge 0111 Capture mode, every 16th rising edge 1000 Compare mode, output match (CCP1IF set) 1001 Compare mode, clear output match (CCP1IF set) 1010 Compare mode, generate software interrupt match (CCP1IF set, CCP1 unaffected) 1011 Compare mode, trigger special event (CCP1IF set; CCP1 resets TMR1or TMR2, starts conversion, module enabled) 1100 mode; P1A, active high; P1B, active high 1101 mode; P1A, active high; P1B, active 1110 mode; P1A, active low; P1B, active high 1111 mode; P1A, active low; P1B, active Legend: Readable Value
Writable
Unimplemented bit, read cleared unknown
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
Capture Mode
8.1.4 ECCP PRESCALER
Capture mode, CCPR1H:CCPR1L captures 16-bit value TMR1 register when event occurs RC5/CCP1/P1A. event defined following configured CCP1CON<3:0>: Every falling edge Every rising edge Every rising edge Every 16th rising edge There four prescaler settings specified bits CCP1M3:CCP1M0 (CCP1CON<3:0>). Whenever ECCP module turned off, ECCP module Capture mode, prescaler counter cleared. RESET will clear prescaler counter. Switching from capture prescaler another generate interrupt. Also, prescaler counter will cleared, therefore, first capture from non-zero prescaler. Example shows recommended method switching between capture prescalers. This example also clears prescaler counter will generate "false" interrupt.
When capture made, interrupt request flag CCP1IF (PIR1<5>) set. interrupt flag must cleared software. another capture occurs before value register CCPR1 read, captured value overwritten captured value.
EXAMPLE 8-1:
CLRF MOVLW
8.1.1
CCP1 CONFIGURATION
CHANGING BETWEEN CAPTURE PRESCALERS
Capture mode, RC5/CCP1/P1A should configured input setting TRISC<5> bit. Note: RC5/CCP1/P1A configured output, write port cause capture condition.
MOVWF
CCP1CON ;Turn ECCP module NEW_CAPT_PS ;Load with ;the prescaler ;move value ECCP CCP1CON ;Load CCP1CON with this ;value
FIGURE 8-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Flag CCP1IF (PIR1<5>)
Prescaler RC5/CCP1/P1A
CCPR1H Capture Enable TMR1H CCP1CON<3:0>
CCPR1L
Edge Detect
TMR1L
8.1.2
TIMER1 MODE SELECTION
Timer1 must running Timer mode Synchronized Counter mode ECCP module capture feature. Asynchronous Counter mode, capture operation work.
8.1.3
SOFTWARE INTERRUPT
When Capture mode changed, false capture interrupt generated. user should keep CCP1IE (PIE1<5>) clear avoid false interrupts should clear flag CCP1IF following such change operating mode.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
Compare Mode
8.2.1 CCP1 CONFIGURATION
Compare mode, 16-bit CCPR1 register value constantly compared against TMR1 register pair value. When match occurs, RC5/CCP1/P1A Driven high Driven Remains unchanged action based value control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). same time, interrupt flag CCP1IF (PIR1<5>) set. user must configure RC5/CCP1/P1A output clearing TRISC<5> bit. Note: Clearing CCP1CON register will force RC5/CCP1/P1A compare output latch default level. This PORTC data latch.
8.2.2
TIMER1 MODE SELECTION
FIGURE 8-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCP1CON<3:0> Mode Select Flag CCP1IF (PIR1<5>) CCPR1H CCPR1L Output Logic Comparator TMR1H TMR1L
Timer1 must running Timer mode Synchronized Counter mode ECCP module using compare feature. Asynchronous Counter mode, compare operation work.
8.2.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode chosen (CCP1M<3:0> 1010), CCP1 affected. CCP1IF (PIR1<5>) set, causing ECCP interrupt enabled). Register 8-1.
RC5/CCP1/P1A
8.2.4
SPECIAL EVENT TRIGGER
Match
this mode (CCP1M<3:0> 1011), internal hardware trigger generated, which used initiate action. Register 8-1. special event trigger output ECCP resets TMR1 register pair. This allows CCPR1 register effectively 16-bit programmable period register Timer1. special event trigger output also starts conversion module enabled). Note: special event trigger from ECCP module will interrupt flag TMR1IF (PIR1<0>).
TRISC<5> Output Enable Special Event Trigger Special Event Trigger will:
clear TMR1H TMR1L registers interrupt flag TMR1F (PIR1<0>) GO/DONE (ADCON0<1>)
TABLE 8-2:
Addr 0Bh/
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1
EEIF
Name INTCON PIR1 TMR1L TMR1H T1CON CMCON1
CCPR1L CCPR1H CCP1CON TRISC
PEIE
ADIF
T0IE
CCP1IF
INTE
C2IF
RAIE
C1IF
T0IF
OSFIF
INTF
TMR2IF
RAIF
TMR1IF
Value POR,
Value other RESETS
0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding Register Least Significant Byte 16-bit TMR1 Register Holding Register Most Significant Byte 16-bit TMR1 Register
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu T1GSS C2SYNC
xxxx xxxx xxxx xxxx CCP1M3 TRISC3 C1IE CCP1M2 TRISC2 OSFIE CCP1M1 TRISC1 TMR2IE CCP1M0 TRISC0 TMR1IE 0000 0000 1111
Capture/Compare/PWM Register1 Byte Capture/Compare/PWM Register1 High Byte P1M1 EEIE P1M0 ADIE DC1B1 TRISC5 CCP1IE DC1B0 TRISC4 C2IE
uuuu uuuu uuuu uuuu 0000 0000
1111
PIE1
0000 0000 0000 0000
Legend:
Unimplemented locations, read `0', unchanged, unknown. Shaded cells used Capture, Compare Timer1 module.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
Enhanced Mode
Enhanced module produces 10-bit resolution output have four outputs, depending selected operating mode. These outputs, designated through P1D, multiplexed with pins PORTC. assignments summarized Table 8-3. Figure shows simplified block diagram operation. configure pins outputs, proper mode must selected setting P1M1:P1M0 CCP1M3:CCP1M0 bits (CCP1CON<7:6> CCP1CON<3:0>, respectively). appropriate TRISC bits must also outputs.
FIGURE 8-3:
Duty Cycle Registers CCPR1L
SIMPLIFIED BLOCK DIAGRAM ENHANCED MODULE
CCP1CON<5:4> P1M<1:0> CCP1M<3:0>
CCP1/P1A TRISC<5> CCPR1H (Slave) Output Controller Comparator Clear Timer2, toggle latch duty cycle PWM1CON TRISC<2> TRISC<3> TRISC<4>
RC5/CCP1/P1A
RC4/C2OUT/P1B
Comparator
RC3/AN7/P1C
TMR2
RC2/AN6/P1D
Note
8-bit timer TMR2 register concatenated with 2-bit internal clock, bits prescaler create 10-bit time-base.
8.3.1
OUTPUT CONFIGURATIONS
P1M1:P1M0 bits CCP1CON register allows four configurations: Single Output Half-Bridge Output Full-Bridge Output, Forward mode Full-Bridge Output, Reverse mode
general relationship outputs configurations summarized Figure 8-3. Note: Clearing CCP1CON register will force output latches their default inactive levels. This PORTC data latch.
TABLE 8-3:
ASSIGNMENTS VARIOUS ENHANCED MODES
CCP1CON Configuration 00xx11xx 10xx11xx x1xx11xx CCP1 RC4/C2OUT RC3/AN7 RC3/AN7 RC2/AN6 RC2/AN6
ECCP Mode Compatible Dual Quad Legend: Note
Don't care. Shaded cells indicate assignments used ECCP given mode. TRIS register values must configured appropriately. With ECCP Dual Quad mode, C2OUT output control PORTC must disabled.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
8.3.2 PERIOD
output (Figure Figure 8-5) timebase (period) time that output active (duty cycle). period specified writing register. period calculated using following formula: following equation used calculate duty cycle time:
EQUATION 8-2:
duty cycle CCPR1L:CCP1CON<5:4> (TMR2 prescale value) When CCPR1H 2-bit latch match TMR2, concatenated with internal 2-bit clock bits TMR2 prescaler, appropriate toggled. Dual mode, will toggled after dead band time expired. polarity (active high active low) mode signal configured P1M1:P1M0 (CCP1CON<7:6>) CCP1M3:CCP1M0 (CCP1CON<3:0>) bits. maximum resolution given frequency given formula:
EQUATION 8-1:
period (TMR2 prescale value) frequency defined [PWM period]. When TMR2 equal PR2, following three events occur next increment cycle: TMR2 cleared appropriate toggles. Dual mode, this occurs after dead band delay expires (exception: duty cycle will set) duty cycle latched from CCPR1L into CCPR1H Note: Timer2 postscaler (see Section Timer2 Operation) used determination frequency. postscaler could used have servo update rate different frequency than output.
EQUATION 8-3:
bits Resolution control registers double buffered loaded beginning cycle (the period boundary when Timer2 resets) order prevent glitches outputs. exception delay register, which loaded either duty cycle boundary period boundary (whichever comes first). Because buffering, module waits until timer resets, instead starting immediately. This means that enhanced waveforms exactly match standard waveforms, instead offset full instruction cycle TOSC). Note: duty cycle value longer than period, assigned pin(s) will remain unchanged.
8.3.3
DUTY CYCLE
duty cycle specified writing CCPR1L register DC1B1:DB1B0 (CCP1CON<5:4>) bits. bits resolution available. CCPR1L contains eight MSbs DC1B1:DB1B0 contains LSbs. CCPR1L DC1B1:DB1B0 written time. mode, CCPR1H read-only register. This 10bit value represented CCPR1L:CCP1CON<5:4>.
TABLE 8-4:
EXAMPLE FREQUENCIES RESOLUTIONS (FOSC MHz)
1.22 kHz(1) 0xFF 4.88 kHz(1) 0xFF 19.53 0xFF 78.12 0x3F 156.3 0x1F 208.3 0x17
Frequency Timer Prescale Value Maximum Resolution (bits)
Note When calculating resolution, additional bits resolution accounted Timer2 prescale value.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
FIGURE 8-4:
CCP1CON <7:6>
OUTPUT RELATIONSHIPS (ACTIVE HIGH STATE)
SIGNAL Duty Cycle Period MODULATED Delay(1) MODULATED Delay(1) PR2+1
(SINGLE OUTPUT)
(Half-Bridge)
MODULATED ACTIVE
(Full-Bridge, Forward)
INACTIVE INACTIVE MODULATED INACTIVE
(Full-Bridge, Reverse)
MODULATED ACTIVE INACTIVE
Relationships: Period TOSC (PR2 (TMR2 prescale value) Duty Cycle TOSC (CCPR1L<7:0>:CCP1CON<5:4>) (TMR2 prescale value) Delay TOSC (PWM1CON<6:0>) Note Dead band delay programmed using PWM1CON register (Section 8.3.6 Programmable Dead Band Delay).
FIGURE 8-5:
CCP1CON <7:6>
OUTPUT RELATIONSHIPS (ACTIVE STATE)
SIGNAL Duty Cycle Period
MODULATED MODULATED
PR2+1
(SINGLE OUTPUT)
(Half-Bridge)
Delay(1)
Delay(1)
MODULATED ACTIVE
(Full-Bridge, Forward)
INACTIVE INACTIVE MODULATED INACTIVE
(Full-Bridge, Reverse)
MODULATED ACTIVE INACTIVE
Relationships: Period TOSC (PR2 (TMR2 prescale value) Duty Cycle TOSC (CCPR1L<7:0>:CCP1CON<5:4>) (TMR2 prescale value) Delay TOSC (PWM1CON<6:0>) Note Dead band delay programmed using PWM1CON register (Section 8.3.6 Programmable Dead Band Delay).
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
8.3.4 HALF-BRIDGE MODE
Half-Bridge Output mode, pins used outputs drive push-pull loads. output signal output RC5/CCP1/P1A pin, while complementary output signal output RC4/ C2OUT/P1B (Figure 8-6). This mode used half-bridge applications, shown Figure 8-7, full-bridge applications, where four power switches being modulated with signals. Half-Bridge Output mode, programmable dead band delay used prevent shoot-through current half-bridge power devices. value bits PDC6:PDC0 (PWM1CON<6:0>) sets number instruction cycles before output driven active. value greater than duty cycle, corresponding output remains inactive during entire cycle. Section 8.3.6 Programmable Dead Band Delay more details dead band delay operations. Since outputs multiplexed with PORTC<5:4> data latches, TRISC<5:4> bits must cleared configure outputs.
FIGURE 8-6:
Period Duty Cycle P1A(2) P1B(2)
HALF-BRIDGE OUTPUT
Period
Dead Band Delay Note this time, TMR2 register equal register. Output signals shown active high.
FIGURE 8-7:
EXAMPLES HALF-BRIDGE APPLICATIONS
Standard Half-Bridge Circuit ("Push-Pull") Driver PIC16F684 Driver
Load
Half-Bridge Output Driving Full-Bridge Circuit
Driver PIC16F684 Load
Driver
Driver
Driver
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
8.3.5 FULL-BRIDGE MODE
Full-Bridge Output mode, four pins used outputs; however, only outputs active time. Forward mode, RC5/CCP1/P1A continuously active RC2/AN6/P1D modulated. Reverse mode, RC3/AN7/P1C continuously active RC4/C2OUT/P1B modulated. These illustrated Figure 8-8. P1A, P1B, outputs multiplexed with PORTC<5:2> data latches. TRISC<5:2> bits must cleared make P1A, P1B, P1C, pins output.
FIGURE 8-8:
FORWARD MODE
FULL-BRIDGE OUTPUT
Period
Duty Cycle P1B(2) P1C(2)
P1D(2) REVERSE MODE Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2)
Note this time, TMR2 register equal register. Note Output signal shown active high.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
FIGURE 8-9: EXAMPLE FULL-BRIDGE APPLICATION
Driver
Driver
PIC16F684 Driver
Load Driver
VP1D
8.3.5.1
Direction Change Full-Bridge Mode
Full-Bridge Output mode, P1M1 (CCP1CON<7>) allows user control Forward/ Reverse direction. When application firmware changes this direction control bit, module will assume direction next cycle. Just before current period, modulated outputs (P1B P1D) placed their inactive state, while unmodulated outputs (P1A P1C) switched drive opposite direction. This occurs time interval TOSC*(Timer2 Prescale value)) before next period begins. Timer2 prescaler will either depending value T2CKPS1:0 bits (T2CON<1:0>). During interval from switch unmodulated outputs beginning next period, modulated outputs (P1B P1D) remain inactive. This relationship shown Figure 8-10. Note that Full-Bridge Output mode, ECCP module does provide dead band delay. general, since only output modulated times, dead band delay required. However, there situation where dead band delay might required. This situation occurs when both following conditions true: direction output changes when duty cycle output near 100%. turn time power switch, including power device driver circuit, greater than turn time.
Figure 8-11 shows example where direction changes from forward reverse, near 100% duty cycle. time output become inactive, while output becomes active. this example, since turn time power devices longer than turn time, shoot-through current flow through power devices (see Figure 8-9) duration `t'. same phenomenon will occur power devices direction change from reverse forward. changing direction high duty cycle required application, following requirements must met: Reduce duty cycle period before changing directions. switch drivers that drive switches faster than they drive them
Other options prevent shoot-through current exist.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
FIGURE 8-10:
SIGNAL
DIRECTION CHANGE
Period(1) Period
(Active High) (Active High) (Active High) (Active High) Note direction ECCP Control Register (CCP1CON<7>) written time during cycle. When changing directions, signals switch before current cycle intervals TOSC, TOSC TOSC, depending Timer2 prescaler value. modulated signals inactive this time.
FIGURE 8-11:
DIRECTION CHANGE NEAR 100% DUTY CYCLE
Forward Period Reverse Period
External Switch toff External Switch Potential Shoot-Through Current Note signals shown active high. turn delay power switch driver. toff turn delay power switch driver. toff
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
8.3.6 PROGRAMMABLE DEAD BAND DELAY
half-bridge applications where power switches modulated frequency times, power switches normally require more time turn than turn both upper lower power switches switched same time (one turned other turned off), both switches short period time until switch completely turns off. During this brief interval, very high current (shootthrough current) flow through both power switches, shorting bridge supply. avoid this potentially destructive shoot-through current from flowing during switching, turning either power switches normally delayed allow other switch completely turn off. Half-Bridge Output mode, digitally programmable dead band delay available avoid shootthrough current from destroying bridge power switches. delay occurs signal transition from non-active state active state. Figure illustration. lower seven bits PWM1CON register (Register 8-2) sets delay period terms microcontroller instruction cycles (TCY TOSC). ately places enhanced output pins into defined shutdown state when shutdown event occurs. shutdown event caused either comparators combination these three sources). comparators used monitor voltage input proportional current being monitored bridge circuit. voltage exceeds threshold, comparator switches state triggers shutdown. Alternatively, digital signal also trigger shutdown. auto-shutdown feature disabled selecting auto-shutdown sources. auto-shutdown sources used selected using ECCPAS2:ECCPAS0 bits (ECCPAS<6:4>). When shutdown occurs, output pins asynchronously placed their shutdown states, specified PSSAC1:PSSAC0 PSSBD1:PSSBD0 bits (ECCPAS<3:0>). Each pair (P1A/P1C P1B/P1D) drive high, drive low, tristated (not driving). ECCPASE (ECCPAS<7>) also hold enhanced outputs their shutdown states. ECCPASE hardware when shutdown event occurs. automatic restarts enabled, ECCPASE cleared firmware when cause shutdown clears. automatic restarts enabled, ECCPASE automatically cleared when cause auto-shutdown cleared. Section 8.3.7.1 Auto-Shutdown Automatic Restart more information.
8.3.7
ENHANCED AUTO-SHUTDOWN
When ECCP programmed enhanced modes, active output pins configured auto-shutdown. auto-shutdown immedi-
REGISTER 8-2:
PWM1CON CONFIGURATION REGISTER (ADDRESS: 16h)
R/W-0 PRSEN R/W-0 PDC6 R/W-0 PDC5 R/W-0 PDC4 R/W-0 PDC3 R/W-0 PDC2 R/W-0 PDC1 R/W-0 PDC0
PRSEN: Restart Enable Upon auto-shutdown, ECCPASE clears automatically once shutdown event goes away; restarts automatically. Upon auto-shutdown, ECCPASE must cleared software restart PWM. PDC<6:0>: Delay Count bits Number FOSC/4 (4*TOSC) cycles between scheduled time when signal should transition active, actual time transitions active. Legend: Readable Value Writable Unimplemented bit, read cleared unknown
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
REGISTER 8-3: ECCPAS ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER (ADDRESS: 17h)
R/W-0 ECCPASE: ECCP Auto-Shutdown Event STATUS shutdown event occurred; ECCP outputs shutdown state ECCP outputs operating ECCPAS<2:0>: ECCP Auto-Shutdown Source Select bits Auto-shutdown disabled Comparator output change Comparator output change Either Comparator change Comparator change Comparator change Comparator Comparator change PSSACn: Shutdown State Control bits Drive Pins Drive Pins Pins tri-state PSSBDn: Shutdown State Control bits Drive Pins Drive Pins Pins tri-state Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 R/W-0 R/W-0 R/W-0 PSSAC1 R/W-0 PSSAC0 R/W-0 PSSBD1 R/W-0 PSSBD0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
8.3.7.1 Auto-Shutdown Automatic Restart 8.3.8 START-UP CONSIDERATIONS
auto-shutdown feature configured allow automatic restarts module following shutdown event. This enabled setting PRSEN PWM1CON register (PWM1CON<7>). Shutdown mode with PRSEN (Figure 8-12), ECCPASE will remain long cause shutdown continues. When shutdown condition clears, ECCPASE cleared. PRSEN (Figure 8-13), once shutdown condition occurs, ECCPASE will remain until cleared firmware. Once ECCPASE cleared, enhanced will resume beginning next period. Note: Writing ECCPASE disabled while shutdown condition active. When ECCP module used mode, application hardware must proper external pullup and/or pull-down resistors output pins. When microcontroller released from RESET, pins high-impedance state. external circuits must keep power switch devices state, until microcontroller drives pins with proper signal levels, activates output(s). CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow user choose whether output signals active high active each pair output pins (P1A/P1C P1B/P1D). output polarities must selected before pins configured outputs. Changing polarity configuration while pins configured outputs recommended since result damage application circuits. P1A, P1B, output latches proper states when module initialized. Enabling pins output same time ECCP module cause damage application circuit. ECCP module must enabled proper Output mode complete full cycle before configuring pins outputs. completion full cycle indicated TMR2IF being second period begins.
Independent PRSEN setting, whether auto-shutdown source comparators INT, shutdown condition level. ECCPASE cannot cleared long cause shutdown persists. Auto-shutdown mode forced writing ECCPASE bit.
FIGURE 8-12:
Shutdown Event ECCPASE Activity
AUTO-SHUTDOWN (PRSEN AUTO RESTART ENABLED)
Period
Normal Start Period Shutdown Shutdown Event Occurs Event Clears Resumes
FIGURE 8-13:
AUTO-SHUTDOWN (PRSEN AUTO RESTART DISABLED)
Period
Shutdown Event ECCPASE Activity Normal Start Period ECCPASE Cleared Shutdown Shutdown Firmware Event Occurs Event Clears Resumes
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
8.3.9 OPERATION SLEEP MODE 8.3.11 SETUP OPERATION
SLEEP mode, clock sources disabled. Timer2 will increment, state module will change. ECCP driving value, will continue drive that value. When device wakes will continue from this state. following steps should taken when configuring ECCP module operation: Configure pins (and P1D, used) inputs setting corresponding TRISC bits. period loading register. Configure ECCP module desired mode configuration loading CCP1CON register with appropriate values: Select available output configurations direction with P1M1:P1M0 bits. Select polarities output signals with CCP1M3:CCP1M0 bits. duty cycle loading CCPR1L register CCP1CON<5:4> bits. Half-Bridge Output mode, dead band delay loading PWM1CON<6:0> with appropriate value. auto-shutdown operation required, load ECCPAS register: Select auto-shutdown sources using ECCPAS<2:0> bits. Select shutdown states output pins using PSSAC1:PSSAC0 PSSBD1:PSSBD0 bits. ECCPASE (ECCPAS<7>). Configure comparators using CMCON0 register. Configure comparator inputs analog inputs. auto-restart operation required, PRSEN (PWM1CON<7>). Configure start TMR2: Clear TMR2 interrupt flag clearing TMR2IF (PIR1<1>). TMR2 prescale value loading T2CKPS bits (T2CON<1:0>). Enable Timer2 setting TMR2ON (T2CON<2>). Enable outputs after cycle started: Wait until TMR2 overflows (TMR2IF set). Enable CCP1/P1A, P1B, and/or outputs clearing respective TRISC bits. Clear ECCPASE (ECCPAS<7>).
8.3.9.1
OPERATION WITH FAIL-SAFE CLOCK MONITOR
Fail-Safe Clock Monitor enabled, clock failure will force ECCP clocked from internal oscillator clock source, which have different clock frequency than primary clock. Section additional details. Oscillator Configurations
8.3.10
EFFECTS RESET
RESET will force ports Input mode ECCP registers their RESET states. This forces Enhanced module reset state compatible with standard module.
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
TABLE 8-5:
Addr
0Bh/
REGISTERS ASSOCIATED WITH TIMER2
EEIF
Name
INTCON PIR1 TMR2 T2CON CCPR1L CCPR1H CCP1CON PWM1CON ECCPAS TRISC PIE1
PEIE ADIF
T0IE CCP1IF
INTE C2IF
RAIE C1IF
T0IF OSFIF
INTF TMR2IF
RAIF TMR1IF
Value POR,
0000 0000 0000 0000 0000 0000
Value other RESETS
0000 0000 0000 0000 0000 0000 -000 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 1111 0000 0000 1111 1111
Timer2 Module Register TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
-000 0000 xxxx xxxx xxxx xxxx
Capture/Compare/PWM Register1 Byte Capture/Compare/PWM Register1 High Byte P1M1 PRSEN P1M0 PDC6 DC1B1 PDC5 DC1B0 PDC4 ECCPAS0 TRISC4 C2IE CCP1M3 PDC3 PSSAC1 TRISC3 C1IE CCP1M2 PDC2 PSSAC0 TRISC2 OSFIE CCP1M1 PDC1 PSSBD1 TRISC1 TMR2IE CCP1M0 PDC0 PSSBD0 TRISC0 TMR1IE
0000 0000 0000 0000 0000 0000 1111 0000 0000 1111 1111
ECCPASE ECCPAS2 ECCPAS1 EEIE ADIE TRISC5 CCP1IE
Timer2 Module Period Register
Legend:
Unimplemented locations, read `0', unchanged, unknown. Shaded cells used Timer2 module.
2003 Microchip Technology Inc.
DS41202A-page
PIC16F684
NOTES:
DS41202A-page
2003 Microchip Technology Inc.
PIC16F684
COMPARATOR MODULE
comparator module contains analog comparators. inputs comparators multiplexed with port p
Other recent searches
STP45NF06 - STP45NF06 STP45NF06 Datasheet
STB45NF06 - STB45NF06 STB45NF06 Datasheet
STM-4 - STM-4 STM-4 Datasheet
ID850NW - ID850NW ID850NW Datasheet
Integrated - Integrated Integrated Datasheet
Debugger - Debugger Debugger Datasheet
Operation - Operation Operation Datasheet
DFM300LXS18-A000 - DFM300LXS18-A000 DFM300LXS18-A000 Datasheet
AD1847 - AD1847 AD1847 Datasheet
2SK1983-01 - 2SK1983-01 2SK1983-01 Datasheet
2SC4562 - 2SC4562 2SC4562 Datasheet
2SA1748 - 2SA1748 2SA1748 Datasheet
2SA1971 - 2SA1971 2SA1971 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
