The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

6107 CY7C342B 128-Macrocell MAX® EPLDs Features ma


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



7C34
6107
CY7C342B
128-Macrocell MAX® EPLDs
Features
macrocells LABs dedicated inputs, bidirectional pins Programmable interconnect array Advanced 0.65-micron CMOS technology increase performance Available 68-pin HLCC, PLCC, macrocells CY7C342B divided into Logic Array Blocks (LABs), LAB. There expander product terms, LAB, used shared macrocells within each LAB. Each interconnected with programmable interconnect array, allowing signals routed throughout chip. speed density CY7C342B allows used wide range applications, from replacement large amounts 7400-series logic, complex controllers multifunction chips. With greater than times functionality 20-pin PLDs, CY7C342B allows replacement over devices. replacing large amounts logic, CY7C342B reduces board space, part count, increases system reliability.
Functional Description
CY7C342B Erasable Programmable Logic Device (EPLD) which CMOS EPROM cells used configure logic functions within device. architecture 100% user configurable, allowing devices accommodate variety independent logic functions.
Logic Block Diagram
(B6) (A6) (L4) (L5) INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT (A7) (A8) (L6) (K6)
SYSTEM CLOCK MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 9-16 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 22-32 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 121-128 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 102-112 (B8) (A9) (B9) (A10) (B10) (B11) (C11) (C10)
(A5) (B4) (A4) (B3) (A3) (A2) (B2) (B1)
(C2) (C1) (D2) (D1) (E1)
(D11) (D10) (E11) (F11) (F10)
(F2) (F1) (G1) (H2) (H1)
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 38-48
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 86-96
(G11) (H11) (H10) (J11) (J10)
(J2) (J1) (K1) (K2) (L2) (K3) (L3) (K4)
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL (B5, E10) (E2, G10,
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
(K11) (K10) (L10) (L9) (K9) (L8) (K8) (L7)
PERTAIN 68-PIN PACKAGE C342B-1
registered trademark Altera Corporation. Warp2 Warp3 registered trademarks Cypress Semiconductor.
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134 408-943-2600 October 1989 Revised October 1995
CY7C342B
Selection Guide
7C342B-12 7C342B-15 Maximum Access Time (ns) Maximum Operating Current (mA) Commercial Military Industrial Maximum Static Current (mA) Commercial Military Industrial 7C342B-20 7C342B-25 7C342B-30 7C342B-35
Configurations
PLCC View BottomView
INPUT INPUT INPUT
7C342B
INPUT
7C342B
4344
INPUT/
C342B-2
INPUT INPUT INPUT
C342B-3
CY7C342B
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature .-65°C to+150°C Ambient Temperature with Power Applied.0°C to+70°C Maximum Junction Temperature (under bias). 150°C Supply Voltage Ground Potential -3.0V to+7.0V Maximum Power Dissipation. 2500 Current Output Current Pin. to+25 Input Voltage[1] .-3.0V 7.0V Program Voltage 13.0V Static Discharge Voltage >1100V (per MIL-STD-883, Method 3015)
Operating Range
Range Commercial Industrial Military Ambient Temperature +70°C -40°C +85°C -55°C +125°C (Case)
Electrical Characteristics Over Operating Range[2]
Parameter ICC1 ICC2 Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Current Output Leakage Current Output Short Circuit Current Power Supply Current (Static) Power Supply Current[5] Recommended Input Rise Time Recommended Input Fall Time Max., VOUT 0.5V[3, Load) Load) MHz[4] Com'l Mil/Ind Com'l Mil/Ind Test Conditions Min., -4.0 Min., -0.3 Min. 0.45 +0.3 Max. Unit
Capacitance[6]
Parameter COUT Description Input Capacitance Output Capacitance Test Conditions VOUT Max. Unit
Notes: Minimum input -0.3V. During transitions, inputs undershoot -3.0V periods less than Typical values 25°C more than output should tested time. Duration short circuit should more than second. VOUT 0.5V been chosen avoid test problems caused tester ground degradation. Guaranteed 100% tested. This parameter measured with device programmed 16-bit counter each LAB. Part Test Load Waveforms used parameters except which used part Test Load Waveforms. external timing parameters measured referenced external pins device.
CY7C342B
Test Loads Waveforms[5]
OUTPUT INCLUDING SCOPE OUTPUT INCLUDING SCOPE 3.0V INPUT PULSES
C342B-5
C342B-4
Equivalent OUTPUT
EQUIVALENT (commercial/military) 1.75V
Logic Array Blocks
There logic array blocks CY7C342B. Each consists macrocell array containing macrocells, expander product term array containing expanders, block. programmable interconnect array dedicated input bus. macrocell feedbacks macrocell array, expander array, programmable interconnect array. Expanders feed themselves macrocell array. feedbacks programmable interconnect array that they accessed macrocells other LABs well macrocells which they situated. Externally, CY7C342B provides eight dedicated inputs, which used system clock. There pins that individually configured input, output, bidirectional data flow.
ment routing iterations required programmable gate array achieve design timing objectives.
Timing Delays
Timing delays within CY7C342B easily determined using Warp2® Warp3® software model shown Figure CY7C342B fixed internal delays, allowing user determine worst case timing delays design. complete timing information Warp3 software provides timing simulator.
Design Recommendations
Operation devices described herein with conditions above those listed under "Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this datasheet implied. Exposure absolute maximum ratings conditions extended periods time affect device reliability. CY7C342B contains circuitry protect device pins from high static voltages electric fields, normal precautions should taken avoid application voltage higher than maximum rated voltages. proper operation, input output pins must constrained range (VIN VOUT) VCC. Unused inputs must always tied appropriate logic level (either GND). Each pins must connected together directly device. Power supply decoupling capacitors least must connected between GND. most effective decoupling, each should separately decoupled directly device. Decoupling capacitors should have good frequency response, such monolithic ceramic types have.
Programmable Interconnect Array
Programmable Interconnect Array (PIA) solves interconnect limitations routing only signals needed each logic array block. inputs outputs every macrocell within device feedback every device. Unlike masked programmable gate arrays, which induce variable delay dependent routing, fixed delay. This eliminates undesired skews among logic signals that cause glitches internal external logic. fixed delay, regardless programmable interconnect array configuration, simplifies design assuring that internal signal skews races avoided. result ease design implementation, often signal pass, without multiple internal logic place-
CY7C342B
EXPANDER DELAY tEXP
REGISTER OUTPUT DELAY OUTPUT tCOMB tLATCH
INPUT INPUT DELAY
LOGIC ARRAY CONTROL DELAY tLAC LOGIC ARRAY DELAY tLAD
tCLR tPRE tRSU
SYSTEM CLOCK DELAY tICS CLOCK DELAY FEEDBACK DELAY
DELAY tPIA
DELAY
C342B-6
Figure CY7C342B Internal Timing Model
CY7C342B
Design Security
CY7C342B contains programmable design security feature that controls access data programmed into device. this programmable feature used, proprietary design implemented device cannot copied retrieved. This enables high level design control obtained since programmed data within EPROM cells invisible. that controls this function, along with other program data, reset simply erasing entire device. CY7C342B fully functionally tested guaranteed through complete testing each programmable EPROM internal logic elements thus ensuring 100% programming yield. erasable nature these devices allows test programs used erased during early stages production flow. devices also contain on-board logic test circuitry allow verification function specification once encapsulated non-windowed packages.
Timing Considerations
Unless otherwise stated, propagation delays include expanders. When using expanders, maximum expander delay tEXP overall delay. Similarly, there additional tPIA delay input from when compared signal from straight input pin. When calculating synchronous frequencies, inputs dedicated input pins. parameter should used data applied pin. greater than tCO1, 1/tS2 becomes limiting frequency data path mode unless 1/(tWH tWL) less than 1/tS2. When expander logic used data path, appropriate maximum expander delay, tEXP tS1. Determine which 1/(tWH tWL), 1/tCO1, 1/(tEXP tS1) lowest frequency. lowest these frequencies maximum data path frequency synchronous configuration. When calculating external asynchronous frequencies, tAS1 inputs dedicated input pins. data applied pin, tAS2 must used required set-up time. (tAS2 tAH) greater than tACO1, 1/(tAS2 tAH) becomes limiting frequency data path mode unless 1/(tAWH tAWL) less than 1/(tAS2 tAH). When expander logic used data path, appropriate maximum expander delay, tEXP tAS1. Determine which 1/(tAWH tAWL), 1/tACO1, 1/(tEXP tAS1) lowest frequency. lowest these frequencies maximum data path frequency asynchronous configuration. parameter indicates system compatibility this device when driving other synchronous logic with positive input hold times, which controlled same synchronous clock. greater than minimum required input hold time subsequent synchronous logic, then devices guaranteed function properly with common synchronous clock under worst-case environmental supply voltage conditions. parameter tAOH indicates system compatibility this device when driving subsequent registered logic with positive hold time using same asynchronous clock CY7C342B. general, tAOH greater than minimum required input hold time subsequent logic (synchronous asynchronous) then devices guaranteed function properly under worst-case environmental supply voltage conditions, provided clock signal source same. This also applies expander logic used clock signal path driving device, driven device. This expander logic second device's clock signal path adding additional delay (tEXP) causing output data from preceding device change prior arrival clock signal following device's register.
Typical fMAX
=5.0V RoomTemp.
MAXIMUM FREQUENCY
Output Drive Current
=5.0V RoomTemp.
0.45
OUTPUT VOLTAGE
CY7C342B
Commercial Industrial External Synchronous Switching Characteristics Over Operating Range
7C342B-12 Parameter tPD1 tPD2 tPD3 tPD4 tCO1 tCO2 fMAX1 fMAX2 Description Dedicated Input Combinatorial Output Delay Input Combinatorial Output Delay[8] Dedicated Input Combinatorial Output Delay with Expander Delay[9] Input Combinatorial Output Delay with Expander Delay[4,10] Input Output Enable Delay[4, Input Output Disable Delay[4, Synchronous Clock Input Output Delay Synchronous Clock Local Feedback Combinatorial Output[4, Dedicated Input Feedback Set-Up Time Synchronous Clock Input[4, Input Set-Up Time Synchronous Clock Input[7] Input Hold Time from Synchronous Clock Synchronous Clock Input HIGH Time Synchronous Clock Input Time Asynchronous Clear Width[4, Asynchronous Clear Recovery Asynchronous Preset Time[4, Asynchronous Clear Registered Output Delay[7] Width[4, Delay[7] 71.4 90.9 58.8 76.9 Asynchronous Preset Recovery Time[4,7] Asynchronous Preset Registered Output External Synchronous Clock Period Synchronous Clock Local Feedback Input[4, (1/(fMAX3))[4] External Feedback Maximum Frequency (1/(tCO1 tS1))[4, Internal Local Feedback Maximum Frequency, lesser (1/(tS1 tCF)) (1/tCO1)[4, Input[7] 47.6 62.5
7C342B-15 Min. Max.
7C342B-20 Min. Max. Unit
Min.
Max.
Notes: This specification measure delay from input signal applied dedicated input (68-pin PLCC input combinatorial output output pin. This delay assumes expander terms used form logic function. When this note applied parameter specification indicates that signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) applied dedicated input only signal path (either clock data) employs expander logic. input signal applied additional delay equal tPIA should added comparable delay dedicated input. expanders used, maximum expander delay overall delay comparable delay without expanders. This specification measure delay from input signal applied macrocell output. This delay assumes expander terms used form logic function. This specification measure delay from input signal applied dedicated input (68-pin PLCC input combinatorial output output pin. This delay assumes expander terms used form logic function includes worst-case expander logic delay pass through expander logic. This specification measure delay from input signal applied macrocell output. This delay assumes expander terms used form logic function includes worst-case expander logic delay pass through expander logic. This parameter tested periodically sampling production material. This specification measure delay from synchronous register clock internal feedback register output signal input logic array then combinatorial output. This delay assumes expanders used, register synchronously clocked feedback within same LAB. This parameter tested periodically sampling production material. data applied input capture macrocell register, input set-up time minimums should observed. These parameters synchronous operation tAS2 asynchronous operation. This specification measure delay associated with internal register feedback path. This delay from synchronous clock logic array input. This delay plus register set-up time, tS1, minimum internal period internal synchronous state machine configuration. This delay feedback within same LAB. This parameter tested periodically sampling production material. This specification indicates guaranteed maximum frequency, synchronous mode, which state machine configuration with external feedback operate. assumed that data inputs feedback signals applied dedicated inputs. feedback assumed local originating within same LAB. This specification indicates guaranteed maximum frequency which state machine with internal-only feedback operate. register output states must also control external points, this frequency still observed long this frequency less than 1/tCO1.
CY7C342B
Commercial Industrial External Synchronous Switching Characteristics Over Operating Range
7C342B-12 Parameter fMAX3 fMAX4 Description Data Path Maximum Frequency, lesser (1/(tWL tWH)), (1/(tS1 (1/tCO1)[4, Maximum Register Toggle Frequency (1/(t WL+tWH))[4,17] Output Data Stable Time from Synchronous Clock Input
7C342B-15 Min. 7C342B-30 Min. Max. Max.
7C342B-20 Min. 71.4 71.4 7C342B-35 Min. Max. 12.5 12.5 Unit 22.2 32.2 Max. Unit
Min. 111.1 111.1
Max.
7C342B-25 Parameter tPD1 tPD2 tPD3 tPD4 tCO1 tCO2 fMAX1 fMAX2 fMAX3 fMAX4 Description Dedicated Input Combinatorial Output Delay[7] Input Combinatorial Output Delay[8] Dedicated Input Combinatorial Output Delay with Expander Delay[9] Input Combinatorial Output Delay with Expander Delay[4,8] Input Output Enable Delay[4, Input Output Disable Delay[4, Synchronous Clock Input Output Delay Synchronous Clock Local Feedback Combinatorial Output[4, Dedicated Input Feedback Set-Up Time Synchronous Clock Input[7, Input Set-Up Time Synchronous Clock Input[7] Input Hold Time from Synchronous Clock Synchronous Clock Input HIGH Time Synchronous Clock Input Time Asynchronous Clear Width[4, Asynchronous Clear Recovery Asynchronous Preset Time[4, Asynchronous Clear Registered Output Delay[7] Width[4, Delay[7] 34.5 55.5 62.5 62.5 Asynchronous Preset Recovery Time[4,7] Asynchronous Preset Registered Output External Synchronous Clock Period Synchronous Clock Local Feedback Input[4, (1/(fMAX3))[4] External Feedback Maximum Frequency (1/(tCO1 tS1))[4, Internal Local Feedback Maximum Frequency, lesser (1/(tS1 tCF)) (1/tCO1)[4, Data Path Maximum Frequency, lesser (1/(tWL tWH)), (1/(tS1 (1/tCO1)[4, Maximum Register Toggle Frequency (1/(t WL+tWH))[4,15] Output Data Stable Time from Synchronous Clock Input[4, Input[7] Min. Max.
27.7 43.4
Notes: This frequency indicates maximum frequency which device operate data path mode (dedicated input output pin). This assumes data input signals applied dedicated input pins expander logic used. data inputs pins, appropriate calculation. This specification indicates guaranteed maximum frequency, synchronous mode, which individual output buried register cycled clock signal applied dedicated clock input pin. This parameter indicates minimum time after synchronous register clock input that previous register output data maintained output pin.
CY7C342B
Commercial Industrial External Asynchronous Switching Characteristics[6] Over Operating Range
7C342B-12 Parameter tACO1 tACO2 tAS1 tAS2 tAWH tAWL tACF fMAXA1 fMAXA2 fMAXA3 fMAXA4 tAOH Description Asynchronous Clock Input Output Delay
7C342B-15 Min. Max. 14.5
7C342B-20 Min. Max. Unit 55.5 55.5
Min.
Max.
Asynchronous Clock Input Local Feedback Combinatorial Output[19] Dedicated Input Feedback Set-Up Time Asynchronous Clock Input[7] Input Set-Up Time Asynchronous Clock Input[7] Input Hold Time from Asynchronous Clock Input Asynchronous Clock Input HIGH Time[7] Asynchronous Clock Input Time[7, (1/(fMAXA4))[4] Asynchronous Clock Local Feedback Input[4,21] External Asynchronous Clock Period 62.5 71.4 Mode[4,24] 83.3 71.4 External Feedback Maximum Frequency Asynchronous Mode (1/(tACO1 tAS1))[4,22] Maximum Internal Asynchronous Frequency[4,23] Data Path Maximum Frequency Asynchronous Maximum Asynchronous Register Toggle Frequency 1/(tAWH tAWL)[4,25] Output Data Stable Time from Asynchronous Clock Input[4,26]
62.5 66.6 62.5
Notes: This specification measure delay from asynchronous register clock input internal feedback register output signal input logic array then combinatorial output. This delay assumes expanders used logic combinatorial output asynchronous clock input. clock signal applied dedicated clock input feedback within single LAB. This parameter tested periodically sampling production material. This parameter measured with positive-edge triggered clock register. negative edge triggering, tAWH tAWL parameters must swapped. given input used clock multiple registers with both positive negative polarity, tAWH should used both tAWH tAWL. This specification measure delay associated with internal register feedback path asynchronous clock logic array input. This delay plus asynchronous register set-up time, tAS1, minimum internal period internal asynchronously clocked state machine configuration. This delay feedback within same LAB, assumes expander logic clock path, assumes that clock input signal applied dedicated input pin. This parameter tested periodically sampling production material. This specification indicates guaranteed maximum frequency which asynchronously clocked state machine configuration with external feedback operate. assumed that data inputs, clock inputs, feedback signals applied dedicated inputs that expander logic employed clock signal path data path. This specification indicates guaranteed maximum frequency which asynchronously clocked state machine with internal-only feedback operate. This parameter determined lesser (1/(tACF tAS1)) (1/(tAWH tAWL)). register output states must also control external points, this frequency still observed long this frequency less than 1/tACO1. This specification assumes expander logic utilized, data inputs clock inputs applied dedicated inputs, state feedback within single LAB. This parameter tested periodically sampling production material. This frequency maximum frequency which device operate asynchronously clocked data path mode. This specification determined lesser 1/(tAWH tAWL), 1/(tAS1 tAH) 1/tACO1. assumes data clock input signals applied dedicated input pins expander logic used. This specification indicates guaranteed maximum frequency which individual output buried register cycled asynchronously clocked mode clock signal applied external dedicated input pin. This parameter indicates minimum time that previous register output data maintained output after asynchronous register clock input applied external dedicated input pin.
CY7C342B
Commercial Industrial External Asynchronous Switching Characteristics[6] Over Operating Range
(continued) 7C342B-25 Parameter tACO1 tACO2 tAS1 tAS2 tAWH tAWL tACF fMAXA1 fMAXA2 fMAXA3 fMAXA4 tAOH Description Asynchronous Clock Input Output Delay
7C342B-30 Min. Max.
7C342B-35 Min. Max. Unit 23.2 33.3 28.5 33.3
Min.
Max.
Asynchronous Clock Input Local Feedback Combinatorial Output[19] Dedicated Input Feedback Set-Up Time Asynchronous Clock Input[7] Input Set-Up Time Asynchronous Clock Input[7] Input Hold Time from Asynchronous Clock Asynchronous Clock Input HIGH Time[7] Asynchronous Clock Input Time[7, (1/(fMAXA4))[4] Asynchronous Clock Local Feedback Input[4,21] External Asynchronous Clock Period 33.3 Mode[4,24] External Feedback Maximum Frequency Asynchronous Mode (1/(tACO1 tAS1))[4,22] Maximum Internal Asynchronous Frequency[4,23] Data Path Maximum Frequency Asynchronous Maximum Asynchronous Register Toggle Frequency 1/(tAWH tAWL)[4,25] Output Data Stable Time from Asynchronous Clock Input[4,26] Input[7]
27.7 33.3
Commercial Industrial Typical Internal Switching Characteristics Over Operating Range
7C342B-12 Parameter tEXP tLAD tLAC tRSU tLATCH tCOMB tICS tPRE Description Dedicated Input Buffer Delay Input Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer Delay Output Buffer Enable Delay[27] Delay[28] Output Buffer Disable Delay Register Set-Up Time Relative Clock Signal Register Register Hold Time Relative Clock Signal Register Flow Through Latch Delay Register Delay Transparent Mode Clock HIGH Time Clock Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Min. Max. 7C342B-15 Min. Max. 7C342B-20 Min. Max. Unit
Notes: Sample tested only output change This specification guarantees maximum combinatorial delay associated with macrocell register bypass when macrocell configured combinatorial operation.
CY7C342B
Commercial Industrial Typical Internal Switching Characteristics Over Operating Range (continued)
7C342B-12 Parameter tCLR tPCW tPCR tPIA Description Asynchronous Register Clear Time Asynchronous Preset Clear Pulse Width Asynchronous Preset Clear Recovery Time Programmable Interconnect Array Delay Time Min. Max. 7C342B-15 Min. Max. 7C342B-20 Min. Max. Unit
Commercial Industrial Typical Internal Switching Characteristics Over Operating Range (continued)
7C342B-25 Parameter tEXP tLAD tLAC tRSU tLATCH tCOMB tICS tPRE tCLR tPCW tPCR tPIA Description Dedicated Input Buffer Delay Input Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer Delay Output Buffer Enable Delay[27] Output Buffer Disable Delay Register Set-Up Time Relative Clock Signal Register Register Hold Time Relative Clock Signal Register Flow Through Latch Delay Register Delay Transparent Mode Delay[28] Clock HIGH Time Clock Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Asynchronous Preset Clear Pulse Width Asynchronous Preset Clear Recovery Time Programmable Interconnect Array Delay Time Min. Max. 12.5 12.5 7C342B-30 Min. Max. 7C342B-35 Min. Max. Unit
CY7C342B
Military External Synchronous Switching Characteristics[6] Over Operating Range
7C342B-15 Parameter tPD1 tPD2 tPD3 Description Dedicated Input Combinatorial Output Delay[7] Input Combinatorial Output Delay[8] Dedicated Input Combinatorial Output Delay with Expander Delay[9] Input Combinatorial Output Delay with Expander Delay[4,10] Input Output Enable Delay[4,7] Input Output Disable Delay[4,7] Synchronous Clock Input Output Delay Synchronous Clock Local Feedback Combinatorial Output[4, Dedicated Input Feedback Set-Up Time Synchronous Clock Input[7,12] Input Set-Up Time Synchronous Clock Input Input Hold Time from Synchronous Clock Input Synchronous Clock Input HIGH Time Synchronous Clock Input Time Asynchronous Clear Width[4, Asynchronous Clear Recovery Time[4, Asynchronous Clear Registered Output Delay[7] Asynchronous Preset Width[4,7] Asynchronous Preset Recovery Time[4,7] Asynchronous Preset Registered Output Delay[7] Synchronous Clock Local Feedback Input[4,13] External Synchronous Clock Period (1/(fMAX3))[4] External Feedback Maximum Frequency (1/(tCO1 tS1))[4,14] Internal Local Feedback Maximum Frequency, lesser (1/(tS1 tCF)) (1/tCO1)[4, 58.8 76.9 47.6 62.5 Min. Max. 7C342B-20 Min. Max. 7C342B-25 Min. Max. 7C342B-30 Min. Max. 7C342B-35 Min. Max. Unit
tPD4
tCO1 tCO2
fMAX1 fMAX2
34.5 55.5
27.7 43.4
12.5 12.5 22.2 32.2
CY7C342B
Military External Synchronous Switching Characteristics[6] Over Operating Range (continued)
7C342B-15 Parameter fMAX3 Description Data Path Maximum Frequency, lesser (1/(tWL tWH)), (1/(tS1 tH)) (1/tCO1)[4,16] Maximum Register Toggle Frequency (1/(tWL tWH))[4,17] Output Data Stable Time from Synchronous Clock Input [4,18] Min. Max. 7C342B-20 Min. 71.4 Max. 7C342B-25 Min. 62.5 Max. 7C342B-30 Min. Max. 7C342B-35 Min. Max. Unit
fMAX4
71.4
62.5
Military External Asynchronous Switching Characteristics[6] Over Operating Range
7C342B-15 Parameter tACO1 tACO2 Description Asynchronous Clock Input Output Delay[7] Asynchronous Clock Input Local Feedback Combinatorial Output[19] Dedicated Input Feedback Set-Up Time Asynchronous Clock Input[7] Input Set-Up Time Asynchronous Clock Input[7] Input Hold Time from Asynchronous Clock Input[7] Asynchronous Clock Input HIGH Time[7] Asynchronous Clock Input Time[7, Asynchronous Clock Local Feedback Input[4,21] External Asynchronous Clock Period (1/(fMAXA4))[4] External Feedback Maximum Frequency Asynchronous Mode (1/(tACO1 tAS1))[4,22] Maximum Internal Asynchronous Frequency[4,23] Data Path Maximum Frequency Asynchronous Mode[4,24] Maximum Asynchronous Register Toggle Frequency 1/(tAWH tAWL)[4,25] Output Data Stable Time from Asynchronous Clock Input[4,26] 50.0 Min. Max. 7C342B-20 Min. Max. 7C342B-25 Min. Max. 7C342B-30 Min. Max. 7C342B-35 Min. Max. Unit
tAS1
tAS2 tAWH tAWL tACF fMAXA1
14.5
33.3
27.7
23.2
fMAXA2 fMAXA3 fMAXA4
62.5 66.6 62.5
55.5 55.5
33.3
33.3 28.5 33.3
tAOH
CY7C342B
Military Typical Internal Switching Characteristics Over Operating Range
7C342B-15 Parameter tEXP tLAD tLAC tRSU tLATCH tCOMB tICS tPRE tCLR tPCW tPCR tPIA Description Dedicated Input Buffer Delay Input Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer Delay Output Buffer Enable Delay[27] Output Buffer Disable Delay Register Set-Up Time Relative Clock Signal Register Register Hold Time Relative Clock Signal Register Flow Through Latch Delay Register Delay Transparent Mode Delay[28] Clock HIGH Time Clock Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Asynchronous Preset Clear Pulse Width Asynchronous Preset Clear Recovery Time Programmable Interconnect Array Delay Time Min. Max. 7C342B-20 Min. Max. 7C342B-25 Min. Max. 12.5 12.5 7C342B-30 Min. Max. 7C342B-35 Min. Max. Unit
CY7C342B
Switching Waveforms
External Combinatorial
DEDICATED INPUT/ INPUT tPD1[7] COMBINATORIAL OUTPUT tER[7] COMBINATORIAL REGISTERED OUTPUT HIGH-IMPEDANCE THREE-STATE VALID OUTPUT
C342B-7
HIGH-IMPEDANCE THREE-STATE
External Synchronous
DEDICATED INPUTS REGISTERED FEEDBACK SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET tRO/t REGISTERED OUTPUTS COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK [11]
C342B-8
tRW/t
tRR/t
tCO2
External Asynchronous
DEDICATED INPUTS REGISTERED FEEDBACK tAS1 ASYNCHRONOUS CLOCK INPUT tAWH tAWL
tACO1 tAOH
tRW/t
tRR/t
ASYNCHRONOUS CLEAR/PRESET ASYNCHRONOUS REGISTERED OUTPUTS COMBINATORIAL OUTPUT FROM ASYNCHRONOUS REGISTERED FEEDBACK
tRO/t
tACO2
C342B-9
CY7C342B
Switching Waveforms (continued)
Internal Combinatorial
INPUT tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT tPIA
LOGIC ARRAY OUTPUT
C342B-10
Internal Asynchronous
tIOR CLOCK CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY tRSU DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT LOCAL LOGIC ARRAY tPIA REGISTER OUTPUT ANOTHER
C342B-11
tAWH
tAWL
tCLR,tPRE
Internal Synchronous
SYSTEM CLOCK SYSTEM CLOCK REGISTER tRSU DATA FROM LOGIC ARRAY
C342B-12
tICS
CY7C342B
Switching Waveforms (continued)
Internal Synchronous
CLOCK FROM LOGIC ARRAY
DATA FROM LOGIC ARRAY OUTPUT HIGH IMPEDANCE STATE
C342B-13
Ordering Information
Speed (ns) Ordering Code CY7C342B-12HC CY7C342B-12JC CY7C342B-12RC CY7C342B-15HC/HI CY7C342B-15JC/JI CY7C342B-15RC/RI CY7C342B-15HMB CY7C342B-15RMB CY7C342B-20HC/HI CY7C342B-20JC/JI CY7C342B-20RC/RI CY7C342B-20HMB CY7C342B-20RMB CY7C342B-25HC/HI CY7C342B-25JC/JI CY7C342B-25RC CY7C342B-25HMB CY7C342B-25RMB CY7C342B-30HC/HI CY7C342B-30JC/JI CY7C342B-30RC/RI CY7C342B-30HMB CY7C342B-30RMB CY7C342B-35HC/HI CY7C342B-35JC/JI CY7C342B-35RC/RI CY7C342B-35HMB CY7C342B-35RMB Package Name Package Type 68-Pin Windowed Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Pin Windowed Ceramic Grid Array 68-Pin Windowed Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Pin Windowed Ceramic Grid Array 68-Pin Windowed Leaded Chip Carrier 68-Pin Windowed Ceramic Grid Array 68-Pin Windowed Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Pin Windowed Ceramic Grid Array 68-Pin Windowed Leaded Chip Carrier 68-Pin Windowed Ceramic Grid Array 68-Pin Windowed Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Pin Windowed Ceramic Grid Array 68-Pin Windowed Leaded Chip Carrier 68-Pin Windowed Ceramic Grid Array 68-Pin Windowed Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Pin Windowed Ceramic Grid Array 68-Pin Windowed Leaded Chip Carrier 68-Pin Windowed Ceramic Grid Array 68-Pin Windowed Leaded Chip Carrier 68-Lead Plastic Leaded Chip Carrier 68-Pin Windowed Ceramic Grid Array 68-Pin Windowed Leaded Chip Carrier 68-Pin Windowed Ceramic Grid Array Military Commercial/ Industrial Military Commercial/ Industrial Military Commercial/ Industrial Military Commercial/ Industrial Military Commercial/ Industrial Operating Range Commercial
CY7C342B
MILITARY SPECIFICATIONS Group Subgroup Testing Characteristics
Parameter ICC1 Subgroups
Switching Characteristics
Parameter tPD1 tPD2 tPD3 tCO1 tACO1 tAS1 tAWH tAWL Subgroups
Document 38-00119-G
CY7C342B
Package Diagrams
68-Pin Windowed Leaded Chip Carrier
CY7C342B
Package Diagrams (continued)
68-Lead Plastic Leaded Chip Carrier
68-Pin Windowed Ceramic
Cypress Semiconductor Corporation, 1995. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

Other recent searches


SD4324-002 - SD4324-002   SD4324-002 Datasheet
RKS150KK - RKS150KK   RKS150KK Datasheet
MQFL-28-15D - MQFL-28-15D   MQFL-28-15D Datasheet
D62ZOV271HC - D62ZOV271HC   D62ZOV271HC Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive