CY7C1031 CY7C1032 Synchronous Cache Features Supports 6
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7C10
CY7C1031 CY7C1032
Synchronous Cache
Features
Supports 66-MHz Pentiummicroprocessor cache systems with zero wait states common Fast clock-to-output times Two-bit wraparound counter supporting Pentium microprocessor burst sequence (7C1031) Two-bit wraparound counter supporting linear burst sequence (7C1032) Separate processor controller address strobes Synchronous self-timed write Direct interface with processor external cache controller Asynchronous output enable I/Os capable 3.3V operation JEDEC-standard pinout 52-pin PLCC PQFP packaging
Functional Description
CY7C1031 CY7C1032 synchronous cache RAMs designed interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise 2-bit on-chip counter captures first address burst increments address automatically rest burst access. CY7C1031 designed Intel Pentium i486 CPU-based systems; counter follows burst sequence Pentium i486 processors. CY7C1032 architected processors with linear burst sequences. Burst accesses initiated with processor address strobe (ADSP) cache controller address strobe (ADSC) inputs. Address advancement controlled address advancement (ADV) input. synchronous self-timed write mechanism provided simplify write interface. synchronous chip select input asynchronous output enable input provide easy control bank selection output three-state control.
Logic Block Diagram
DATA REGISTER ADDR LOGIC ARRAY ARRAY VCCQ VSSQ DQ10 DQ11 DQ12 DQ13 VSSQ VCCQ DQ14 DQ15 DP1[1]
Configuration
PLCC View
ADSP ADSC TIMING CONTROL
7C1031 7C1032 2122
VCCQ VSSQ VSSQ VCCQ
DQ15 1031-2 1031-1
Selection Guide
Maximum Access Time (ns) Maximum Operating Current (mA) 7C1031-7 7C1032-7 7C1031-8 7C1032-8 7C1031-10 7C1032-10 7C1031-12 7C1032-12
Commercial Military
Shaded area contains advanced information. Pentium trademark Intel Corporation. Note: functionally equivalent DQx.
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134 408-943-2600 January 1993 Revised March 1995
Functional Description (continued)
Single Write Accesses Initiated ADSP This access initiated when following conditions satisfied clock rise: ADSP LOW. ADSP-triggered write cycles completed clock periods. address through loaded into address register address advancement logic delivered core. write signal ignored this cycle because cache other external logic uses this clock period perform address comparisons protection checks. write allowed proceed, write input CY7C1031 CY7C1032 will pulled before next clock rise. ADSP ignored HIGH. both next clock rise, information presented DQ15 will written into location specified address advancement logic. controls writing while controls writing DQ15 DP1. Because CY7C1031 CY7C1032 common-I/O devices, output enable signal (OE) must deasserted before data from delivered DQ15 DP1. safety precaution, appropriate data lines three-stated cycle where both sampled LOW, regardless state input. Single Write Accesses Initiated ADSC This write access initiated when following conditions satisfied rising edge clock: LOW, ADSC LOW, LOW. ADSC triggered accesses completed single clock cycle. address through loaded into address register address advancement logic delivered core. Information presented DQ15 will written into location specified address advancement logic. Since CY7C1031 CY7C1032 common-I/O devices, output enable signal (OE) must deasserted before data from cache controller delivered data parity lines. safety precaution, appropriate data parity lines three-stated cycle where sampled regardless state input. Single Read Accesses single read access initiated when following conditions satisfied clock rise: LOW, ADSP ADSC
CY7C1031 CY7C1032
LOW, HIGH. address through stored into address advancement logic delivered core. output enable (OE) signal asserted (LOW), data will available data outputs maximum after clock rise. ADSP ignored HIGH.
Burst Sequences
CY7C1031 provides 2-bit wraparound counter, pins that implements Intel 80486 Pentium processor's address burst sequence (see Table Note that burst sequence depends first burst address. Table Counter Implementation Intel Pentium/80486 Processor's Sequence First Address Second Address Third Address Fourth Address
CY7C1032 provides two-bit wraparound counter, pins that implements linear address burst sequence (see Table Table Counter Implementation Linear Sequence First Address Second Address Third Address Fourth Address
Application Example
Figure shows 512-Kbyte secondary cache Pentium microprocessor using four CY7C1031 cache RAMs.
66-MHz
CY7C1031 CY7C1032
DATA PENTIUM PROCESSOR
DATA ADSP ADSC INTERFACE MAIN MEMORY 7C1031
CACHE DATA MATCH DIRTY VALID
ADSC DATA ADSP CACHE CONTROLLER MATCH DIRTY VALID
Figure Cache Using Four CY7C1031s
Definitions
Signal Name VCCQ VSSQ ADSP ADSC DQ15-DQ0 DP1-DP0 Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input/Output Input/Output Pins Description Power 3.3V (Outputs) Ground Ground (Outputs) Clock Address Address Strobe from Processor Address Strobe from Cache Controller Write Enable High Byte Write Enable Byte Advance Output Enable Chip Select Regular Data Parity Data
Descriptions
Signal Name Description
CY7C1031 CY7C1032
Descriptions (continued)
Signal Name Description Advance. This signal sampled rising edge CLK. When asserted, automatically increments 2-bit on-chip auto-address-increment counter. CY7C1032, address will incremented linearly. CY7C1031, address will incremented according Pentium/486 burst sequence. This signal ignored ADSP ADSC asserted concurrently with Note that ADSP effect HIGH. Chip select. This signal sampled rising edge CLK. HIGH ADSC LOW, SRAM deselected. ADSC ADSP LOW, address captured address register. HIGH, ADSP ignored. Output enable. This signal asynchronous input that controls direction data pins. asserted (LOW), data pins outputs, SRAM read long asserted when sampled beginning cycle). deasserted (HIGH), data pins will three-stated, functioning inputs, SRAM written.
Input Signals Clock signal. used capture address, data written, following control signals: ADSP, ADSC, ADV. also used advance on-chip auto-address-increment logic (when appropriate control signals have been set). Sixteen address lines used select locations. They captured on-chip register rising edge ADSP ADSC LOW. rising edge clock also loads lower address lines, into on-chip auto-address-increment logic ADSP ADSC LOW. Address strobe from processor. This signal sampled rising edge CLK. When this input and/or ADSC asserted, A0-A15 will captured on-chip address register. also allows lower address bits loaded into on-chip auto-address-increment logic. both ADSP ADSC asserted rising edge CLK, only ADSP will recognized. ADSP input should connected output processor. ADSP ignored when HIGH. Address strobe from cache controller. This signal sampled rising edge CLK. When this input and/or ADSP asserted, A0-A will captured on-chip address register. also allows lower address bits loaded into on-chip auto-address-increment logic. ADSC input should connected output processor. Write signal high-order half array. This signal sampled rising edge CLK. sampled LOW, i.e., asserted, control logic will perform self-timed write DQ15 from on-chip data register into selected location. There exception this. ADSP, asserted (LOW) rising edge CLK, write signal, ignored. Note that ADSP effect HIGH. Write signal low-order half array. This signal sampled rising edge CLK. sampled LOW, i.e., asserted, control logic will perform self-timed write from on-chip data register into selected location. There exception this. ADSP, asserted (LOW) rising edge CLK, write signal, ignored. Note that ADSP effect HIGH.
A15-A
ADSP
ADSC
Bidirectional Signals DQ15 -DQ0 Sixteen bidirectional data lines. DQ15 inputs outputs from high-order half array, while inputs outputs from low-order half array. inputs, they feed into on-chip data register that triggered rising edge CLK. outputs, they carry data read from selected location array. direction data pins controlled when high, data pins three-stated used inputs; when low, data pins driven output buffers outputs. DQ15 also three-stated when respectively, sampled clock rise. bidirectional data lines. These operate exactly same manner DQ15 DQ0, named differently because their primary purpose store parity bits, while DQs' primary purpose store ordinary data bits. input output from high-order half array, while input output from lower-order half array.
DP1-DP0
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature .-65°C +150°C Ambient Temperature with Power Applied.-55°C +125°C Supply Voltage Relative GND. -0.5V +7.0V Voltage Applied Outputs High State[2] .-0.5V 0.5V Input Voltage[2] .-0.5V 0.5V Current into Outputs (LOW)
CY7C1031 CY7C1032
Static Discharge Voltage >2001V (per MIL-STD-883, Method 3015) Latch-Up Current >200
Operating Range
Range Com'l Ambient Temperature[3] +70°C -55°C +125°C VCCQ 3.0V
Electrical Characteristics Over Operating Range[4]
7C1031-7 7C1032-7 Parameter Description Test Conditions Min. Max. VCCQ -0.3 VCC, Output Disabled VCC=Max., VOUT=GND VCC=Max., Com'l Iout=0mA, f=fMAX =1/tCYC Max. VCC, Com'l VIH, VIL, f=fMAX 0.3V -300 -0.3 Output HIGH Voltage Min., IOH=-4.0 Output Voltage Input HIGH Voltage Input Voltage[2] Input Load Current Output Leakage Current Output Short Circuit Current[5] Operating Supply Current Automatic Power-Down Current-TTL Inputs Min, IOL=8.0 7C1031-8 7C1032-8 Min. Max. VCCQ 0.3V -300 -0.3 7C1031-10 7C1032-10 Min. Max. VCCQ 0.3V -300 -0.3 7C1031-12 7C1032-12 Min. Max. VCCQ 0.3V -300 Unit
ISB1
ISB2
Automatic Max. VCC, Com'l Power-Down Current 0.3V, CMOS Inputs -0.3V 0.3V, f=0[6]
Shaded area contains advanced information. Notes: Minimum voltage equals -2.0V pulse durations less than "instant case temperature. last page Group subgroup testing information. more than output should shorted time. Duration short circuit should exceed seconds. Inputs disabled, clock allowed speed.
Capacitance[7]
Parameter CIN: Addresses CIN: Other Inputs COUT Output Capacitance Description Input Capacitance Test Conditions 25°C, MHz, Com'l 5.0V Com'l Com'l Max.
CY7C1031 CY7C1032
Unit
Shaded areas contain advanced information
Test Loads Waveforms
OUTPUT =1.5V INCLUDING JIGAND SCOPE VCCQ OUTPUT INPUT PULSES 3.0V
1031-3 1031-4
Notes: Tested initially after design process changes that affect these parameters. Resistor values VCCQ=5V are: R1=1179 R2=868. Resistor values VCCQ=3.3V R1=317 R2=348.
Switching Characteristics Over Operating Range[9]
7C1031-7 7C1032-7 Parameter tCYC tCDV tDOH tADS tADSH tWES tWEH tADVS tADVH tCSS tCSH tCSOZ tEOZ tEOV tWEOZ tWEOV Clock Cycle Time Clock HIGH Clock Address Set-Up Before Rise Address Hold After Rise Data Output Valid After Rise Data Output Hold After Rise ADSP, ADSC Set-Up Before Rise ADSP, ADSC Hold After Rise Set-Up Before Rise Hold After Rise Set-Up Before Rise Hold After Rise Data Input Set-Up Before Rise Data Input Hold After Rise Chip Select Set-Up Chip Select Hold After Rise Chip Select Sampled Output High HIGH Output High Output Valid Sampled Output High Sampled HIGH Output Z[10, Valid[11] Z[10] Z[10] Description Min. 13.3 Max. 7C1031-8 7C1032-8 Min. Max. 7C1031-10 7C1032-10 Min. Max.
CY7C1031 CY7C1032
7C1031-12 7C1032-12 Min. Max. Unit
Shaded areas contain advanced information Notes: Unless otherwise noted, test conditions assume signal transition time less, timing reference levels 1.5V, input pulse levels 3.0V, output loading specified IOL/IOH load capacitance. Shown test loads. tCSOZ, tEOZ, tWEOZ specified with load capacitance part Test Loads. Transition measured from steady-state voltage. given voltage temperature, tWEOZ min. less than tWEOV min.
Switching Waveforms
Single Read[12]
tCSS ADDRESS
[13]
CY7C1031 CY7C1032
tCYC
tCSH
tADS
tADSH
ADSP ADSC tWES
[14]
tWEH
tCDV DATA
tDOH
1031-6
Single Write Timing: Write Initiated ADSP
tCSS ADDRESS tADS ADSP tWES
[14]
tCSH
tADSH
tWEH
DATA
DATA tEOZ
1031-5
Notes: throughout this operation. ADSP asserted while HIGH, ADSP will ignored. ADSP effect ADV, HIGH.
Switching Waveforms (continued)
Single Write Timing: Write Initiated ADSC
tCSS ADDRESS tADS ADSC tWES DATA tWEH tADSH tCSH
CY7C1031 CY7C1032
DATA tEOZ
1031-7
Burst Read Sequence with Four Accesses
tCSS ADDRESS tADS tADSH tCSH
ADSP
[13]
ADSC tADVS tADVH
[14] [14]
WH,WL
tWES
tWEH
tCDV DATA DATA0 tDOH DATA1 DATA2 DATA3
1031-8
Switching Waveforms (continued)
Output (Controlled
CY7C1031 CY7C1032
DATA tEOZ
1031-9
tEOV
Write Burst Timing: Write Initiated ADSC
tCSS tWES tWEH tCSH
tADS ADSP
[13]
tADSH
tADS ADSC ADDR
tADSH
tADVS DATA DATA0
tADVH
DATA1
DATA2
DATA3
1031-10
Switching Waveforms (continued)
Write Burst Timing: Write Initiated ADSP
CY7C1031 CY7C1032
tCSS tCSH
[14]
ADSC tADS ADSP
[13]
tADSH
ADDR
tADVS tADVH
[14]
DATA
DATA1 DATA2 DATA3
DATA0
1031-11
Switching Waveforms (continued)
Output Timing (Controlled
CY7C1031 CY7C1032
tADS ADSC tADS tADSH tCSS tCSS tCDV DATA
1031-12
tADSH
tCSH
tCSH
tCSOZ
Output Timing (Controlled
tADS ADSC ADSP tWES tWEOZ DATA
1031-13
tADSH
tADS
tADSH
tWEH
tWEOV
Truth Table
ADSP Input ADSC Address Same address previous cycle Incremented burst address Same address previous cycle Incremented burst address External External External Incremented burst address Incremented burst address Same address previous cycle Same address previous cycle Operation Chip deselected Read cycle (ADSP ignored) Read cycle, burst sequence (ADSP ignored) Write cycle (ADSP ignored) Write cycle, burst sequence (ADSP ignored) Read cycle, begin burst Read cycle, begin burst Write cycle, begin burst Write cycle, burst sequence Read cycle, burst sequence Write cycle Read cycle
Ordering Information
Speed (ns) Ordering Code CY7C1031-7JC CY7C1031-7NC CY7C1031-8JC CY7C1031-8NC CY7C1031-10JC CY7C1031-10NC CY7C1031-12JC CY7C1031-12NC CY7C1031-12YMB Speed (ns) Package Name Package Name Package Type 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack 52-Pin Ceramic Leaded Chip Carrier Military Operating Range Commercial Commercial Commercial Commercial Military Commercial Commercial Commercial Operating Range Commercial
CY7C1031 CY7C1032
Ordering Code CY7C1032-7JC CY7C1032-7NC CY7C1032-8JC CY7C1032-8NC CY7C1032-10JC CY7C1032-10NC CY7C1032-12JC CY7C1032-12NC CY7C1032-12YMB
Package Type 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Quad Flatpack 52-Pin Ceramic Leaded Chip Carrier
Shaded areas contain advanced information.
Document 38-00219-B
Package Diagrams
52-Lead Plastic Leaded Chip Carrier
CY7C1031 CY7C1032
52-P Ceramic Leaded Chip Carrier
Cypress Semiconductor Corporation, 1995. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
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