RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS GENERAL DES

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS GENERAL DES

Datasheet Thumbnail

Top Searches for this datasheet

SPACE PRODUCTS
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS GENERAL DESCRIPTION
Actel builds most reliable field programmable gate arrays (FPGAs) industry, with overall antifuse reliability ratings less than failures-in-time (FITs), corresponding useful life more than years. Actel FPGAs production-proven, with more than five million devices shipped more than trillion antifuses manufactured. Actel devices fully tested prior shipment, with out-going defect level only ppm. (Further reliability data available "Actel Device Reliability Report" http://www.actel.com/hirel). Additionally, programmable architecture both 1280ARP 14100ARP offers high performance, design flexibility, fast inexpensive prototyping-all without expense test vectors, charges, long lead times, schedule cost penalties design refinements. Recently, Actel joined with Space Electronics, Inc. (SEi) combine Actel's antifuse-based FPGAs with SEi's RAD-PAK® package shielding technology. This technology incorporates radiation shielding FPGA package, eliminating requirement box- board-level shielding significantly improving total ionizing dose survivability Actel devices. 1280ARP 14100ARP provide high-reliability, low-risk, fast time-to-launch solution that survives wide subset Earth orbits deep space environments. 1280ARP device uses A1280A RAD-PAK® package. This device from Family Actel FPGAs, utilizes two-module architecture that consists combinatorial modules (C-modules) sequential modules (S-modules) optimized both combinatorial sequential designs. Based Actel's patented channeled array architecture, 1280ARP 8,000 ASIC-equivalent gates user I/Os. 1280ARP device fully pin- function-compatible with commercially-equivalent A1280A-CQ172C device easy inexpensive prototyping. 14100ARP device uses A14100A RAD-PAK® package. This device from Family Actel devices, which also utilizes two-module architecture. 14100ARP offers additional device resources above 1280ARP, including increased gates (10,000 gate array equivalent gates), higher I/Os (228), faster performance. 14100ARP device fully pin- function-compatible with commercially-equivalent A14100A-CQ256C device easy inexpensive prototyping.
FEATURES
Radiation Characteristics RAD-PAK® package technology from Space Electronics, Inc. Improved Total Ionizing Dose (TID) survivability improve 2-10x over standard package achieve krads (Si) some orbits Packages: 172-pin 256-pin RAD-PAK® ceramic quad flat pack Offered packaging screening Class High Density Performance 16,000 20,000 gates 8,000 10,000 ASIC equivalent gates on-chip performance user I/Os four fast, low-skew block networks
Memory
Easy Logic Integration Non-volatile, user programmable Pin-compatible commercial devices available prototyping Highly predictable performance with 100% automatic place route 100% resource utilization with 100% pin-locking Secure programming technology prevents reverse engineering design theft Permanently programmed operation power-up Unique in-system diagnostic debug facility with Silicon Explorer Actel Designer Series Design Tools, supported Cadence, Exemplar, Mentor Graphics, Model Technology, Synopsys, Synplicity Viewlogic Design Entry Simulation Tools\
1029.99Rev0
data sheets subject change without notice
(858) 452-4167 Fax: (858) 452-5499 www.spaceelectronics.com
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
PRODUCT FAMILY PROFILE
DEVICE Gates ASIC Equivalent Gates Equivalent Gates Equivalent Package 20-Pin Equivalent Packages Logic Modules S-Modules C-Modules User I/Os CQFP Package Count Performance System Speed (maximum) Ordering Information Part Number (Class Part Number (E-Flow) Commercial Equivalent Prototyping 1280ARP 16,000 8,000 20,000 1,232 1280ARP-CQ172B 1280ARP-CQ172E A1280A-CQ172C 14100ARP 20,000 10,000 25,000 1,377 14100ARP-CQ256B 14100ARP-CQ256E A14100A-CQ256C
Memory
Radiation Survivability
bare both 1280ARP 14100ARP devices have some inherent total dose radiation survivability. levels which these bare able survive varies device type. Actel provides Group testing bare that gives indication characteristics. These results provided reference customer evaluation, testing performed MIL-STD-883, Method 1019.5 Space Electronics, Inc. radiation survivability levels RAD-PAK® devices vary number factors. customer must evaluate determine applicability these devices their specific design environmental requirements.
Radiation Performance RAD-PAK® FPGAs
components natural radiation space consist trapped electrons, trapped protons, galactic cosmic rays, solar flare protons, alpha particles. Depending orbit deep space probe mission, energy levels magnitude each component will vary. Since shielding effectiveness dependent radiation component type energy level, overall performance RAD-PAK® FPGAs will vary with application. Figure Figure show typical applications different orbits. These figures show amount mission dose that expected when given amount shielding utilized sample orbits. closer examination shielding RAD-PAK® shielding shows specific requirements components originated. Figure shows typical orbit degrees, years. Under these conditions, typical satellite designers might have aluminum shield between components outside environment. figure shows that shield average thickness yields approximately KRad (Si) inside shield. This specification becomes design requirement active components satellite. When RAD-PAK® shielding added shielding, shown line, total dose seen component only krad (Si). When second orbit (35,790 degrees, years) examined using same methodology, similar results achieved higher total dose levels. Figure shows that average shielding provides protection krad(Si). RAD-PAK® design brings total dose seen device level down krad (Si). above discussion shows RAD-PAK® products shield significant levels total dose seen level. ability Actel FPGA meet these lower levels total dose radiation make RAD-PAK® FPGAs design choice many space applications.
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
proper application RAD-PAK® FPGA products, following information should available: Orbit mission Satellite level shielding thickness type Mission dose shielding thickness curves Actel personnel then assist determining whether RAD-PAK® FPGA devices usable customer's application radiation requirements.
FIGURE SPACE-LEVEL TOTAL DOSE: TYPICAL ORBIT 98o, YEARS
Memory
FIGURE SPACE-LEVEL TOTAL DOSE: TYPICAL ORBIT 35,790 YEARS
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
FIGURE RAD-PAK® TOTAL DOSE SHIELDING: TYPICAL ORBIT 98o, YEARS
Memory
FIGURE RAD-PAK® TOTAL DOSE SHIELDING: TYPICAL ORBIT 35,790 YEARS
Disclaimer
radiation performance information provided information purposes only guaranteed. total dose effects bare lot-dependent, Actel does warrant that future devices will continue exhibit similar radiation characteristics. addition, nature RAD-PAK®
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
shielding, actual performance vary widely variety factors, including limited characteristics orbit, radiation environment, proximity satellite exterior, amount inherent shielding from other sources within satellite actual bare variations. these reasons, Actel does warrant level radiation survivability, solely responsibility customer determine whether device will meet requirements specific design.
Design Tool Support
with Actel FPGAs, RAD-PAK® devices fully supported Actel's Designer Series development tools, which include: DirectTime automated, timing-driven place route ACTgen fast development using wide range macro functions Designer Series supports industry-leading VHDL- Verilog-based design tools, including synthesis tools from industry leaders such Exemplar Logic, Synplicity, Synopsys. addition, RAD-PAK® devices supported Actel's Silicon Explorer diagnostic debugging tool kit. Silicon Explorer dramatically reduces verification time from several hours cycle seconds enabling real-time, in-circuit debugging. Silicon Explorer includes: Probe Pilot, high-speed signal acquisition control tool that samples data (asynchronous) (synchronous). Probe Pilot features probing channels connects user's standard serial port connection. Diagnostic software, which turns into fully-featured, logic analyzer easy graphical analysis waveforms. Silicon Explorer's internal probe circuitry enables 100% observability into device's internal nodes. Silicon Explorer also functions 18-channel logic analyzer that automatically displays signals board.
Memory
RAD-PAK® DEVICE ORDERING INFORMATION
1280ARP
Package Type Ceramic Quad Flat Pack (CQFP) Speed Grade Standard Speed Approximately Faster than Standard Part Number 1280ARP=8,000 Gates-RAD-PAK® 14100ARP=10,000 Gates-RAD-PAK®
Designer Series also supports design entry simulation tools from Cadence, Exemplar, Mentor Graphics, Model Technology, Synopsys, Synplicity Viewlogic.
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
DEVICE RESOURCES
FPGA DEVICE TYPE LOGIC MODULES GATE ARRAY EQUIVALENT GATES CQFP 172-PIN 1280ARP 14100ARP 1232 1377 8000 10000 -USER I/OS CQFP 256-PIN -228
Architectural Overview
1280ARP 14100ARP architecture composed fine-grained logic modules that produce fast, efficient logic designs. devices composed logic modules, routing resources, clock networks, modules, which building blocks fast logic designs.
Logic Modules
Both devices contain types logic modules: combinatorial (C-modules) sequential (S-modules). C-module, shown Figure implements following function: where: S0=A0*B0 S1=A1+B1
Memory
FIGURE C-MODULE IMPLEMENTATION
S-module, shown Figure designed implement high-speed sequential functions within single logic module. S-module implements same combinatorial logic function C-module, adds sequential element. sequential element configured either D-type flip-flop transparent latch. increase flexibility, S-module register bypassed implements purely combinatorial logic.
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
FIGURE S-MODULE IMPLEMENTATION
GATE
7-Input Function Plus D-Type Flip-Flop with Clear
7-Input Function Plus Latch
GATE
Memory
4-Input Function Plus Latch with Clear
8-Input Function (Same C-Module)
Flip-flops also created using C-modules. single event upset (SEU) characteristics differ between S-module flip-flop flip-flop created using C-modules. details, Radiation Specifications section this Data Sheet "Design Techniques RadHard FPGAs" Application Note http://www.actel.com/hirel
Description
CLKA Clock (Input)
clock input global clock distribution networks. clock input buffered prior clocking logic modules. This also used I/O.
CLKB Clock (Input)
clock input global clock distribution networks. clock input buffered prior clocking logic modules. This also used I/O.
DCLK Diagnostic Clock (Input)
clock input diagnostic probe device programming. DCLK active when MODE HIGH. This functions when MODE LOW.
Ground
supply voltage.
HCLK Dedicated (Hard-Wired) Array Clock (Input)
14100ARP A14100A only. clock input sequential modules. This input directly wired each S-module, offering clock speeds independent number S-modules being driven. This also used I/O.
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
Input/Output (Input, Output)
functions input, output, tri-state, bi-directional buffer. Input output levels compatible with standard CMOS specifications. 1280ARP, unused pins automatically driven LOW. 14100ARP, unused pins automatically tri-stated.
IOCLK Dedicated (Hard-Wired) Clock (Input)
14100ARP A14100A only. clock input modules. This input directly wired each module, offering clock speeds independent number modules being driven. This also used I/O.
IOPCL Dedicated (Hard-Wired) Preset/Clear (Input)
14100ARP A14100A only. input preset clear. This global input directly wired preset clear inputs registers. This functions when preset clear macros used.
MODE Mode (Input)
MODE controls diagnostic pins (DCLK, PRA, PRB, SDI). When MODE HIGH, special functions active. When MODE LOW, pins function I/Os. provide debugging capability, MODE should terminated through resistor that MODE pulled HIGH when required.
Connection
This connected circuitry within device.
PRA, Probe (Output)
Probe used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when debugging been completed. accessible when MODE HIGH. This functions when MODE LOW.
PRB, Probe (Output)
Memory
Probe used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when debugging been completed. accessible when MODE HIGH. This functions when MODE LOW.
Serial Data Input (Input)
Serial data input diagnostic probe device programming. active when MODE HIGH. This functions when MODE LOW.
Supply Voltage
HIGH supply voltage.
MIL-STD-883 PRODUCT FLOW
STEP SCREEN Internal Visual Temperature Cycling Constant Acceleration Seal Fine b.Gross Visual Inspection Pre-Burn-In Electrical Parameters Burn-in Test Interim (Post-Burn-In) Electrical Parameters METHOD 2010, Test Condition 1010, Test Condition 2001, Test Condition (Min), Orientation Only 1014 100% 100% 2009 accordance with applicable Actel device specification 1015 Test Condition hours 125°C Min. accordance with applicable Actel device specification 100% 100% 100% 100% CLASS REQUIREMENT 100% 100% 100%
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
MIL-STD-883 PRODUCT FLOW
STEP 10.0 SCREEN Percent Defective Allowable Final Electrical Test Static Tests (1)25°C (Subgroup Table (2)-55°C +125°C (Subgroups Table b.Dynamic Functional Tests (1)25°C (Subgroup Table (2)-55°C +125°C (Subgroups Table Switching Tests 25°C (Subgroup Table 11.0 METHOD accordance with applicable Actel device specification 100% 5005 5005 CLASS REQUIREMENT Lots
100% 5005 5005
5005
100%
Memory
Qualification Quality Confirmation Inspection Test Sam- 5005 Selection (Group Group External Visual 2009
Lots
12.0
100%
EXTENDED FLOW1
STEP SCREEN Wafer Acceptance Destructive In-Line Bond Pull Internal Visual Serialization Temperature Cycling Constant Acceleration Visual Inspection Particle Impact Noise Detection Radiographic Pre-Burn-In Test Burn-in Test Interim (Post-Burn-In) Electrical Parameters Reverse Bias Burn-In Interim (Post-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation 1010, Test Condition 2001, Test Condition (Min), Orientation Only 2009 2020, Test Condition 2012 accordance with applicable Actel device specification 1015, Test Condition hours 125°C minimum accordance with applicable Actel device specification 1015, Test Condition hours 150°C minimum accordance with applicable Actel device specification Functional Parameters 25°C METHOD 5007 with Step Coverage Waiver 2011, Test Condition 2010, Test Condition REQUIREMENT Lots Sample 100% 100% 100% 100% 100% 100% Performed 100% 100% 100% 100% 100% Lots
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
EXTENDED FLOW1
STEP SCREEN Final Electrical Test Static Tests 25°C (Subgroup Table1) -55°C +125°C (Subgroups Table b.Dynamic Functional Tests 25°C (Subgroup Table -55°C +125°C (Subgroups Table1) Switching Tests 25°C (Subgroup Table Seal Fine b.Gross Qualification Quality Conformance Inspection Test Sample Selection External Visual METHOD accordance with Actel applicable device specification 5005 5005 100% 5005 5005 REQUIREMENT 100% 100%
5005 1014
100% 100%
5005 2009
Group Group 100%
Memory
offers extended flow customers that require additional screnning beyond requirements MIL-STD-883, Class compliant requirements MIL-STD-883, Paragraph 1.2.1, MIL-I-38535, Appendix offering this extended flow incorporating majority screening procedures outlined Method 5004 MIL-STD-883 Class exceptions Method 5004 shown notes below. Wafer acceptance performed Method 5007; however, step coverage requirement specified Method 2018 must waived. Method 5004 required 100%, non-destructive bond pull Method 2023. Substitutes destructive bond pull Method 2011, Condition sample basis only. Radiographic test performed since RAD-PAK® package technology screens X-rays test results uninformative.
ABSOLUTE MAXIMUM RATINGS
FREE TEMPERATURE RANGE
PARAMETER Supply Voltage 2,3,4 Input Voltage Output Voltage Source Sink Current Storage Temperature SYMBOL II/O TSTG -0.5 -0.5 -0.5 UNIT
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Device should operated outside recommended operating conditions. VCC, except during device programming. VCC, except during device programming. GND, except during device programming. Device inputs normally high impedance draw extremely current. However, when input voltage greater than 0.5V less than 0.5V, internal protection diode will forward-biased draw excessive current.
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
RECOMMENDED OPERATING CONDITIONS
PARAMETER Temperature Range Power Supply Tolerance COMMERCIAL MILITARY
UNIT
%VCC
power supplied must recommended operating range. more information, please refer "Power-Up Design Considerations" application note www.actel.com. Ambient temperature (TA) used commercial industrial; case temperature (TC) used military.
Package Thermal Characteristics
device junction case thermal characteristic Maximum junction temperature 150°C. sample calculation absolute maximum power dissipation allowed CQFP 172-pin package military temperature follows:
Memory
Max. junction temp. (°C) Max. military temp. 150°C 125°C 4.2W 6°C/W °C/W
PACKAGE TYPE Ceramic Quad Flat Pack
COUNT
UNITS °C/W
ELECTRICAL SPECIFICATIONS
PARAMETER HIGH Level Output Level Output HIGH Level Input Level Input Input Leakage 3-State Output Leakage Capacitance Standby Supply Current Dynamic Supply Current SYMBOL
TEST CONDITION (CMOS) (CMOS) (CMOS) Inputs Inputs GND, "Power Dissipation" Section
-2.0 -0.3
-0.4
UNITS
ICC(S) ICC(D)
Actel devices drive receive either CMOS signal levels. assignment I/Os CMOS required. Tested output time, min. tested; information only. VOUT MHz.
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
Power Dissipation
General Power Equation
[ICCstandby ICCactive] (VCC VOH)
Where: ICCstandby current flowing when inputs outputs changing. ICCactive current flowing CMOS switching. IOL, sink/source currents. VOL, level output voltages. equals number outputs driving loads VOL. equals number outputs driving loads VOH. accurate determination problematical because their values depend family type, design details, system I/O. power divided into components: static active. Static Power Component Actel FPGAs have small static power components that result power dissipation lower than that PALs PLDs. integrating multiple PALs PLDs into FPGA, even greater reduction board-level power dissipation achieved. power standby current typically small component overall power. Standby power calculated below commercial, worst-case conditions.
Memory
Family 1280ARP, 14100ARP
5.25V
Power 10.5
static power dissipated loads depends number outputs driving HIGH load current. Again, this value typically small. instance, 32-bit sinking 0.33V will generate with outputs driving LOW, with outputs driving HIGH. Active Power Component Power dissipation CMOS devices usually dominated active (dynamic) power dissipation. This component frequency-dependent, function logic external I/O. Active power dissipation results from charging internal chip capacitances interconnect, unprogrammed antifuses, module inputs, module outputs, plus external capacitance board traces load device inputs. additional component active power dissipation totem pole current CMOS transistor pairs. effect associated with equivalent capacitance that combined with frequency voltage represent active power dissipation. Equivalent Capacitance power dissipated CMOS circuit expressed Equation
Power (uW) VCC2
where: equivalent capacitance expressed power supply volts (V). switching frequency MHz.
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
Equivalent capacitance calculated measuring ICCactive specified frequency voltage each circuit component interest. Measurements made over range frequencies fixed value VCC. Equivalent capacitance frequency-independent, results used over wide range operating conditions. Equivalent capacitance values shown below.
VALUES ACTEL FPGAS
1280ARP Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR) Dedicated Clock Buffer Loads (CEQCD) Clock Buffer Loads (CEQCI) 12.9 23.8 14100ARP 10.4
calculate active power dissipated from complete design, switching frequency each part logic must known. Equation shows piece-wise linear summation over components. Since 1280ARP routed array clocks, dedicated_Clk IO_Clk terms apply. 14100ARP device, terms will apply.
Memory
Power VCC2 CEQM* fm)modules CEQI* fn)inputs (CEQO+ fp)outputs CEQCR fq1)routed_Clk1 fq1)routed_Clk1 CEQCR fq2)routed_Clk2 fq2)routed_Clk2 CEQCD fs1)dedicated_Clk CEQCI fs2)IO_Clk](2)
where:
CEQM CEQI CEQO CEQCR CEQCD CEQCI
1029.99Rev0
Number logic modules switching Number input buffers switching Number output buffers switching Number clock loads first routed array clock Number clock loads second routed array clock Fixed capacitance first routed array clock Fixed capacitance second routed array clock Fixed number clock loads dedicated array clock (14100ARP only) Fixed number clock loads dedicated clock (14100ARP only) Equivalent capacitance logic modules Equivalent capacitance input buffers Equivalent capacitance output buffers Equivalent capacitance routed array clock Equivalent capacitance dedicated array clock Equivalent capacitance dedicated clock Output lead capacitance Average logic module switching rate Average input buffer switching rate
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
Average output buffer switching rate Average first routed array clock rate Average second routed array clock rate Average dedicated array clock rate (14100ARP only) Average dedicated clock rate (14100ARP only)
Fixed Capacitance Values Actel FPGAs Device Type 1280ARP 14100ARP routed_Clk1 routed_Clk2
Fixed Clock Loads (s1/s2-ACT Only) Clock Loads Dedicated Array Clock Clock Loads Dedicated Clock
Memory
Device Type 14100ARP Determining Average Switching Frequency
determine switching frequency design, must have detailed understanding data input values circuit. guidelines table below meant represent worst-case scenarios; they generally used predict upper limits power dissipation.
1280ARP
Logic Modules Input Switching Outputs Switching First Routed Array Clock Loads (q1) Second Routed Array Clock Loads (q2) Load Capacitance (CL) Average Logic Module Switching Rate (fm) Average Input Switching Rate (fn) Average Output Switching Rate (fp) Average First Routed Array Clock Rate (fq1) Average Second Routed Array Clock Rate (fq2) Average Dedicated Array Clock Rate (fs1) Average Dedicated Clock Rate (fs2)
1029.99Rev0
Combinatorial Modules Inputs/4 Outputs/4 Sequential Modules Sequential Modules F/10 F/10
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
14100ARP
Logic Modules Input Switching Outputs Switching First Routed Array Clock Loads (q1) Second Routed Array Clock Loads (q2) Load Capacitance (CL) Average Logic Module Switching Rate (fm) Average Input Switching Rate (fn) Average Output Switching Rate (fp) Average First Routed Array Clock Rate (fq1) Average Second Routed Array Clock Rate (fq2) Average Dedicated Array Clock Rate (fs1) Average Dedicated Clock Rate (fs2) Combinatorial Modules Inputs/4 Outputs/4 Sequential Modules Sequential Modules F/10 F/10
Memory
1280ARP TIMING MODEL
Input Delays Module tINYL Internal Delays Combinatorial Logic Module tIRD2 tDLH 16.5 tPD1 tRD1 tRD2 tRD4 tRD8 10.8 Predicted Routing Delays Output Delays Module
tINH tINSU tINGL Sequential Logic Module
Combinatorial Logic included tSUD
Module tDLH 16.5
tRD1
tENHZ 11.5
tOUTH tOUTSU tGLH 14.6
Array Clocks
tCKH 15.7 FMAX
tSUD
Values shown 1280A worst case military conditions.
1029.99Rev0
Input module predicted routing delay
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
14100ARP TIMING MODEL
Input Delays Module tINY Internal Delays Combinatorial Logic Module tIRD2 tDHS 10.8 tRD1 tRD4 tRD8 Module tDHS 10.8 Predicted Routing Delays Output Delays Module
tINH tINSU tICKY
Sequential Logic Module
Combinatorial Logic included tSUD
tRD1
tENZHS
Array Clock
tHCKH FHMAX
tSUD
tOUTH tOUTSU tCKHS 16.0
Memory
Clock
tIOCKH (pad-to-pad) FIOMAX
PARAMETER MEASUREMENT
OUTPUT BUFFER DELAYS
TRIBUFF test loads (shown below)
1.5V tENZL 1.5V tENLZ
1.5V tENZH tENHZ
1.5V
tDLH
tDHL
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
TEST LOAD
Load (Used measure propagation delay) Load (Used measure rising/falling edges) output under test
output under test
tPLZ/tPZL tPHZ/tPZH
INPUT BUFFER DELAYS
Memory
INBUF
tINYH 1.5V 1.5V tINYL
COMBINATORIAL MACRO DELAYS
tPHL tPLH tPLH tPHL
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
FLIP-FLOPS LATCHES (1280ARP)
(Positive Edge-Triggered) tSUD tSUENA tHENA tWCLKA
Memory
PRE, tWASYN
represents data functions involving multiplexed flip-flops.
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
FLIP-FLOPS LATCHES (14100ARP)
(Positive Edge-Triggered)
tSUD tSUENA tHENA tWCLKA
Memory
tCLR tWASYN
represents data functions involving multiplexed flip-flops.
INPUT BUFFER LATCHES (1280ARP)
CLKBUF
IBDL
tINH tINSU tHEXT tSUEXT
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
OUTPUT BUFFER LATCHES (1280ARP)
OBDLHS
tOUTSU tOUTH
1280ARP TIMING CHARACTERISTICS (WORST CASE MILITARY CONDITIONS; 3.0V,
LOGIC MODULE PROPAGATION DELAYS PARAMETER tPD1 DESCRIPTION Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q -`-1 SPEED -`STD' SPEED UNITS
Memory
PREDICTED ROUTING DELAYS tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay -2.4 -2.8 10.8
SEQUENTIAL TIMING CHARACTERISTICS tSUD tSUENA tHENA tWCLKA tWASYN tINH
1029.99Rev0
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold
16.4
22.1
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
1280ARP TIMING CHARACTERISTICS (WORST CASE MILITARY CONDITIONS; 3.0V,
LOGIC MODULE PROPAGATION DELAYS PARAMETER tINSU tOUTH tOUTSU fMAX DESCRIPTION Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency -`-1 SPEED -`STD' SPEED UNITS
dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst case operation conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Direct Time Analyzer utility. Set-up hold timing parameters input buffer latch defined with respect input. External set-up/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal set-up (hold) time.
Memory
1280ARP TIMING CHARACTERISTICS
(WORST CASE MILITARY CONDITIONS; 3.0V, INPUT MODULE PROPAGATION DELAYS PARAMETER tINYH tINYL tINGH tINGL DESCRIPTION Pad-to-Y HIGH Pad-to-Y G-to-Y HIGH G-to-Y -`-1' SPEED -`STD' SPEED UNITS
INPUT MODULE PREDICTED ROUTING DELAYS tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tCKH tCKL tPWH FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay -6.2 12.9 -7.3 10.5 15.2
GLOBAL CLOCK NETWORK Input HIGH Input HIGH Minimum Pulse Width HIGH -6.9 13.3 17.9 13.3 18.2 -8.1 15.7 21.1 15.7 21.4
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
1280ARP TIMING CHARACTERISTICS (WORST CASE MILITARY CONDITIONS; 3.0V,
INPUT MODULE PROPAGATION DELAYS PARAMETER tPWL tCKSW tSUEXT tHEXT fMAX DESCRIPTION Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency -0.0 13.8 13.7 16.0 -`-1' SPEED -0.6 -0.0 13.8 16.2 18.9 -`STD' SPEED -0.6 UNITS
These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst case operating conditions. Post-route timing analysis simulation required determine actual worst case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
Memory
1280ARP TIMING CHARACTERISTICS
(WORST CASE MILITARY CONDITIONS, 3.0V, OUTPUT MODULE TIMING PARAMETER DESCRIPTION SPEED `STD' SPEED UNIT
OUTPUT MODULE TIMING tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable-to-Pad HIGH Enable-to-Pad Enable-to-Pad HIGH Enable-to-Pad G-to-Pad HIGH G-to-Pad Delta HIGH Delta HIGH -11.0 13.9 12.3 16.1 11.5 12.4 15.5 0.09 0.17 -13.0 16.4 14.4 19.0 11.5 13.6 14.6 18.2 0.11 0.20 ns/pF ns/pF
CMOS OUTPUT MODULE TIMING tDLH tDHL tENZH
1029.99Rev0
Data-to-Pad HIGH Data-to-Pad Enable-to-Pad HIGH
14.0 11.7 12.3
16.5 13.7 14.4
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
1280ARP TIMING CHARACTERISTICS
(WORST CASE MILITARY CONDITIONS, 3.0V, OUTPUT MODULE TIMING PARAMETER tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL DESCRIPTION Enable-to-Pad Enable-to-Pad HIGH Enable-to-Pad G-to-Pad HIGH G-to-Pad Delta HIGH Delta HIGH -`-1 SPEED 16.1 11.5 12.4 15.5 0.17 0.12 -`STD' SPEED 19.0 11.5 13.6 14.6 18.2 0.20 0.15 ns/pF ns/pF UNIT
information found "Simultaneously Switching Output Limits Actel FPGAs" Application Note www.actel.com. Delays based loading.
Memory
14100ARP TIMING CHARACTERISTICS 3.0V, 125°C)
LOGIC MODULE PROPAGATION DELAYS PARAMETER tCLR DESCRIPTION Internal Array Module Sequential Clock-to-Q Asynchronous Clear-to-Q -`-1' SPEED -`STD' SPEED UNITS
PREDICTED ROUTING DELAYS tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWASYN tWCLKA fMAX FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay -1.3 -1.5
LOGIC MODULE SEQUENTIAL TIMING Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency -100 11.6
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
dual-module macros, tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst case performance. Post-rout timing based actual routing delay measurements performed device prior shipment.
14100ARP TIMING CHARACTERISTICS (WORST CASE MILITARY CONDITIONS, 3.0V,
MODULE INPUT PROPAGATION DELAYS PARAMETER tINY tICKY tOCKY tICLRY tOCLRY DESCRIPTION Input Data Pad-to-Y Input IOCLK Pad-to-Y Output IOCLK Pad-to-Y Input Asynchronous Clear-to-Y Output Asynchronous Clear-to-Y -`-1 SPEED -`STD' SPEED UNIT
Memory
PREDICTED INPUT ROUTING DELAYS tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay -1.3 -1.5
MODULE SEQUENTIAL TIMING Input Flip-Flop Data Hold Input Flip-Flop Data Set-Up Input Data Enable Hold Input Data Enable Set-Up Output Flip-Flop Data Hold Output Flip-Flop Data Set-Up Output Data Enable Hold Output Data Enable Set-Up -0.0 10.0
Routing delays typical designs across worst case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
14100ARP TIMING CHARACTERISTICS
(WORST CASE MILITARY CONDITIONS, 3.0V, MODULE OUTPUT TIMING PARAMETER tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS DESCRIPTION Data-to-Pad, High Slew Data-to-Pad, Slew Enable-to-Pad, H/L, High Slew Enable-to-Pad, H/L, Slew Enable-to-Pad, High Slew Enable-to-Pad, Slew IOCLK Pad-to-Pad H/L, High Slew IOCLK Pad-to-Pad H/L, Slew Delta HIGH, High Slew Delta HIGH, Slew Delta HIGH LOW, High Slew Delta HIGH LOW, Slew -`-1 SPEED 11.9 10.9 11.9 10.9 12.2 17.8 0.04 0.07 0.05 0.07 -`STD' SPEED 14.0 12.8 14.0 12.8 14.0 17.8 0.04 0.08 0.06 0.08 ns/pF ns/pF UNIT
Memory
ns/pF ns/pF
MODULE CMOS OUTPUT TIMING1 tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Data-to-Pad, High Slew Data-to-Pad, Slew Enable-to-Pad, H/L, High Slew Enable-to-Pad, H/L, Slew Enable-to-Pad, High Slew Enable-to-Pad, Slew IOCLK Pad-to-Pad H/L, High Slew IOCLK Pad-to-Pad H/L, Slew Delta HIGH, High Slew Delta HIGH, Slew Delta HIGH LOW, High Slew Delta HIGH LOW, Slew -9.2 17.3 13.1 11.6 10.9 14.4 20.2 0.06 0.11 0.04 0.05 -10.8 20.3 15.5 14.0 12.8 16.0 22.4 0.07 0.13 0.05 0.06 ns/pF ns/pF ns/pF ns/pF
information found "Simultaneously Switching Output Limits Actel FPGAs" application note www.actel.com. Delays based loading.
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
14100ARP TIMING CHARACTERISTICS (WORST CASE MILITARY CONDITIONS, 3.0V,
DEDICATED (HARD-WIRED) CLOCK NETWORK PARAMETER tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX DESCRIPTION Input HIGH (Pad Module Input) Minimum Pulse Width HIGH Minimum Pulse Width Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency -4.8 -9.9 -`-1' SPEED -0.9 -100 -5.7 -11.6 -`STD' SPEED -1.0 UNIT
DEDICATED (HARD-WIRED) ARRAY CLOCK NETWORK tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input HIGH (Pad S-Module Input) Input HIGH (Pad S-Module Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency -4.8 -9.9 -5.5 -0.9 -100 -5.7 -11.6 -6.4 -1.0
Memory
ROUTED ARRAY CLOCK NETWORKS tRCKH tRCKL tRPWH tRPWL tRCKSW fRMAX Input HIGH (FO=256) Input HIGH (FO=256) Min. Pulse Width HIGH (FO=256) Min. Pulse Width (FO=256) Maximum Skew (FO=128) Minimum Period (FO=256) Maximum Frequency (FO=256) -6.3 -12.9 -9.0 -1.9 -7.1 -14.5 -10.5 10.5 -2.1
CLOCK-TO-CLOCK SKEWS tIOHCKSW tIORCKSW tHRCKSW Clock H-Clock Skew Clock R-Clock Skew H-Clock R-Clock Skew max.)
Delays based loading.
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
PACKAGE ASSIGNMENTS
172-PIN (TOP VIEW)
Memory
172-PIN CQFP
NUMBER
1029.99Rev0
1280ARP FUNCTION MODE
NUMBER
1280ARP FUNCTION
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
172-PIN CQFP
NUMBER
1029.99Rev0
1280ARP FUNCTION
NUMBER
1280ARP FUNCTION
Memory
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
172-PIN CQFP
NUMBER
1029.99Rev0
1280ARP FUNCTION SDI,
NUMBER
1280ARP FUNCTION
Memory
PRA, CLKA, CLKB, PRB,
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
172-PIN CQFP
NUMBER 1280ARP FUNCTION DCLK, NUMBER 1280ARP FUNCTION
Unused pins designated outputs Designer driven LOW. MODE should terminated through resistor enable Silicon Explorer usage; otherwise, terminated directly GND.
PACKAGE ASSIGNMENTS
256-PIN (TOP VIEW)
Memory
256-PIN CQFP
NUMBER
1029.99Rev0
14100ARP FUNCTION SDI,
NUMBER
14100ARP FUNCTION
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
256-PIN CQFP (continued)
NUMBER
1029.99Rev0
14100ARP FUNCTION MODE
NUMBER
14100ARP FUNCTION
Memory
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
256-PIN CQFP (continued)
NUMBER
1029.99Rev0
14100ARP FUNCTION PRB, HCLK,
NUMBER
14100ARP FUNCTION IOPCL,
Memory
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
256-PIN CQFP (continued)
NUMBER
1029.99Rev0
14100ARP FUNCTION IOCLK,
NUMBER
14100ARP FUNCTION
Memory
CLKA, CLKB, PRA,
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS
256-PIN CQFP (continued)
NUMBER 14100ARP FUNCTION NUMBER 14100ARP FUNCTION
Memory
DCLK,
Important Notice: These data sheets created using chip manufacturers published specifications. Space Electronics verifies functionality testing parameters either 100% testing, sample testing characterization. specifications presented within these data sheets represent latest most accurate information available date. However, these specifications subject change without notice Space Electronics assumes responsibility this information. Space Electronics' products authorized critical components life support devices systems without express written approval from Space Electronics. claim against Space Electronics Inc. must made within days from date shipment from Space Electronics. Space Electronics' liability shall limited replacement defective parts.
1029.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.

RADIATION TOLERANT RAD-PAK® FIELD PROGRAMMABLE GATE ARRAYS GENERAL DES

Top Searches for this datasheet

Other recent searches