VDDQ VSSQ VDDQ VSSQ A10/AP VSSQ VDDQ VSSQ VDDQ NC/A13 NC/RFU NC/A12

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VDDQ VSSQ VDDQ VSSQ A10/AP VSSQ VDDQ VSSQ VDDQ NC/A13 NC/RFU NC/A12

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SPACE PRODUCTS
VDDQ VSSQ VDDQ VSSQ A10/AP VSSQ VDDQ VSSQ VDDQ NC/A13 NC/RFU NC/A12
GIGABIT SYNCHRONOUS DRAM
97SD10004RP
SINGLE EIGHT HIGH STACK
Memory
DUAL FOUR HIGH STACKS
FEATURES:
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation cycle with address programs latency Burst length Page Burst type (Sequential Interleave) inputs sampled positive going edge system clock. Burst read single-bit write operation masking Auto self refresh 64ms refresh period Cycle) Total dose tolerance krads (Si); dependent upon orbit SEL: Single Event Latch-up observed SELTH MeV/mg/cm2 SEU: LETTH MeV/mg/cm2 cross section 3E-08 cm2/bit
1207.99Rev0
DESCRIPTION:
Space Electronics' offering Gigabit synchronous high data rate Dynamic very compact hermetic package using stacked TSOPs. Synchronous design allows precise cycle control with system clock transactions possible every clock cycle. Range operating frequencies, programmable burst length programmable latencies allow same device useful variety high bandwidth, high performance memory system applications space. patented radiation-hardened Rad-Pak® technology incorporates radiation shielding microcircuit package. eliminates shielding while providing required lifetime orbit. This product available with packaging screening Class This product upgradable with identical footprints.
data sheets subject change without notice
(858) 452-4167 Fax: (858) 452-5499 www.spaceelectronics.com
©1999 Space Electronics Inc. rights reserved.
97SD10004RP
BLOCK DIAGRAM
Data Power/ Controls
GIGABIT SYNCHRONOUS DRAM
Address 0-11
Memory
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage relative Voltage supply relative Storage temperature Power dissipation Short circuit current SYMBOL VIN, VOUT VDD, VDDQ TSTG -1.0 -1.0 UNIT
Permanent device damage occur "ABSOLUTE MAXIMUM RATINGS" exceeded. Functional operation should restricted recommended operating condition. Exposure higher than recommended voltage extended periods time could affect device reliability.
TABLE OPERATING CONDITIONS RECOMMENDED OPERATING CONDITIONS (VOLTAGE REFERENCED 85°C)
PARAMETER Supply voltage Input logic high voltage Input logic voltage Output logic high voltage (IOH -2mA)
1207.99Rev0
SYMBOL VDD, VDDQ
-0.3
VDD+0.3
UNIT
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
97SD10004RP
PARAMETER Output logic voltage (IOL 2mA) Input leakage current SYMBOL
GIGABIT SYNCHRONOUS DRAM
TABLE OPERATING CONDITIONS RECOMMENDED OPERATING CONDITIONS (VOLTAGE REFERENCED 85°C)
UNIT
(max) 5.6V AC.The overshoot voltage duration 3ns. (min) -2.0V undershoot voltage duration 3ns. input VDDQ. Input leakage currents include HI-Z output leakage bi-directional buffers with Tri-State outputs. Dout disabled, VOUT VDDQ.
TABLE CAPACITANCE
(VDD 3.3V, MHZ, VREF 1.4V Clock RAS, CAS, CKE, Address
SYMBOL CCLK CADD COUT
UNIT
Memory
only specify maximum value only specify maximum value only specify maximum value
TABLE CHARACTERISTICS
85°C UNLESS OTHERWISE SPECIFIED.) PARAMETER Operating current (One bank active) SYMBOL ICC1 TEST CONDITION Burst length tRC(min) VIL(max), VIL(max), VIH(min), VIH(min), Input signals changed time during 20ns VIH(min), VIL(max), Input signals stable VIL(max), VIL(max), VIH(min), VIH(min), Input signals changed time during UNIT
Precharge standby current power-down mode Precharge standby current power-down mode
ICC2P ICC2PS ICC2N ICC2NS
Active standby current power-down mode Active standby current power-down mode (One bank active)
ICC3P ICC3PS ICC3N
1207.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
97SD10004RP
TABLE CHARACTERISTICS 85°C UNLESS OTHERWISE SPECIFIED.)
PARAMETER Active standby current power-down mode (One bank active) Operating current (Burst mode) SYMBOL ICC3NS ICC4 TEST CONDITION
GIGABIT SYNCHRONOUS DRAM
UNIT
VIH(min), VIL(max), Input signals stable Page burst tCCD CLKs tRC(min) 0.2V
Refresh current Self refresh current Measured with outputs open. Refresh period 64ms.
ICC5 ICC6
TABLE OPERATING TEST CONDITIONS
(VDD 3.3V 0.3V, 70°C)
Memory
PARAMETER Input levels (Vih/Vil) Input timing measurement reference level Input rise fall time Output timing measurement reference level Output load condition
VALUE 2.4/0.4 tr/tf Output Load Circuit
UNIT
3.3V
1.4V
1200
(DC) 2.4V, -2mA OUTPUT (DC) 0.4V, 50pF 50pF OUTPUT
Output Load Circuit
Output Load Circuit
TABLE OPERATING PARAMETER
PARAMETER active active delay delay precharge time
1207.99Rev0
SYMBOL tRRD tRCD
UNIT
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
97SD10004RP
TABLE OPERATING PARAMETER
PARAMETER active time cycle time Last data precharge Last data Active delay Last data col. address delay Last data burst stop2 Col. address col. address stop Number valid output data SYMBOL tRAS tRDL (min) tDAL (min) tCDL (min) tBDL (min) tCCD (min) latency latency
GIGABIT SYNCHRONOUS DRAM
-MAX -100 UNIT
minimum number clock cycles determined dividing minimum time required with clock cycle time then rounding next higher integer. Minimum delay required complete write. parts allow every cycle column address change.
Memory
case precharge interrupt, auto precharge read burst stop.
TABLE CHARACTERISTICS
PARAMETER cycle time valid output delay Output data hold time high pulse width pulse width Input setup time Input hold time output Low-Z output High-Z latency latency Parameters depend programmed latency. clock rising time longer than 1ns, (tr/2-0.5)ns should added parameter. Assumed input rise fall time tf)= 1ns. longer than 1ns, transient time compensation should considered, i.e., [(tr tf)/2-1]ns should added parameter. tested. latency latency latency latency latency latency tSLZ tSHZ tSAC SYMBOL -MAX 1000 1000 UNIT
1207.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
97SD10004RP
PARAMETER Output rise time Output fall time Output rise time 3,4,5 Output fall time SYMBOL CONDITION Measure linear region: 1.2V ~1.8V Measure linear region: 1.2V 1.8V Measure linear region: 1.2V 1.8V Measure linear region: 1.2V 1.8V
GIGABIT SYNCHRONOUS DRAM
TABLE BUFFER OUTPUT DRIVE CHARACTERISTICS
1.37 1.30 2.80 -3.90 4.37 5.60 UNIT V/ns V/ns V/ns V/ns
measurements done with respect VSS. Measured into only, these values characterize tested. Rise time specification based VSS, these values design Fall time specification based VDD, these values design
Memory
1207.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
97SD10004RP
CHARACTERISTICS (PULL-UP)
VOLTAGE 3.45 1.65 100MHZ (mA) -21.1 -34.1 -58.7 -67.3 -73.0 -77.9 -80.8 -88.6 -93.0 100MHZ (mA) -2.4 -27.3 -74.1 -129.2 -153.3 -197.0 -226.2 -248.0 -269.7 -284.3 -344.5 -502.4 66MHZ
GIGABIT SYNCHRONOUS DRAM
66MHz 100MHz Pull-up
(mA) -0.7
-200 -100
-7.5 -13.3 -27.5 -35.5 -41.1 -47.9 -52.4 -72.5
-300 -400
(100MHz) 100MHz)
-500
(66MHz)
-600 VOLTAGE
Memory
-93.0
CHARACTERISTICS (PULL-DOWN)
VOLTAGE 0.65 0.85 1.65 1.95 3.45 100MHZ (mA) 27.5 41.8 51.6 58.0 70.7 72.9 75.4 77.0 77.6 80.3 81.4 100MHZ (mA) 70.2 107.5 133.8 151.2 187.7 194.4 202.5 208.6 212.0 219.6 222.6 66MHZ (mA) 17.7 26.9 33.3 37.6
(100MHz) (100MHz) (66MHz)
46.6 48.0 49.5 50.7 51.5 54.2 54.9
VOLTAGE
1207.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
97SD10004RP
CLAMP @CLK,CKE,CS,DQM
(mA)
GIGABIT SYNCHRONOUS DRAM
Minimum Clamp Current
0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31
VOLTAGE
Memory
CLAMP @CLK,CKE,CS,DQM
-2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2
1207.99Rev0
Minimum Clamp Current
(mA)
VOLTAGE
-57.23 -45.77 -38.26 -31.22 -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
97SD10004RP
GIGABIT SYNCHRONOUS DRAM
TABLE SIMPLIFIED TRUTH TABLE (V=Valid, Care, H=Logic High, L=Logic Low)
COMMAND Register Mode Register Auto Refresh Refresh Entry Self Refresh Exit
CKEn-1 Bank selection banks Entry Exit Entry
CKEn
BA0,1
A10/AP
A11,
CODE Address Column Address A11) Column Address A11)
Bank Active Address Read Column Address Write Column Address Burst Stop Precharge Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
Memory
Clock Suspend Active Power Down
Precharge Power Down Mode Exit Operation Command
issued only banks precharge state. command issued after cycles MRS. Code Operand Code Program keys. (@MRS) Auto refresh functions same refresh DRAM. automatical precharge without precharge command meant "Auto". Auto/self refresh issued only banks precharge state.
1207.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
97SD10004RP
Bank select addresses. both "Low" read, write, active precharge, bank selected. both "Low" "High" read, write, active precharge, bank selected. both "High" "Low" read, write, active precharge, bank selected. both "High" read, write, active precharge, bank selected. A10/AP "High" precharge, ignored banks selected. During burst read write with auto precharge, read/write command issued. Another bank read/write command issued after burst. active assoiated bank issued after burst. Burst stop command valid every burst length.
GIGABIT SYNCHRONOUS DRAM
sampled positive going edge masks data-in very (Write latency makes Hi-Z state data-out cycles after. (Read latency
Memory
1207.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
97SD10004RP
GIGABIT SYNCHRONOUS DRAM
54LD Dual Stack
Memory
54-PIN RAD-PAK® FLAT PACKAGE
SYMBOL 0.500 0.182 0.363 0.363 0.010 0.005 -1.660 -DIMENSION 0.370 0.015 0.010 1.750 1.750 -0.050 -0.195 0.368 -0.208 0.373 0.377 0.020 0.015 2.405 1.670 1.865
F54-01 Note: dimensions inches.
1207.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
97SD10004RP
GIGABIT SYNCHRONOUS DRAM
54LD Single Stack
Memory
54-PIN RAD-PAK® FLAT PACKAGE
SYMBOL 0.500 0.182 0.363 0.363 0.010 0.005 -0.900 -DIMENSION 0.370 0.015 0.010 1.750 1.100 -0.050 -0.195 0.368 -0.208 0.373 0.377 0.020 0.015 2.405 1.300 1.865
F54-02 Note: dimensions inches
1207.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
97SD10004RP
Important Notice:
GIGABIT SYNCHRONOUS DRAM
These data sheets created using chip manufacturers published specifications. Space Electronics verifies functionality testing parameters either 100% testing, sample testing characterization. specifications presented within these data sheets represent latest most accurate information available date. However, these specifications subject change without notice Space Electronics assumes responsibility this information. Space Electronics' products authorized critical components life support devices systems without express written approval from Space Electronics. claim against Space Electronics Inc. must made within days from date shipment from Space Electronics. Space Electronics' liability shall limited replacement defective parts.
Memory
1207.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.

VDDQ VSSQ VDDQ VSSQ A10/AP VSSQ VDDQ VSSQ VDDQ NC/A13 NC/RFU NC/A12

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