8/16/32 DRAM EDAC 48D32DRP EDAC EDAC-CORE MD(31:0)

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8/16/32 DRAM EDAC 48D32DRP EDAC EDAC-CORE MD(31:0)

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SPACE PRODUCTS
8/16/32 DRAM EDAC
48D32DRP
EDAC
EDAC-CORE
MD(31:0)
D(31:0) ND(31:0) CB(7:0) DBERR Checkbit Generator
CD(31:0)
MC(7:0)
CB(7:0)
D(31:0)
LDQP
RAD-PAK®
CS/RD/WR
Memory
I/OA(3:0)
EDAC CONTROL LOGIC
I/O(7:0)
ERROR COUNTER
DBERR
FEATURES:
Operates EDAC single event latchup MeV/mg/cm2 Single event upset upsets/day Total dose hardness100 krad (Si) typical Package: RAD-PAK® quad flat pack Weight: grams Cascadable EDAC Flow-thru architecture Super-high speed Single double error detection Single error counter Single auto-correct Double error counter Read-Modify-Write required Absolute minimum gate usage
DESCRIPTION:
Space Electronics' 48D32DRP high speed CMOS DRAM EDAC (Error Dectection Correction) features minimum kilorad (Si) total dose tolerance. 48D32DRP does require Read-Modify-Write memory partial word writes, thus used EDAC. These partial-word writes done single cycle without performance penalties. 48D32DRP incorporates four separate byte-wide EDAC modules parallel. Each module broken down into main blocks -the check generator (CBG) read/correct data (CORR). unique flow-thru architecture achieves 25ns from data (MD) corrected data (CD). readable error counters allow single-bit error (ERR) double-bit error (DBERR) tracking. Error signals internally masked mask bits. Capable surviving space environments, DRAM EDAC ideal satellite, spacecraft, space probe missions. RAD-PAK® technology incorporates radiation shielding microcircuit package. eliminates shielding while providing lifetime orbit. DRAM EDAC available with packaging screening Class
0503.99Rev0
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(619) 452-4167 Fax: (619) 452-5499 www.spaceelectronics.com
©1999 Space Electronics Inc. rights reserved.
48D32DRP
TABLE 48D32DRP DESCRIPTION
NAME Memory Data Memory CheckBit SYMBOL MD0-7, MD8-15, MD16-23, MD24-31 MC0-7, MC8-15, MC16-23, MC24-31 FUNCTION
8/16/32 DRAM EDAC
These pines accept data word from main memory error detection and/or correction. memory checkbits bits pins accept checkbits from checkbit memory error detection and/or correction. They also output corrected checkbits checkbit memory when 48D32DRP used bi-directional configuation. Data from MD0-31 appears these pins corrected when memory read mode. Partial-writes done without read-modify-writes. Allows read select four SRAM modules when performing data writes memory. Allows write select four SRAM modules when performing data writes memory. Selects internal registers read. Selects internal registers write. Selects memory modules read write modules. System clock 48D32DRP. Internal error counter clock. Global reset. Clears 48D32DRP EDAC cores zeros. Internal register address bus. Internal register data bus. Indicates double error occurred.
Data Memory Read Memory Write Read Write SRAM Chip Select Clock Clock Reset Address Error Counter Double Error
CD0-7, CD8-15, CD16-23, CD24-31 MEM_RD0-3 MEM_WR0-3 IO_RD IO_WR SRAM_CS0-3 CLKIN_A CLKIN_B RESET IO_A0-2 IO_OUT0-7 DBERR
Memory
TABLE 48D32DRP ABSOLUTE MAXIMUM RATINGS1
PARAMETER Voltage Supply Input Voltage Output Voltage Source/Sink Current Storage Temperature SYMBOL TSTG -0.5 -0.5 -0.5 +7.0 +150 UNITS
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Device should operated outside Recommended Operationg Condition. Device inputs normally high impedance draw extremely current. However, when input voltage greater than less than -0.5V, internal protection diode will forward-biased draw excessive current.
0503.99Rev0
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©1999 Space Electronics Inc. rights reserved.
48D32DRP
PARAMETER Temperature Range Power Supply Tolerance Case temperature (TC) used.
8/16/32 DRAM EDAC
TABLE 48D32DRP RECOMMENDED OPERATING CONDITIONS
+125 UNITS
%VCC
TABLE 48D32DRP ELECTRICAL SPECIFICATIONS
SYMBOL VOH1 Input Transition CIO, Capacitance2 IIH, IOZL, IOZH Standby3 Active3,4 GND, 5.5V VOUT GND, 5.5V
TEST CONDITIONS
GROUP SUBGROUPS 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3
LIMIT -2.2 -0.3 -MAX -+0.4 +0.8 +500
UNITS
Memory
Only output tested time. min. tested, information only. outputs unloaded. inputs GND. MHz.
TABLE 48D32DRP ELECTRICAL CHARACTERISTICS
PROPICATION DELAY FROM INPUT DATA Data OUTPUT SINGLE ERROR DBERR SINGLE ERROR UNIT
TABLE 48D32DRP ASSIGNMENT
0503.99Rev0
SIGNAL
SIGNAL
SIGNAL
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©1999 Space Electronics Inc. rights reserved.
48D32DRP
TABLE 48D32DRP ASSIGNMENT
0503.99Rev0
8/16/32 DRAM EDAC
SIGNAL -MD0 MEM_RD0 MEM_RD1 MD10 MD11 MD12 MD13 MD14 MD15 MEM_RD2 MEM_RD3 MD16 MD17 MD18 MD19 MD20 MD21 MD22 SIGNAL MC10 MC11 MC12 MC13 MC14 MC15 MC16 MC17 MC18 MC19 MC20 MC21 I)_RD IO_WR MC22 MC23 MC24 MC25 MC26 -MC27 MC28 MC29 MC30 MC31 IO_OUT_D0 IO_OUT_D1 IO_OUT_D2 IO_OUT_D3 SIGNAL CD10 CD11 CD12 -CD13
Memory
(SDI)* CD14 CD15 SRAM_CS0 SRAM_CS1 SRAM_CS2 SRAM_CS3 CD16 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CLKIN CD25 SPARE4
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
48D32DRP
TABLE 48D32DRP ASSIGNMENT
SIGNAL MD23 MD24 MD25 MD26 MD27 MD28 -MD29 MD30 MD31 MEM_WR0 MEM_WR1 MEM_WR2 MEM_WR3 SIGNAL IO_OUT_D4 IO_OUT_D5 IO_OUT_D6 IO_OUT_D7 IO_A0 IO_A1 IO_A2 CS_IO DBERR RESET
8/16/32 DRAM EDAC
SIGNAL CD26 CD27 CD28 CD29 CD30 CD31
Memory
0503.99Rev0
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©1999 Space Electronics Inc. rights reserved.
48D32DRP
Estimated Power 49D32DRP SRAM EDAC
8/16/32 DRAM EDAC
Power
er/Frequency
Memory
itching Frequency (MHz)
0503.99Rev0
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©1999 Space Electronics Inc. rights reserved.
48D32DRP
8/16/32 DRAM EDAC
Memory
RAD-PAK® QUAD FLAT PACKAGE
SYMBOL Q172-01 Note: dimensions inches
0503.99Rev0
DIMENSION 0.133 0.008 0.006 1.150 1.050 0.025 0.013 0.890 0.881 2.500 2.485 1.690 0.079 0.046 0.895 0.890 2.520 2.500 1.700 0.091 -0.900 0.899 2.540 2.505 1.710 0.103 0.146 0.013 0.009 1.162
0.116 0.007 0.004 1.138
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
48D32DRP
Important Notice:
8/16/32 DRAM EDAC
These data sheets created using chip manufacturers published specifications. Space Electronics verifies functionality testing parameters either 100% testing, sample testing characterization. specifications presented within these data sheets represent latest most accurate information available date. However, these specifications subject change without notice Space Electronics assumes responsibility this information. Space Electronics' products authorized critical components life support devices systems without express written approval from Space Electronics. claim against Space Electronics Inc. must made within days from date shipment from Space Electronics. Space Electronics' liability shall limited replacement defective parts.
Memory
0503.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.

8/16/32 DRAM EDAC 48D32DRP EDAC EDAC-CORE MD(31:0)

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