PEEL18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Lo

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PEEL18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Lo

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Commercial/ Industrial
PEEL18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device
Multiple Speed Power, Temperature Options Volts ±10% Speeds ranging from Power 37mA 25MHz Commercial industrial versions available CMOS Electrically Erasable Technology Superior factory testing Reprogrammable plastic package Reduces retrofit development costs Development Programmer Support Third party software programmers PLACE Development Software PDS-3 programmer PLD-to-PEELJEDEC file translator
Architectural Flexibility Enhanced architecture fits more logic product terms input array inputs pins possible macrocell configurations Asynchronous clear Independent output enables DIP/SOIC/TSSOP PLCC Application Versatility Replaces random logic Super sets PLDs (PAL, GAL, EPLD) Enhanced Architecture fits more logic than ordinary
General Description
PEELTM18CV8 Programmable Electrically Erasable Logic (PEELTM) device providing attractive alternative ordinary PLDs. PEELTM18CV8 offers performance, flexibility, ease design production practicality needed logic designers today. PEELTM18CV8 available 20-pin PLCC, SOIC TSSOP packages with speeds ranging from 25ns with power consumption 37mA. EE-Reprogrammability provides convenience instant reprogramming development reusable production inventory minimizing impact programming changes errors. EE-Reprogrammability also improves factory testability, thus assuring highest quality possible. PEELTM18CV8 architecture allows replace over standard 20-pin PLDs (PAL, GAL, EPLD etc.). also provides additional architecture features more logic into every design. ICT's JEDEC file translator instantly converts PEELTM18CV8 existing 20-pin PLDs without need rework existing design. Development programming support PEELTM18CV8 provided popular third-party programmers development software. also offers free PLACE development software low-cost development system (PDS-3).
Figure Configuration
I/CLK
Figure Block Diagram
TSSOP
PLCC
SOIC
PEEL18CV8
Figure PEELTM18CV8 Logic Array Diagram
PEEL18CV8
Function Description
PEELTM18CV8 implements logic functions sum-ofproducts expressions programmable-AND/fixed-OR logic array. User-defined functions created programming connections input signals into array. Userconfigurable output structures form macrocells further increase logic flexibility. array. (Note that PEELdevice programmers automatically program connections unused product terms that they will have effect output function).
Programmable Macrocell
unique twelve-configuration output macrocell provides complete control over architecture each output. ability configure each output independently permits users tailor configuration PEELTM18CV8 precise requirements their designs.
Architecture Overview
PEELTM18CV8 architecture illustrated block diagram Figure dedicated inputs I/Os provide inputs outputs creation logic functions. core device programmable electrically-erasable array which drives fixed array. With this structure, PEELTM18CV8 implement sum-of-products logic expressions. Associated with each functions macrocell which independently programmed different configurations. programmable macrocells allow each create sequential combinatorial logic functions active-high active-low polarity, while providing three different feedback paths into array.
Macrocell Architecture
Each macrocell, shown Figure consists Dtype flip-flop signal-select multiplexers. configuration each macrocell determined four EEPROM bits controlling these multiplexers. These bits determine output polarity, output type (registered nonregistered) input-feedback path (bidirectional I/O, combinatorial feedback). Refer Table details. Equivalent circuits twelve macrocell configurations illustrated Figure addition emulating four PAL-type output structures (configurations 3,4,9, 10), macrocell provides eight additional configurations. When creating PEELdevice design, desired macrocell configuration generally specified explicitly design file. When design assembled compiled, macrocell configuration bits defined last lines JEDEC programming file.
AND/OR LOGIC ARRAY
programmable array PEELTM18CV8 (shown Figure formed input lines intersecting product terms. input lines product terms used follows:
Input Lines: input lines carry true complement signals applied input pins additional lines carry true complement values feedback input signals from I/Os product terms: product terms (arranged groups used form product functions output enable terms (one each I/O) global synchronous preset term global asynchronous clear term
Output Type
signal from array directly output (combinatorial function) latched D-type flipflop (registered function). D-type flip-flop latches data rising edge clock controlled global preset clear terms. When synchronous preset term satisfied, output register will HIGH next rising edge clock input. Satisfying asynchronous clear will LOW, regardless clock state. both terms satisfied simultaneously, clear will override preset.
each input-line/product-term intersection, there EEPROM memory cell that determines whether there logical connection that intersection. Each product term essentially 36-input gate. product term that connected both true complement input signal will always FALSE thus will affect function that drives. When connections product term opened, "don't care" state exists that term will always TRUE. When programming PEELTM18CV8, device programmer first performs bulk erase remove previous pattern. erase cycle opens every logical connection array. device configured perform userdefined function programming selected connections
Output Polarity
Each macrocell configured implement active-high active-low logic. Programmable polarity eliminates need external inverters.
Output Enable
output each macrocell enabled disabled under control associated programmable output enable product term. When logical conditions programmed output enable term satisfied, output signal propagated pin. Otherwise, output buffer switched into high-impedance state.
PEEL18CV8
Under control output enable term, function dedicated input, dedicated output, bidirectional I/O. Opening every connection output enable term will permanently enable output buffer yield dedicated output. Conversely, every connection intact, enable term will always logically false will function dedicated input.
Registered Feedback
Feedback also taken from register, regardless whether output function combinatorial registered. When implementing combinatorial output function, registered feedback allows internal latching states without giving external output.
Input/Feedback Select
PEELTM18CV8 macrocell also provides control over feedback path. input/feedback signal associated with each macrocell obtained from three different locations; from input pin, from output flip-flop (registered feedback), directly from gate (combinatorial feedback).
Design Security
PEELTM18CV8 provides special EEPROM security that prevents unauthorized reading copying designs programmed into device. security programmer, either conclusion programming cycle separate step, after device been programmed. Once security impossible verify (read) program PEELuntil entire device first been erased with bulk-erase function.
Bi-directional
input/feedback signal taken from when using dedicated input bi-directional I/O. (Note that possible create registered output function with bi-directional I/O.)
Programming Support
ICT's JEDEC file translator allows easy conversion existing designs PEELTM18CV8, without need redesign. supports broad range popular third party design entry systems, including Data Synario Abel, Logical Devices CUPL others. also offers (for free) proprietary PLACE software, easy-to-use entry level PC-based software development system. Programming support includes popular third party programmers; Data I/O, Logical Devices, numerous others. also provides cost development programmer system, PDS-3.
Combinatorial Feedback
signal-select multiplexer gives macrocell ability feedback output gate, bypassing output buffer, regardless whether output function registered combinatorial. This feature allows creation asynchronous latches, even when output must disabled. (Refer configurations 5,6,7 Figure
Figure Block Diagram PEELTM18CV8
PEEL18CV8
Figure Equivalent Circuits Twelve Configurations PEELTM18CV8 Macrocell
Configuration
Input/Feedback Select
Register Bi-directional
Output Select
Active Active High Active Active High Active Active High Active Active High Active Active High Active Active High
Combinatorial Register Combinatorial Feedback Combinatorial Register Register Feedback Combinatorial
PEEL18CV8
This device been designed tested specified operating ranges. Proper operation outside these levels guaranteed. Exposure absolute maximum ratings cause permanent damage.
Absolute Maximum Ratings Symbol
Parameter
Supply Voltage Voltage Applied Output Current Storage Temperature Lead Temperature
ConditionRelative Ground Relative Ground (IOL, IOH)
Rating
-0.5 -0.5 +150
Unit
Soldering Second
+300
Operating Range Symbol
TRVCC
Parameter
Supply Voltage Commercial Industrial Commercial Industrial Note Note Note
Condition
4.75
5.25
Unit
Ambient Temperature Clock Rise Time Clock Fall TIme Rise Time
D.C. Electrical Characteristics Over operating range (Unless otherwise specified) Symbol
VOHC VOLC ISC9
Parameter
Output HIGH Voltage Output HIGH Voltage CMOS12
ConditionVCC Min, -4.0 Min, Min, 16mA/24mA Min,
Unit
Output Voltage Output Voltage CMOS12 Input HIGH level Input Voltage Input, Leakage Current Input pull-ups disabled Input, Leakage Current Input pull-ups enabled Input, Leakage Current HIGH Output Short Circuit Current
0.15 -0.3 -100 (Typical) -135 90/100 45/55 37/50
Max, GND, High Max, GND, High Max, VCC, High 0.5V, 25°C
ICC10
Current, f=25MHz
VCC, Outputs disabled4
-10/I-10 -15/I-15 -25/I-25
Input Capacitance Output Capacitance
COUT7
25°C, 5.0V
PEEL18CV8
A.C. Electrical CharacteristicOver operating range
Symbol
tCO1 tCO2
tCL, fMAX1 fMAX2 fMAX3 tRESET Input5 Input5
Parameter
Input5 non-registered output output output enable6 disable6
-10/I-10 -15/I-15 -25/I-25 Units
117.6 83.3 142.8 83.3 41.6 28.5 28.5 33.3
Clock Output Clock comb. output delay internal registered feedback Clock Feedback Input5 feedback setup clock Input5 hold after clock Clock time, clock high time8
166.7 166.7
clock period (tSC tCO1) Internal feedback (1/tSC+tCF)11
External Feedback (1/tCP)11 Feedback (1/tCL+tCH)11 Asynchronous Reset Pulse Width Input Asynchronous Reset Asynchronous Reset recovery time Power-on reset time registers clear state
Switching WaveformInputs, I/O, Registered Feedback, Synchronous Preset Clock Asynchronous Reset Registered Outputs Combinatorial OutputNotes:
Minimum input -0.5V, however, inputs undershoot -2.0V periods less than specified program/verify operation. Test Points Clock referenced levels. pins VCC. "Input" refers input signal. measured from input transition VREF±0.1V, measured from input transition VOH-0.1V VOL+0.1V; VREF=VL. Capacitances tested sample basis. Test conditions assume: signal transition times less from points, timing reference levels 1.5V (Unless otherwise specified). Test output time duration less than second. typical application: This parameter tested with device programmed 8-bit Counter. Parameters 100% tested. Specifications based initial characterization tested after design process modification that might affect operational frequency. Available only 18CV8 -15/I-15/-25/I-25 grades 24mA available 18CV8-5/-7. other speeds 16mA.
PEEL18CV8
PEELDevice Array Test LoadStandard Load Thevenin Equivalent
Output Output
Technology
CMOS12 -10/-15/-25 -5/-7
480k
480k
228k
2.375V 2.02V 2.129V
Ordering Information Part Number
PEEL18CV8J-5 PEEL18CV8P-7 PEEL18CV8J-7 PEEL18CV8S-7 PEEL18CV8P-10 PEEL18CV8PI-10 PEEL18CV8J-10 PEEL18CV8JI-10 PEEL18CV8S-10 PEEL18CV8SI-10 PEEL18CV8T-10 PEEL18CV8TI-10 PEEL18CV8P-15 PEEL18CV8PI-15 PEEL18CV8J-15 PEEL18CV8JI-15 PEEL18CV8S-15 PEEL18CV8SI-15 PEEL18CV8T-15 PEEL18CV8TI-15 PEEL18CV8P-25 PEEL18CV8PI-25 PEEL18CV8J-25 PEEL18CV8JI-25 PEEL18CV8S-25 PEEL18CV8SI-25 PEEL18CV8T-25 PEEL18CV8TI-25
Speed
Temperature
Commercial Commercial Commercial Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Package
20-pin Plastic Leaded Chip Carrier (PLCC) 20-pin Plastic 20-pin Plastic Leaded Chip Carrier (PLCC) 20-pin SOIC 20-pin Plastic 20-pin Plastic Leaded Chip Carrier (PLCC) 20-pin SOIC 20-pin TSSOP 20-pin Plastic 20-pin Plastic Leaded Chip Carrier (PLCC) 20-pin SOIC 20-pin TSSOP 20-pin Plastic 20-pin Plastic Leaded Chip Carrier (PLCC) 20-pin SOIC 20-pin TSSOP
PEEL18CV8
Part Number
Device Suffix PEELTM18CV8 PI-25 Speed 7.5ns 10ns 15ns 25ns Temperature Range (Blank) Commercial +70°C Industrial
Package 20-pin Plastic 300mil 20-pin Plastic Leaded Chip Carrier (PLCC) 20-pin SOIC Gullwing 20-pin TSSOP
PEEL18CV8

PEEL18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Lo

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