38MHz-320MHz Phase Noise VCXO Less than 0.4ps (12KHz-20MHz) phase

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38MHz-320MHz Phase Noise VCXO Less than 0.4ps (12KHz-20MHz) phase

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PL580-37/38/39
38MHz-320MHz Phase Noise VCXO
Less than 0.4ps (12KHz-20MHz) phase jitter frequencies Less than 25ps (typ.) peak peak jitter frequencies. phase noise output 1MHz frequency offset -144dBc/Hz 155.52MHz -140dBC/Hz 311.04MHz 19MHz-40MHz crystal input. 38MHz-320MHz output. Available PECL, LVDS, CMOS outputs. external varicap required. Output Enable selector. Wide pull range (+/-200ppm). 3.3V operation. Available 16-pin TSSOP packages.
PACKAGE ASSIGNMENT
VDDANA XOUT SEL2^ OE_CTRL VCON GNDANA SEL0^ SEL1^ GNDBUF QBAR VDDBUF GNDBUF
PL580-3X
16-pin TSSOP
VDDANA SEL0^
XOUT
SEL1^
GNDBUF QBAR VDDBUF
DESCRIPTION
PL580-3X monolithic jitter phase noise VCXO, capable 0.4ps phase jitter CMOS, LVDS, PECL outputs, covering wide frequency output range 320MHz. allows control output frequency with input voltage (VCON), using cost crystal. frequency selector pads PL580-3X enable output frequencies PL580-3X designed address demanding requirements high performance applications such SONET, GPS, Video, etc.
SEL2^ OE_CTRL VCON
PL580-3X
GNDANA
Note1: QBAR used single ended CMOS output. Note2: Denotes internal pull resistor.
BLOCK DIAGRAM
VCON
VARICAP
Divider Charge Pump Loop Filter Output Divider (1,2,4,8)
GNDBUF
XOUT
XTAL
Phase Detector
x16)
QBAR
Performance Tuner
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 09/29/05 Page
PL580-37/38/39
38MHz-320MHz Phase Noise VCXO
OUTPUT ENABLE LOGICAL LEVELS
Part
PLL580-38 (PECL) PLL580-37 (CMOS LVDS)
(Default) (Default)
State
Output enabled Tri-state Tri-state Output enabled
DESCRIPTIONS
Name
VDDANA XOUT SEL2 OE_CTRL VCON GNDANA GNDBUF VDDBUF QBAR GNDBUF SEL1 SEL0
TSSOP number
3x3mm number
Type
analog Circuitry.
Description
Crystal input pin. (See Crystal Specifications page Crystal output pin. (See Crystal Specifications page Output frequency Selector pin. Output enable control pin. (See OE_CTRL Logic Levels). Voltage control input. Ground analog circuitry. Tuning inductor connection. inductor recommended high small size 0402 0603 component, must placed between adjacent pin. Place inductor close possible minimize parasitic effects maintain inductor connection output buffer circuitry. PECL LVDS output. connection output buffer circuitry. VDDBUF should separately decoupled from other VDDs whenever possible. Complementary PECL, LVDS, single ended CMOS output. connection output buffer circuitry. Output frequency Selector pin. Output frequency Selector pin.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 09/29/05 Page
PL580-37/38/39
38MHz-320MHz Phase Noise VCXO
FREQUENCY SELECTION TABLE
SEL2
SEL1
SEL0
Selected Multiplier/Output Frequency
Max* Min* Reserved Reserved
pads have internal pull-ups (default value `1'). Bond Special Test Modes help selecting inductor value target output frequency.
PERFORMANCE TUNING INDUCTOR VALUE SELECTION
Please refer PhaseLink's `PhasorV Tuning Assistance' software automatically calculate optimum inductor values your application. addition, chart below could used reference quick inductor value selection. Please note that inductor values mentioned table below, when using `PhasorV Tuning Assistance' derived based parasitic values PhaseLink's evaluation board. performance enhancement your custom board design, please follow following instruction: special test modes "VCO Max" "VCO Min" determine optimum inductor value. "VCO Max" represents high range "VCO Min" represents range. output frequency "VCO Max" "VCO Min" test modes VCO/16. This means that output frequencies around crystal frequency that will used. optimum inductor value where target crystal frequency closest middle between "VCO Max" "VCO Min" output frequencies. this case will lock middle tuning range with maximum margin either side.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 09/29/05 Page
PL580-37/38/39
38MHz-320MHz Phase Noise VCXO
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) Protection, Human Body Model
SYMBOL
MIN.
-0.5 -0.5
MAX.
+0.5 +0.5
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied. Note: Operating Temperature guaranteed design parts (COMMERCIAL INDUSTRIAL), tested COMMERCIAL grade only.
Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Crystal Pullability Recommended
SYMBOL
(xtal) (xtal)
CONDITIONS
Parallel Fundamental Mode VCON VCON 1.65V VCON 3.3V
MIN.
TYP.
17.7
MAX.
UNITS
Note: Crystal Loading rating: listed numbers only. Specify crystal value VCON 1.65V package parasitic. round number (i.e. 12pF) achieved adding external capacitors. same value XOUT, please note, that frequency pulling oscillator gain decrease.
Voltage Control Crystal Oscillator PARAMETERS
VCXO Stabilization Time VCXO Tuning Range output pullability VCXO Tuning Characteristic Pull range linearity VCON input impedance VCON modulation
SYMBOL
VCXOSTB
CONDITIONS
From power valid 40MHz; XTAL VCON 3.3V VCON=1.65V, ±1.65V
MIN.
TYP.
MAX.
UNITS
ppm/V
±200
VCON 3.3V, -3dB
Note: Parameters denoted with asterisk represent nominal characterization data production tested specific limits.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 09/29/05 Page
PL580-37/38/39
38MHz-320MHz Phase Noise VCXO
General Electrical Specifications PARAMETERS
Supply Current, Dynamic (with Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current
Note: CMOS operation advised above 200MHz with 15pF load; 320MHz with 10pF load.
SYMBOL
CONDITIONS
PECL/LVDS/CMOS 38MHz<Fout<100MHz 100MHz<Fout<320MHz
MIN.
TYP.
MAX.
65/45/30 80/60/40
UNITS
(CMOS) 1.25V (LVDS) 1.3V (PECL)
2.97
3.63
Jitter Specifications PARAMETERS
Integrated jitter
CONDITIONS
Integrated With capacitive decoupling between GND. Over 10,000 cycles. With capacitive decoupling between GND. Over 10,000 cycles.
FREQUENCY
155.52MHz 311.04MHz 77.76MHz 155.52MHz 311.04MHz 77.76MHz 155.52MHz 311.04MHz
MIN.
TYP.
MAX.
UNITS
Period jitter
Period jitter Peak-toPeak
Phase Noise Specifications PARAMETERS
Phase Noise relative carrier (typical)
FREQ.
77.76MHz 155.52MHz 311.04MHz
@10Hz
@100Hz
@1kHz -124 -120 -116
@10kHz -134 -132 -129
@100kHz -132 -128 -124
-145 -144 -140
@10M -149 -150 -148
UNITS
dBc/Hz
Note: Phase Noise measured VCON
CMOS Electrical Characteristics PARAMETERS
Output drive current Output Clock Rise/Fall Time Output Clock Rise/Fall Time
SYMBOL
CONDITIONS
-0.4V, =3.3V 0.4V, 3.3V 0.3V 3.0V with load 20%-80% with Load
MIN.
TYP.
MAX.
UNITS
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 09/29/05 Page
PL580-37/38/39
38MHz-320MHz Phase Noise VCXO
LVDS Electrical Characteristics PARAMETERS
Output Differential Voltage Magnitude Change Output High Voltage Output Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
(see figure)
1.125 -5.7
1.375
LVDS Switching Characteristics PARAMETERS
Differential Clock Rise Time Differential Clock Fall Time
LVDS Levels Test Circuit
SYMBOL
CONDITIONS
(see figure)
MIN.
TYP.
MAX.
UNITS
LVDS Switching Test Circuit
10pF
VDIFF
10pF
LVDS Transistion Time Waveform
(Differential)
VDIFF
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 09/29/05 Page
PL580-37/38/39
38MHz-320MHz Phase Noise VCXO
PECL Electrical Characteristics PARAMETERS
Output High Voltage Output Voltage
SYMBOL
CONDITIONS
(see figure)
MIN.
1.025
MAX.
1.620
UNITS
PECL Switching Characteristics PARAMETERS
Clock Rise Fall Times Clock Rise Fall Times
SYMBOL
FREQ.
<150MHz >150MHz <320MHz
CONDITIONS
@20/80% PECL @80/20% PECL
MIN.
TYP.
MAX.
UNITS
0.55
PECL Levels Test Circuit
PECL Output Skew
2.0V
tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 09/29/05 Page
PL580-37/38/39
38MHz-320MHz Phase Noise VCXO
LAYOUT RECOMMENDATIONS
LAYOUT CONSIDERATIONS PERFORMANCE OPTIMIZATION
following guidelines assist with performance optimized design: Keep traces PL580 short possible, well keeping other traces away from possible. Place crystal close possible both crystal pins device. This will reduce cross-talk between crystal other signals. Separate crystal traces from other signals PCB, allow ample distance between crystal traces. Place 0.01µF~0.1µF decoupling capacitor between GND, component side PCB, close pin. recommended place this component backside PCB. Going through vias will reduce signal integrity, causing additional jitter phase noise. highly recommended keep traces short possible. When connecting long traces inch) CMOS output, important design traces transmission line `stripline', avoid reflections ringing. this case, CMOS output needs matched trace impedance. Usually `striplines' designed impedance CMOS outputs usually have lower than impedance matching achieved adding resistor series with CMOS output `stripline' trace. Please contact PhaseLink application note design outputs driving long traces Gerber files PL580 layout.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 09/29/05 Page
PL580-37/38/39
38MHz-320MHz Phase Noise VCXO
PACKAGE INFORMATION 16-PIN SSOP
TSSOP
Symbol Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 0.45 0.75 0.65
16-PIN
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 09/29/05 Page
PL580-37/38/39
38MHz-320MHz Phase Noise VCXO
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PL580-3X
PART NUMBER TAPE REEL NONE= TUBE GREEN PACKAGE NONE= REGULAR PACKAGE PACKAGE TYPE O=TSSOP TEMPERATURE C=COMMERCIAL I=INDUSTRAL
Order Number
PL580-37OC PL580-37OC-R PL580-37OCL PL580-37OCL-R PL580-37QC PL580-37QC-R PL580-37QCL PL580-37QCL-R PL580-38OC PL580-38OC-R PL580-38OCL PL580-38OCL-R PL580-38QC PL580-38QC-R PL580-38QCL PL580-38QCL-R PL580-39OC PL580-39OC-R PL580-39OCL PL580-39OCL-R PL580-39QC PL580-39QC-R PL580-39QCL PL580-39QCL-R
Marking
P580-37OC P580-37OC P580-37OCL P580-37OCL P580-37QC P580-37QC P580-37QCL P580-37QCL P580-38OC P580-38OC P580-38OCL P580-38OCL P580-38QC P580-38QC P580-38QCL P580-38QCL P580-39OC P580-39OC P580-39OCL P580-39OCL P580-39QC P580-39QC P580-39QCL P580-39QCL
Package Option
TSSOP Tube TSSOP Tape Reel TSSOP Tube (GREEN Package) TSSOP Tape Reel (GREEN Package) Tube Tape Reel Tube (GREEN Package) Tape Reel (GREEN Package) TSSOP Tube TSSOP Tape Reel TSSOP Tube (GREEN Package) TSSOP Tape Reel (GREEN Package) Tube Tape Reel Tube (GREEN Package) Tape Reel (GREEN Package) TSSOP Tube TSSOP Tape Reel TSSOP Tube (GREEN Package) TSSOP Tape Reel (GREEN Package) Tube Tape Reel Tube (GREEN Package) Tape Reel (GREEN Package)
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 09/29/05 Page

38MHz-320MHz Phase Noise VCXO Less than 0.4ps (12KHz-20MHz) phase

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