Power CMOS Output VCXO Family (17MHz 130MHz) VCXO output 17MHz 13

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Power CMOS Output VCXO Family (17MHz 130MHz) VCXO output 17MHz 13

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PLL500-17B/27B/37B
Power CMOS Output VCXO Family (17MHz 130MHz)
VCXO output 17MHz 130MHz range PLL500-17B: 17MHz 36MHz PLL500-27B: 27MHz 65MHz PLL500-37B: 65MHz 130MHz phase noise (-142 10kHz offset). CMOS output with tri-state control. Selectable output drive (Standard High drive). Standard: drive capability level. High: 24mA drive capability level. Fundamental crystal input. Integrated high linearity variable capacitors. pull range, linearity. jitter (RMS): 2.5ps period jitter. 3.3V operation. Available 8-Pin SOIC DIE.
CONFIGURATION
XOUT VDD*
P500-x7B
Denotes internal Pull-up
LAYOUT
(812,986)
XOUT DRIVSEL^
DESCRIPTION
PLL500-17B/27B/37B cost, high performance, phase noise, high linearity VCXO family 130MHz range, providing less than -130dBc 10kHz offset. very jitter (2.5 period jitter) makes these chips ideal applications requiring voltage controlled frequency sources. IC's designed accept fundamental resonant mode crystals.
VCON
ID:PLL500-17B: C500A0505-05P
PLL500-27B: C500A0505-05Q PLL500-37B: C500A0505-05R
(0,0)
Note: denotes internal pull
FREQUENCY RANGE
PART PLL500-17B PLL500-27B PLL500-37B MULTIPLIER FREQUENCY
SPECIFICATIONS
Name Value
Size Reverse side dimensions Thickness
micron micron
BLOCK DIAGRAM
XOUT XTAL VARICAP
VCON
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 12/21/05 Page
PLL500-17B/27B/37B
Power CMOS Output VCXO Family (17MHz 130MHz)
DESCRIPTION
Name
VCON DRIVSEL XOUT
Pin#
Position (µm)
94.183 94.157 94.183 94.193 715.472 715.307 715.472 476.906
(µm)
768.599 605.029 331.756 140.379 203.866 455.726 626.716 888.881
Type
Description
Crystal input pin. Output Enable input pin. Disables output when low. Internal pull-up enables output default connected low. Frequency control voltage input pin. Ground pin. Output clock pin. power supply pin. Output drive select pin. High drive `0'. drive `1'. Internal pull-up. Crystal output pin. clock input.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) Protection, Human Body Model
SYMBOL
MIN.
-0.5 -0.5
MAX.
+0.5 +0.5
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied. Note: Operating Temperature guaranteed design parts (COMMERCIAL INDUSTRIAL), tested COMMERCIAL grade only.
Electrical Specifications PARAMETERS
Input Crystal Frequency
SYMBOL
CONDITIONS
PLL500-17B PLL500-27B PLL500-47B 0.8V 2.0V with load 0.3V 3.0V with load Measured 1.4V
MIN.
TYP.
MAX.
UNITS
Output Clock Rise/Fall Time Output Clock Duty Cycle Short Circuit Current
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 12/21/05 Page
PLL500-17B/27B/37B
Power CMOS Output VCXO Family (17MHz 130MHz)
Voltage Control Crystal Oscillator PARAMETERS
VCXO Stabilization Time VCXO Tuning Range output pullability VCXO Tuning Characteristic Pull range linearity Power Supply Rejection VCON input impedance VCON modulation PWSRR
SYMBOL
VCXOSTB
CONDITIONS
From power valid 25MHz; XTAL VCON 3.3V VCON=1.65V, ±1.65V
MIN.
TYP.
MAX.
UNITS
ppm/V
±150
Frequency change with varied VCON 3.3V, -3dB
2000
Note: Preliminary Specifications still characterized. Parameters denoted with asterisk represent nominal characterization data production tested specific limits.
Jitter Phase Noise Specifications PARAMETERS
Period Jitter sigma 10,000 samples) Phase Noise relative carrier Phase Noise relative carrier Phase Noise relative carrier Phase Noise relative carrier Phase Noise relative carrier
CONDITIONS
With capacitive decoupling between GND. @100Hz offset @1kHz offset @10kHz offset @100kHz offset @1MHz offset
MIN.
TYP.
-100 -125 -142 -150 -150
MAX.
UNITS
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 12/21/05 Page
PLL500-17B/27B/37B
Power CMOS Output VCXO Family (17MHz 130MHz)
Specifications PARAMETERS
Supply Current, Dynamic, with Loaded Outputs
SYMBOL
CONDITIONS
27MHz, 15pF output load 35MHz, 15pF output load 78MHz, 15pF output load PLL500-17B PLL500-27B PLL500-37B drive 100MHz PLL500-37B High drive -8mA -4mA Standard drive level High drive level
MIN.
TYP.
MAX.
UNITS
Allowable output load capacitance Operating Voltage Output High Voltage Output Voltage Output High Voltage CMOS level Output drive current Short Circuit Current VCXO Control Voltage
(Output)
2.25
3.63
VCON
Crystal Specifications PARAMETERS
Crystal Loading Rating (VCON 1.65V) Maximum Sustainable Drive Level Operating Drive Level PLL500-17B PLL500-27B PLL500-37B C0/C1
SYMBOL
(xtal)
MIN.
TYP.
MAX.
UNITS
Note: crystal must such that oscillates (parallel resonant) nominal frequency when presented Load specified above. crystal requires more load nominal frequency, additional load must added externally. This however reduce pull range.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 12/21/05 Page
PLL500-17B/27B/37B
Power CMOS Output VCXO Family (17MHz 130MHz)
PACKAGE INFORMATION
SOIC (Dimensions
Symbol Dimension Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PLL500-X7B
PART NUMBER NONE= TUBE R=TAPE REEL
NONE=NORMAL PACKAGE L=GREEN PACKAGE
PACKAGE TYPE S=SSOP
TEMPERATURE C=COMMERCIAL I=INDUSTRIAL
Order Number
PLL500-X7BDC PLL500-X7BSC PLL500-X7BSC-R PLL500-X7BSCL PLL500-X7BSCL-R
Marking
P500-X7BDC P500-X7BSC P500-X7BSC P500-X7BSCL P500-X7BSCL
Package Option
(Waffle Pack) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape Reel) 8-Pin SOIC (Tube), GREEN 8-Pin SOIC (Tape Reel) GREEN
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without press written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 12/21/05 Page

Power CMOS Output VCXO Family (17MHz 130MHz) VCXO output 17MHz 13

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