Rev. 3/2000 DSP56303 Advance Information 24-Bit General
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Order Number: DSP56303/D
Rev. 3/2000
DSP56303
Advance Information
24-Bit General-Purpose Digital Signal Processor
DSP56303 member DSP56300 core family programmable CMOS Digital Signal Processors (DSPs). This family uses high-performance, single clock cycle instruction engine providing twofold performance increase over Motorola's popular DSP56000 core family while retaining code compatibility. Significant architectural features DSP56300 core family include barrel shifter, 24-bit addressing, instruction cache, DMA. DSP56303 offers 66/80/100 MIPS using internal 66/80/100 clock 3.0-3.6 volts. DSP56300 core family offers rich instruction power dissipation, well increasing levels speed power, enabling wireless, telecommunications, multimedia products.
Triple Timer
Host Interface HI08
ESSI Interface
Interface
Program 4096 (default)
Data Data 2048 2048 (default) (default)
Memory Expansion Area
PIO_EB
PM_EB
XM_EB
Address Generation Unit Six-Channel Unit
YM_EB
Peripheral Expansion Area
External Address Switch External
Address
Bootstrap
24-Bit DSP56300 Core
Control
Interface
Cache
Control
Internal Data Switch
EXTAL
External Data Switch
Data
XTAL
Clock Generator
Power Mngmnt. Program Interrupt Controller Program Decode Controller MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Program Address Generator Data 56-bit 56-bit Accumulators 56-bit Barrel Shifter
JTAG OnCEDE
RESET
PINIT/NMI
Figure DSP56303 Block Diagram
This document contains information product. Specifications information herein subject change without notice. Motorola, Inc., 2000
CONTENTS
SECTION SECTION SECTION SECTION SECTION APPENDIX SIGNAL/CONNECTION DESCRIPTIONS SPECIFICATIONS: UDR2 TECHNOLOGY MASKS 2A-1 SPECIFICATIONS: CDR2 TECHNOLOGY MASKS 2B-1 PACKAGING DESIGN CONSIDERATIONS POWER CONSUMPTION BENCHMARK
APPENDIX BOOTSTRAP PROGRAM: UDR2 TECHNOLOGY MASKS B1-1 APPENDIX BOOTSTRAP PROGRAM: CDR2 TECHNOLOGY MASKS B2-1 INDEX .Index-1
TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.mot.com/SPS/DSP
Data Sheet Conventions
This data sheet uses following conventions:
OVERBAR "asserted" "deasserted" Examples: Used indicate signal that active when pulled (For example, RESET active when low.) Means that high true (active high) signal high that true (active low) signal Means that high true (active high) signal that true (active low) signal high Signal/Symbol Logic State Signal State Voltage1
Note:
True False True False
Asserted Deasserted Asserted Deasserted
VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values VIL, VOL, VIH, defined individual product specifications.
DSP56303 Technical Data
Features
FEATURES High Performance DSP56300 Core
66/80/100 million instructions second (MIPS) with 66/80/100 clock 3.0-3.6 Object code compatible with DSP56000 core Highly parallel instruction Data Arithmetic Logic Unit (Data ALU) Fully pipelined 24-bit parallel Multiplier-Accumulator (MAC) 56-bit parallel barrel shifter (fast shift normalization; stream generation parsing) Conditional instructions 24-bit 16-bit arithmetic support under software control
Program Control Unit (PCU) Position Independent Code (PIC) support Addressing modes optimized applications (including immediate offsets) On-chip instruction cache controller On-chip memory-expandable hardware stack Nested hardware loops Fast auto-return interrupts
Direct Memory Access (DMA) channels supporting internal external accesses One-, two-, three- dimensional transfers (including circular buffering) End-of-block-transfer interrupts Triggering from interrupt lines peripherals
Phase Lock Loop (PLL) Allows change power Divide Factor (DF) without loss lock Output clock with skew elimination
Hardware debugging support On-Chip Emulation module Joint Action Test Group (JTAG) Test Access Port (TAP) Address Trace mode reflects internal Program accesses external port
DSP56303 Technical Data
Features
On-Chip Memories
Program RAM, Instruction Cache, data RAM, data size programmable:
Instruction Cache disabled enabled disabled enabled Switch Mode disabled disabled enabled enabled Program Size 4096 24-bit 3072 24-bit 2048 24-bit 1024 24-bit Instruction Cache Size 1024 24-bit 1024 24-bit Data Size 2048 24-bit 2048 24-bit 3072 24-bit 3072 24-bit Data Size 2048 24-bit 2048 24-bit 3072 24-bit 3072 24-bit
24-bit bootstrap
Off-Chip Memory Expansion
Data memory expansion 24-bit word memory spaces 24bit word memory spaces using Address Attribute AA0-AA3 signals) Program memory expansion 24-bit words memory space 24-bit word memory space using Address Attribute AA0-AA3 signals) External memory expansion port Chip Select Logic glueless interface SRAMs On-chip DRAM Controller glueless interface DRAMs
On-Chip Peripherals
Enhanced DSP56000-like 8-bit parallel Host Interface (HI08) supports variety buses (for example, ISA) provides glueless connection number industry-standard microcomputers, microprocessors, DSPs Enhanced Synchronous Serial Interfaces (ESSI), each with receiver three transmitters (allows six-channel home theater) Serial Communications Interface (SCI) with baud rate generator Triple timer module thirty-four programmable General-Purpose Input/Output (GPIO) pins, depending which peripherals enabled
DSP56303 Technical Data
Target Applications
Reduced Power Dissipation
Very power CMOS design Wait Stop power standby modes Fully static logic, operation frequency down (DC) Optimized power management circuitry (instruction-dependent, peripheral-dependent, mode-dependent)
TARGET APPLICATIONS
DSP56303 intended telecommunication applications, such multi-line voice/data/fax processing, video conferencing, audio applications, control, general digital signal processing
PRODUCT DOCUMENTATION
three documents listed following table required complete description DSP56303 necessary design properly with part. Documentation available from following sources (see back cover detailed information): local Motorola distributor Motorola semiconductor sales office Motorola Literature Distribution Center World Wide (WWW)
DSP56303 Documentation Name DSP56300 Family Manual DSP56303 User's Manual DSP56303 Technical Data Description Detailed description DSP56300 family processor core instruction Detailed functional description DSP56303 memory configuration, operation, register programming DSP56303 features list physical, electrical, timing, package specifications Order Number DSP56300FM/AD
DSP56303UM/AD
DSP56303/D
DSP56303 Technical Data
DSP56303 Technical Data
SECTION SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
DSP56303 input output signals organized into functional groups, shown Table illustrated Figure 1-1. DSP56303 operates from supply; however, some inputs tolerate special notice this feature added signal descriptions those inputs.
Table 1-1. DSP56303 Functional Signal Groupings
Functional Group Power (VCC) Ground (GND) Clock Address Data Control Interrupt Mode Control Host Interface (HI08) Enhanced Synchronous Serial Interface (ESSI) Serial Communication Interface (SCI) Timer JTAG/OnCE Port Notes:
Port
Number Signals Port
Detailed Description Table Table Table Table Table Table Table Table Table 1-11 Table 1-12 Table 1-13 Table 1-14 Table 1-15 Table 1-16
Ports Port
Port signals define external memory interface port, including external address bus, data bus, control signals. Port signals HI08 port signals multiplexed with GPIO signals. Port signals ESSI port signals multiplexed with GPIO signals. Port signals port signals multiplexed with GPIO signals.
DSP56303 Technical Data
Signal Groupings
DSP56303
VCCP VCCQ VCCA VCCD VCCC VCCH VCCS Power Inputs: Internal Logic Address Data Control HI08 ESSI/SCI/Timer Grounds: Internal Logic Address Data Control HI08 ESSI/SCI/Timer Interrupt/M Control
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET Non-Multiplexe H0-H7 HCS/HCS Single HDS/HDS Single HREQ/HREQ HACK/HACK Multiplexed HAD0-HAD7 HAS/HAS HA10 Double HRD/HRD HWR/HWR Double HTRQ/HTRQ HRRQ/HRRQ Port GPIO PC0-PC2 Port GPIO PD0-PD2 Port GPIO Timer GPIO TIO0 TIO1 TIO2 Port GPIO PB0-PB7 PB10 PB13 PB11 PB12 PB14 PB15
GNDP GNDP1 GNDQ GNDA GNDD GNDC GNDH GNDS
Host Interface (HI08) Port1
EXTAL XTAL CLKOUT PCAP PINIT/NMI
Clock
Enhanced Synchronous Serial Interface Port (ESSI0)2
SC00-SC02 SCK0 SRD0 STD0
Enhanced Synchronous Serial Interface Port (ESSI1)2
SC10-SC12 SCK1 SRD1 STD1
Port
A0-A17 D0-D23 AA0-AA3/ RAS0-RAS3 BCLK BCLK Note:
External Address External Data External Control
Serial Communications Interface (SCI) Port2
SCLK
Timers3
TIO0 TIO1 TIO2 TRST
JTAG/OnC Port
HI08 port supports non-multiplexed multiplexed bus, single double Data Strobe (DS), single double Host Request (HR) configurations. Since each these modes configured independently, combination these modes possible. These HI08 signals also configured GPIO signals (PB0-PB15). Signals with dual designations (for example, HAS/HAS) have configurable polarity. ESSI0, ESSI1, signals multiplexed with Port GPIO signals (PC0-PC5), Port GPIO signals (PD0-PD5), Port GPIO signals (PE0-PE2), respectively. TIO0-TIO2 configured GPIO signals.
Figure 1-1. Signals Identified Functional Group
DSP56303 Technical Data
Power
POWER
Table 1-2. Power Inputs
Power Name VCCP Description Power dedicated with Phase Lock Loop (PLL). voltage should well-regulated input should provided with extremely impedance path power rail. There VCCP input. Quiet Power isolated power internal processing logic. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCQ inputs. Address Power isolated power sections address drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCA inputs. Data Power isolated power sections data drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCD inputs. Control Power isolated power control drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCC inputs. Host Power isolated power HI08 drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCH input. ESSI, SCI, Timer Power isolated power ESSI, SCI, timer drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCS inputs. These designations package-dependent. Some packages connect inputs except VCCP each other internally. those packages, power input except VCCP labeled VCC. numbers connections indicated this table minimum values; total connections package-dependent.
VCCQ
VCCA
VCCD
VCCC
VCCH
VCCS
Note:
DSP56303 Technical Data
Ground
GROUND
Table 1-3. Grounds
Ground Name GNDP Description Ground Ground dedicated use. connection should provided with extremely low-impedance path ground. VCCP should bypassed GNDP 0.47 capacitor located close possible chip package. There GNDP connection. Ground Ground dedicated use. connection should provided with extremely low-impedance path ground. There GNDP1 connection. Quiet Ground isolated ground internal processing logic. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDQ connections. Address Ground isolated ground sections address drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDA connections. Data Ground isolated ground sections data drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDD connections. Control Ground isolated ground control drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDC connections. Host Ground isolated ground HI08 drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDH connection. ESSI, SCI, Timer Ground isolated ground ESSI, SCI, timer drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDS connections.
GNDP1
GNDQ
GNDA
GNDD
GNDC
GNDH
GNDS
Note:
These designations package-dependent. Some packages connect inputs except GNDP GNDP1 each other internally. those packages, ground connections except GNDP GNDP1 labeled GND. numbers connections indicated this table minimum values; total connections package-dependent.
DSP56303 Technical Data
Clock
CLOCK
Table 1-4. Clock Signals
Signal Name EXTAL Type Input State During Reset Input Signal Description External Clock/Crystal Input Interfaces internal crystal oscillator input external crystal external clock. Crystal Output Connects internal crystal oscillator output external crystal. external clock used, leave XTAL unconnected.
XTAL
Output
Chip-driven
PHASE LOCK LOOP (PLL)
Table 1-5. Phase Lock Loop Signals
Signal Name PCAP Type Input State During Reset Input Signal Description Capacitor Connects off-chip capacitor filter. Connect capacitor terminal PCAP other terminal VCCP. used, PCAP tied GND, left floating. CLKOUT Output Chip-driven Clock Output Provides output clock synchronized internal core clock phase. enabled both multiplication division factors equal one, then CLKOUT also synchronized EXTAL. disabled, CLKOUT frequency half frequency EXTAL. PINIT/NMI Input Input Initial/Non-Maskable Interrupt During assertion RESET, value PINIT/NMI written into Enable (PEN) control register, determining whether enabled disabled. After RESET deassertion during normal instruction processing, PINIT/NMI Schmitt-trigger input negative-edge-triggered Non-Maskable Interrupt (NMI) request internally synchronized CLKOUT. PINIT/NMI tolerate
DSP56303 Technical Data
External Memory Expansion Port (Port
EXTERNAL MEMORY EXPANSION PORT (PORT
Note: When DSP56303 enters low-power standby mode (Stop Wait), releases mastership tri-states relevant Port signals: A0-A17, D0-D23, AA0/RAS0-AA3/RAS3, CAS, BCLK, BCLK.
EXTERNAL ADDRESS
Table 1-6. External Address Signals
Signal Name A0-A17 Type Output State During Reset Tri-stated Signal Description Address When master, A0-A17 specify address external program data memory accesses. Otherwise, signals tri-stated. minimize power dissipation, A0-A17 change state when external memory spaces being accessed.
EXTERNAL DATA
Table 1-7. External Data Signals
Signal Name D0-D23 Type Input/Output State During Reset Tri-stated Signal Description Data When master, D0-D23 provide bidirectional data external program data memory accesses. Otherwise, D0-D23 tri-stated.
EXTERNAL CONTROL
Table 1-8. External Control Signals
Signal Name AA0-AA3/ RAS0-RAS3 Type Output State During Reset Tri-stated Signal Description Address Attribute Address Strobe these signals function chip selects additional address lines. RAS, these signals used Dynamic Random Access Memory (DRAM) interface. These signals have programmable polarity. Read Enable When master, asserted read external memory data (D0-D23). Otherwise, tri-stated.
Output
Tri-stated
DSP56303 Technical Data
External Memory Expansion Port (Port
Table 1-8. External Control Signals (Continued)
Signal Name Type Output State During Reset Tri-stated Signal Description Write Enable When master, asserted write external memory data (D0-D23). Otherwise, tri-stated. Transfer Acknowledge DSP56303 master there external activity, DSP56303 master, input ignored. input Data Transfer Acknowledge (DTACK) function that extend external cycle indefinitely. number wait states 2,., infinity) added wait states inserted keeping deasserted. typical operation, deasserted start cycle, asserted enable completion cycle, deasserted before next cycle. current cycle completes clock period after asserted synchronous CLKOUT. number wait states determined input Control Register (BCR), whichever longer. minimum number wait states external cycles. functionality, must programmed least wait state. zero wait state access cannot extended deassertion; otherwise improper operation result. operate synchronously asynchronously, depending setting Operating Mode Register (OMR). functionality cannot used during DRAM-type accesses; otherwise improper operation result. Output Output (deasserted) Request Asserted when requests mastership deasserted when longer needs bus. asserted deasserted independently whether DSP56303 master slave. "parking" allows deasserted even though DSP56303 master (see description "parking" signal description). Request Hole (BRH) allows asserted under software control, even though does need bus. typically sent external arbitrator that controls priority, parking tenure each master same external bus. affected only requests external bus, never internal bus. During hardware reset, deasserted arbitration reset slave state. Grant Must asserted/deasserted synchronous CLKOUT proper operation. external arbitration circuit asserts when DSP56303 becomes next master. When asserted, DSP56303 must wait until deasserted before taking mastership. When deasserted, mastership typically given current cycle. This occur middle instruction that requires more than external cycle execution.
Input
Ignored Input
Input
Ignored Input
DSP56303 Technical Data
Interrupt Mode Control
Table 1-8. External Control Signals (Continued)
Signal Name Type State During Reset Signal Description Busy Indicates that active must asserted deasserted synchronous CLKOUT. Only after deasserted pending master become master (and then assert signal again). master keep asserted after ceasing activity, regardless whether asserted deasserted. This called "bus parking" allows current master reuse without re-arbitration until another device requires bus. deasserted "active pull-up" method (that driven high then released held high external pull-up resistor). requires external pull-up resistor. Output Tri-stated Column Address Strobe When master, DRAM uses strobe column address. Otherwise, Mastership Enable (BME) DRAM Control Register cleared, signal tri-stated. Clock When master, BCLK active when OMR[ATE] set. When BCLK active synchronized CLKOUT internal PLL, BCLK precedes CLKOUT one-fourth clock cycle. Clock When master, BCLK inverse BCLK signal. Otherwise, signal tri-stated.
Input/Outp Input
BCLK
Output
Tri-stated
BCLK
Output
Tri-stated
INTERRUPT MODE CONTROL
interrupt mode control signals select chip's operating mode comes hardware reset. After RESET deasserted, these inputs hardware interrupt request lines.
DSP56303 Technical Data
Interrupt Mode Control
Table 1-9. Interrupt Mode Control
Signal Name RESET Type Input State During Reset Input Signal Description Reset Deassertion RESET internally synchronized clock (CLKOUT). When asserted, chip placed Reset state internal phase generator reset. Schmitt-trigger input allows slowly rising input (such capacitor charging) reset chip reliably. RESET deasserted synchronous CLKOUT, exact start-up timing guaranteed, allowing multiple processors start operate synchronously. When RESET signal deasserted, initial chip operating mode latched from MODA, MODB, MODC, MODD inputs. RESET signal must asserted after power-up. RESET tolerate MODA/IRQA Input Input Mode Select A/External Interrupt Request Selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA/IRQA MODA, MODB, MODC, MODD select sixteen initial chip operating modes, latched into when RESET signal deasserted. Internally synchronized CLKOUT. IRQA asserted synchronous CLKOUT, multiple processors re-synchronized using WAIT instruction asserting IRQA exit Wait state. processor Stop standby state IRQA asserted, processor will exit Stop state. MODA/IRQA tolerate MODB/IRQB Input Input Mode Select B/External Interrupt Request Selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select sixteen initial chip operating modes, latched into when RESET signal deasserted. Internally synchronized CLKOUT. IRQB asserted synchronous CLKOUT, multiple processors re-synchronized using WAIT instruction asserting IRQB exit Wait state. MODB/IRQB tolerate
DSP56303 Technical Data
Host Interface (HI08)
Table 1-9. Interrupt Mode Control (Continued)
Signal Name MODC/IRQC Type Input State During Reset Input Signal Description Mode Select C/External Interrupt Request Selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select sixteen initial chip operating modes, latched into when RESET signal deasserted. Internally synchronized CLKOUT. IRQC asserted synchronous CLKOUT, multiple processors re-synchronized using WAIT instruction asserting IRQC exit Wait state. MODC/IRQC tolerate MODD/IRQD Input Input Mode Select D/External Interrupt Request Selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select sixteen initial chip operating modes, latched into when RESET signal deasserted. Internally synchronized CLKOUT. IRQD asserted synchronous CLKOUT, multiple processors re-synchronized using WAIT instruction asserting IRQD exit Wait state. MODD/IRQD tolerate
HOST INTERFACE (HI08)
HI08 provides fast, parallel data-to-8-bit port that directly connect host bus. HI08 supports variety standard buses directly connect number industry-standard microcomputers, microprocessors, DSPs, hardware.
Host Port Usage Considerations
Careful synchronization required when system reads multiple-bit registers that written another asynchronous system. This common problem when asynchronous systems connected they Host port). considerations proper operation discussed Table 1-10.
1-10
DSP56303 Technical Data
Host Interface (HI08)
Table 1-10. Host Port Usage Considerations
Action Asynchronous read receive byte registers Description When reading receive byte registers, Receive register High (RXH), Receive register Middle (RXM), Receive register (RXL), host interface programmer should interrupts poll Receive register Data Full (RXDF) flag that indicates data available. This assures that data receive byte registers valid. host interface programmer should write transmit byte registers, Transmit register High (TXH), Transmit register Middle (TXM), Transmit register (TXL), unless Transmit register Data Empty (TXDE) indicating that transmit byte registers empty. This guarantees that transmit byte registers transfer valid data Host Receive (HRX) register. host interface programmer must change Host Vector (HV) register only when Host Command (HC) clear. This practice guarantees that interrupt control logic receives stable vector.
Asynchronous write transmit byte registers
Asynchronous write host vector
Host Port Configuration
HI08 signal functions vary according programmed configuration interface determined bits HI08 Port Control Register (HPCR). Refer DSP56303 User's Manual detailed descriptions HI08 configuration registers.
Table 1-11. Host Interface
Signal Name H0-H7 Type Input/Output State During Reset Tri-stated Signal Description Host Data When HI08 programmed interface with non-multiplexed host function selected, these signals lines Data bus. Host Address When HI08 programmed interface with multiplexed host function selected, these signals lines Address/Data bus. Port When HI08 configured GPIO through HPCR, these signals individually programmed through HI08 Data Direction Register (HDDR). This input tolerant.
HAD0-HAD7
Input/Output
PB0-PB7
Input Output
DSP56303 Technical Data
1-11
Host Interface (HI08)
Table 1-11. Host Interface (Continued)
Signal Name Type Input State During Reset Input Signal Description Host Address Input When HI08 programmed interface with non-multiplexed host function selected, this signal line Host Address bus. Host Address Strobe When HI08 programmed interface with multiplexed host function selected, this signal Host Address Strobe (HAS) Schmitt-trigger input. polarity address strobe programmable, configured active-low (HAS) following reset. Port When HI08 configured GPIO through HPCR, this signal individually programmed through HDDR. This input tolerant. Input Input Host Address Input When HI08 programmed interface with non-multiplexed host function selected, this signal line Host Address bus. Host Address When HI08 programmed interface with multiplexed host function selected, this signal line Host Address bus. Port When HI08 configured GPIO through HPCR, this signal individually programmed through HDDR. This input tolerant. Input Input Host Address Input When HI08 programmed interface with non-multiplexed host function selected, this signal line Host Address bus. Host Address When HI08 programmed interface with multiplexed host function selected, this signal line Host Address bus. Port When HI08 configured GPIO through HPCR, this signal individually programmed through HDDR. This input tolerant.
HAS/HAS
Input
Input Output
Input
Input Output
Input
PB10
Input Output
1-12
DSP56303 Technical Data
Host Interface (HI08)
Table 1-11. Host Interface (Continued)
Signal Name Type Input State During Reset Input Signal Description Host Read/Write When HI08 programmed interface with single-data-strobe host function selected, this signal Host Read/Write input. Host Read Data When HI08 programmed interface with double-data-strobe host function selected, this signal Host Read Data strobe (HRD) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HRD) after reset. Port When HI08 configured GPIO through HPCR, this signal individually programmed through HDDR. This input tolerant. HDS/HDS Input Input Host Data Strobe When HI08 programmed interface with single-data-strobe host function selected, this signal Host Data Strobe (HDS) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HDS) following reset. Host Write Data When HI08 programmed interface with double-data-strobe host function selected, this signal Host Write Data Strobe (HWR) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HWR) following reset. Port When HI08 configured GPIO through HPCR, this signal individually programmed through HDDR. This input tolerant.
HRD/HRD
Input
PB11
Input Output
HWR/HWR
Input
PB12
Input Output
DSP56303 Technical Data
1-13
Host Interface (HI08)
Table 1-11. Host Interface (Continued)
Signal Name Type Input State During Reset Input Signal Description Host Chip Select When HI08 programmed interface with non-multiplexed host function selected, this signal Host Chip Select (HCS) input. polarity chip select programmable, configured active-low (HCS) after reset. Host Address When HI08 programmed interface with multiplexed host function selected, this signal line Host Address bus. Port When HI08 configured GPIO through HPCR, this signal individually programmed through HDDR. This input tolerant. HREQ/HREQ Output Input Host Request When HI08 programmed interface with single host request host function selected, this signal Host Request (HREQ) output. polarity host request programmable, configured active-low (HREQ) following reset. host request programmed driven open-drain output. Transmit Host Request When HI08 programmed interface with double host request host function selected, this signal Transmit Host Request (HTRQ) output. polarity host request programmable, configured active-low (HTRQ) following reset. host request programmed driven open-drain output. Port When HI08 programmed interface with multiplexed host signal configured GPIO through HPCR, this signal individually programmed through HDDR. This input tolerant.
HA10
Input
PB13
Input Output
HTRQ/HTRQ
Output
PB14
Input Output
1-14
DSP56303 Technical Data
Host Interface (HI08)
Table 1-11. Host Interface (Continued)
Signal Name HACK/HACK Type Input State During Reset Input Signal Description Host Acknowledge When HI08 programmed interface with single host request host function selected, this signal Host Acknowledge (HACK) Schmitt-trigger input. polarity host acknowledge programmable, configured active-low (HACK) after reset. Receive Host Request When HI08 programmed interface with double host request host function selected, this signal Receive Host Request (HRRQ) output. polarity host request programmable, configured active-low (HRRQ) after reset. host request programmed driven open-drain output. Port When HI08 configured GPIO through HPCR, this signal individually programmed through HDDR. This input tolerant.
HRRQ/HRRQ
Output
PB15
Input Output
DSP56303 Technical Data
1-15
Enhanced Synchronous Serial Interface (ESSI0)
ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI0)
synchronous serial interfaces (ESSI0 ESSI1) provide full-duplex serial port serial communication with variety serial devices, including more industry-standard CODECs, other DSPs, microprocessors, peripherals that implement Motorola Serial Peripheral Interface (SPI).
Table 1-12. Enhanced Synchronous Serial Interface (ESSI0)
Signal Name SC00 Type Input Output State During Reset Input Signal Description Serial Control Functions either Synchronous Asynchronous mode. Asynchronous mode, this signal isthe receive clock (Schmitt-trigger input). Synchronous mode, this signal either Transmitter output Serial Flag Port default configuration following reset GPIO. PC0, signal direction controlled through Port Directions Register (PRR0). signal configured ESSI signal SC00 through Port Control Register (PCR0). This input tolerant. SC01 Input/Output Input Serial Control Functions either Synchronous Asynchronous mode. Asynchronous mode, this signal receiver frame sync I/O. Synchronous mode, this signal either Transmitter output Serial Flag Port default configuration following reset GPIO. PC1, signal direction controlled through PRR0. signal configured ESSI signal SC01 through PCR0. This input tolerant. SC02 Input/Output Input Serial Control Signal frame sync both transmitter receiver Synchronous mode, transmitter only Asynchronous mode. When configured output, this signal internally generated frame sync signal. When configured input, this signal receives external frame sync signal transmitter (and receiver synchronous operation). Port default configuration following reset GPIO. PC2, signal direction controlled through PRR0. signal configured ESSI signal SC02 through PCR0. This input tolerant.
Input Output
Input Output
1-16
DSP56303 Technical Data
Enhanced Synchronous Serial Interface (ESSI0)
Table 1-12. Enhanced Synchronous Serial Interface (ESSI0) (Continued)
Signal Name SCK0 Type Input/Output State During Reset Input Signal Description Serial Clock Provides serial rate clock ESSI interface both transmitter receiver Synchronous modes, transmitter only Asynchronous modes. Although external serial clock independent asynchronous system clock, must exceed minimum clock cycle time (that system clock frequency must least three times external ESSI clock frequency). ESSI needs least three phases inside each half serial clock. Input Output Port default configuration following reset GPIO. PC3, signal direction controlled through PRR0. signal configured ESSI signal SCK0 through PCR0. This input tolerant. SRD0 Input/Output Input Serial Receive Data Receives serial data transfers data ESSI receive shift register. SRD0 input when data being received. Port default configuration following reset GPIO. PC4, signal direction controlled through PRR0. signal configured ESSI signal SRD0 through PCR0. This input tolerant. STD0 Input/Output Input Serial Transmit Data Transmits data from serial transmit shift register. STD0 output when data being transmitted. Port default configuration following reset GPIO. PC5, signal direction controlled through PRR0. signal configured ESSI signal STD0 through PCR0. This input tolerant.
Input Output
Input Output
DSP56303 Technical Data
1-17
Enhanced Synchronous Serial Interface (ESSI1)
ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI1)
Table 1-13. Enhanced Synchronous Serial Interface (ESSI1)
Signal Name SC10 Type Input Output State During Reset Input Signal Description Serial Control Selection Synchronous Asynchronous mode determines function. Asynchronous mode, this signal receive clock (Schmitt-trigger input). Synchronous mode, this signal either Transmitter output Serial Flag Port default configuration following reset GPIO. PD0, signal direction controlled through Port Directions Register (PRR1). signal configured ESSI signal SC10 through Port Control Register (PCR1). This input tolerant. SC11 Input/Output Input Serial Control Selection Synchronous Asynchronous mode determines function. Asynchronous mode, this signal receiver frame sync I/O. Synchronous mode, this signal either Transmitter output Serial Flag Port default configuration following reset GPIO. PD1, signal direction controlled through PRR1. signal configured ESSI signal SC11 through PCR1. This input tolerant. SC12 Input/Output Input Serial Control Signal Frame sync both transmitter receiver Synchronous mode, transmitter only Asynchronous mode. When configured output, this signal internally generated frame sync signal. When configured input, this signal receives external frame sync signal transmitter (and receiver Synchronous operation). Port default configuration following reset GPIO. PD2, signal direction controlled through PRR1. signal configured ESSI signal SC12 through PCR1. This input tolerant.
Input Output
Input Output
1-18
DSP56303 Technical Data
Enhanced Synchronous Serial Interface (ESSI1)
Table 1-13. Enhanced Synchronous Serial Interface (ESSI1) (Continued)
Signal Name SCK1 Type Input/Output State During Reset Input Signal Description Serial Clock Provides serial rate clock ESSI interface. Clock input output used transmitter receiver Synchronous modes, transmitter only Asynchronous modes. Although external serial clock independent asynchronous system clock, must exceed minimum clock cycle time (that system clock frequency must least three times external ESSI clock frequency). ESSI needs least three phases inside each half serial clock. Input Output Port default configuration following reset GPIO. PD3, signal direction controlled through PRR1. signal configured ESSI signal SCK1 through PCR1. This input tolerant. SRD1 Input/Output Input Serial Receive Data Receives serial data transfers ESSI receive shift register. SRD1 input when data being received. Port default configuration following reset GPIO. PD4, signal direction controlled through PRR1. signal configured ESSI signal SRD1 through PCR1. This input tolerant. STD1 Input/Output Input Serial Transmit Data Transmits data from serial transmit shift register. STD1 output when data being transmitted. Port default configuration following reset GPIO. PD5, signal direction controlled through PRR1. signal configured ESSI signal STD1 through PCR1. This input tolerant.
Input Output
Input Output
DSP56303 Technical Data
1-19
Serial Communication Interface (SCI)
SERIAL COMMUNICATION INTERFACE (SCI)
Serial Communication interface (SCI) provides full duplex port serial communication with other DSPs, microprocessors, peripherals such modems.
Table 1-14. Serial Communication Interface (SCI)
Signal Name Input Type State During Reset Input Signal Description Serial Receive Data Receives byte-oriented serial data transfers receive shift register. Port default configuration following reset GPIO. When configured PE0, signal direction controlled through Port Directions Register (PRR). signal configured signal through Port Control Register (PCR). This input tolerant. Output Input Serial Transmit Data Transmits data from transmit data register. Port default configuration following reset GPIO. When configured PE1, signal direction controlled through PRR. signal configured signal through PCR. This input tolerant. SCLK Input/Output Input Serial Clock Provides input output clock used transmitter and/or receiver. Port default configuration following reset GPIO. PE2, signal direction controlled through PRR. signal configured signal SCLK through PCR. This input tolerant.
Input Output
Input Output
Input Output
1-20
DSP56303 Technical Data
Timers
TIMERS
DSP56303 three identical independent timers. Each internal external clocking, interrupt DSP56303 after specified number events (clocks), signal external device after counting specific number internal events.
Table 1-15. Triple Timer Signals
Signal Name TIO0 Type Input Output State During Reset Input Signal Description Timer Schmitt-Trigger Input/Output external event counter Measurement mode, TIO0 input. Watchdog, Timer, Pulse Modulation mode, TIO0 output. default mode after reset GPIO input. This changed output configured Timer Input/Output through Timer Control/Status Register (TCSR0). This input tolerant. TIO1 Input Output Input Timer Schmitt-Trigger Input/Output external event counter Measurement mode, TIO1 input. Watchdog, Timer, Pulse Modulation mode, TIO1 output. default mode after reset GPIO input. This changed output configured Timer Input/Output through Timer Control/Status Register (TCSR1). This input tolerant. TIO2 Input Output Input Timer Schmitt-Trigger Input/Output external event counter Measurement mode, TIO2 input. Watchdog, Timer, Pulse Modulation mode, TIO2 output. default mode after reset GPIO input. This changed output configured Timer Input/Output through Timer Control/Status Register (TCSR2). This input tolerant.
DSP56303 Technical Data
1-21
JTAG/ONCE INTERFACE
Table 1-16. JTAG/OnCE Interface
Signal Name Input Type State During Reset Input Signal Description Test Clock test clock signal synchronizing JTAG test logic. This input tolerant. Input Input Test Data Input test data serial signal test instructions data. sampled rising edge internal pull-up resistor. This input tolerant. Output Tri-stated Test Data Output test data serial signal test instructions data. tri-statable, actively driven shift-IR shift-DR controller states, changes falling edge TCK. Test Mode Select Sequences test controller's state machine, sampled rising edge TCK, internal pull-up resistor. This input tolerant. TRST Input Input Test Reset Asynchronously initializes test controller, internal pull-up resistor, must asserted after power This input tolerant.
Input
Input
1-22
DSP56303 Technical Data
JTAG/OnCE Interface
Table 1-16. JTAG/OnCE Interface (Continued)
Signal Name Type Input/Output State During Reset Input Signal Description Debug Event Provides enter Debug mode from external command controller input) acknowledge that chip entered Debug mode output). When asserted input, causes DSP56300 core finish current instruction, save instruction pipeline information, enter Debug mode, wait commands from debug serial input line. When debug request breakpoint condition cause chip enter Debug mode asserted output three clock cycles. internal pull-up resistor. standard part JTAG Test Access Port (TAP) Controller. connects OnCE module initiate Debug mode directly provide direct external indication that chip entered Debug mode. other interface with OnCE module must occur through JTAG port. This input tolerant.
DSP56303 Technical Data
1-23
JTAG/OnCE Interface
1-24
DSP56303 Technical Data
SECTION SPECIFICATIONS: UDR2 PROCESS TECHNOLOGY MASKS
INTRODUCTION
DSP56303 fabricated high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs outputs. DSP56303 specifications preliminary from design simulations, they fully tested guaranteed. Finalized specifications will published after full characterization device qualifications complete.
CAUTION
DSP56303 Technical Data
This Section contains specifications masks 0F94R, 1F94R, 0F88S, 0J22A, 2J22A, 3J22A, 4J22A DSP56303. These masks Motorola's Universal Design Rules (UDR2) process technology. Section specifications more recent masks DSP56303 that Motorola's Communications Design Rules (CDR2) process technology.
2A-1
Maximum Ratings
Specifications: UDR2 Process Technology Masks
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting against damage high static voltage electrical fields; however, normal precautions should taken avoid exceeding maximum voltage ratings. Reliability enhanced unused inputs tied appropriate logic voltage level (for example, either VCC).
Note: calculation timing requirements, adding maximum value specification minimum value another specification does yield reasonable sum. maximum specification calculated using worst case variation process parameter values direction. minimum specification calculated using worst case same parameters opposite direction. Therefore, "maximum" value specification will never occur same device that "minimum" value another specification; adding maximum minimum represents condition that never exist.
Table 2A-1. Maximum Ratings
Symbol Rating1 Value1,
Unit
Supply Voltage
-0.3
input voltages excluding tolerant" inputs3 tolerant" input voltages
VIN5
3.95
Current drain excluding Operating temperature range Storage temperature Notes:
+100 +150
TSTG
-40C +100C, Absolute maximum ratings stress ratings only, functional operation maximum guaranteed. Stress beyond maximum rating affect device reliability cause permanent damage device. CAUTION: Tolerant" input voltages cannot more than 3.95 greater than supply voltage; this restriction applies "power on," well during normal operation. case, input voltages must higher than 5.75 Tolerant" inputs inputs that tolerate
2A-2
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
Thermal Characteristics
THERMAL CHARACTERISTICS
Table 2A-2. Thermal Characteristics
Characteristic Junction-to-ambient thermal resistance Junction-to-case thermal resistance Thermal characterization parameter Notes: Symbol RqJA RqJC TQFP Value 55.7 11.4 PBGA3 Value PBGA4 Value Unit
°C/W °C/W °C/W
ELECTRICAL CHARACTERISTICS
Table 2A-3. Electrical Characteristics6
Symbol Characteristics VIHP VIHX VILP VILX ITSI 0.01 -0.3 -0.3 -0.3 DSP56303 Technical Data
Junction-to-ambient thermal resistance based measurements horizontal single-sided printed circuit board SEMI G38-87 natural convection.(SEMI Semiconductor Equipment Materials International, East Middlefield Rd., Mountain View, 94043, (415) 964-5111). Junction-to-case thermal resistance based measurements using cold plate SEMI G30-88, with exception that cold plate temperature used case temperature. These simulated values; testing complete. note test board conditions. These simulated values; testing complete. test board 2-ounce signal layers 1-ounce solid ground planes internal test board.
Unit
Supply voltage
Input high voltage D(0-23), MOD1/IRQ1, RESET, PINIT/NMI JTAG/ESSI/SCI/Timer/HI08 pins EXTAL8 Input voltage D(0-23), MOD1/IRQ1, RESET, PINIT JTAG/ESSI/SCI/Timer/HI08 pins EXTAL8 Input leakage current
3.95
High impedance (off-state) input current Output high voltage (IOH -0.4 mA)5,7 CMOS (IOH mA)5
2A-3
Electrical Characteristics
Specifications: UDR2 Process Technology Masks
Table 2A-3. Electrical Characteristics6 (Continued)
Characteristics Output voltage (IOL open-drain pins mA)5,7 CMOS (IOL mA)5 Internal supply current2: Normal mode Wait mode3 Stop mode4 Symbol ICCI ICCW ICCS MHz: MHz: MHz: MHz: MHz: MHz: 0.01 Unit
supply current5 Input capacitance5 Notes:
Refers MODA/IRQA, MODB/IRQB, MODC/IRQC, MODD/IRQD pins. Power Consumption Considerations page provides formula compute estimated current requirements Normal mode. order obtain these results, inputs must terminated (that allowed float). Measurements based synthetic intensive benchmarks (see $SSHQGL[ power consumption numbers this specification percent measured results this benchmark. This reflects typical applications. Typical internal supply current measured with 100°C. order obtain these results, inputs must terminated (that allowed float). XTAL signals disabled during Stop state. order obtain these results, inputs that disconnected Stop mode must terminated (that allowed float). Periodically sampled percent tested. -40°C +100 This characteristic does apply XTAL PCAP. Driving EXTAL VIHX high VILX value cause additional power consumption current). minimize power consumption, minimum VIHX should lower than maximum VILX should higher than VCC.
ELECTRICAL CHARACTERISTICS
timing waveforms shown electrical characteristics section tested with maximum minimum pins except EXTAL, which tested using input levels shown 1RWH Table 2A-3. timing specifications, which referenced device input signal, measured production with respect percent point respective input signal's transition. DSP56303 output levels measured with production test machine reference levels respectively. Note: Although minimum value frequency EXTAL MHz, device test conditions rated speed.
2A-4
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
Internal Clocks
INTERNAL CLOCKS
Table 2A-4. Internal Clocks, CLKOUT
Expression1, Characteristics Symbol Internal operation frequency CLKOUT with enabled Internal operation frequency CLKOUT with disabled Internal clock CLKOUT high period With disabled With enabled With enabled Internal clock CLKOUT period With disabled With enabled With enabled MF)/ (PDF Ef/2
0.49 DF/MF 0.47 DF/MF 0.49 DF/MF 0.47 DF/MF DF/MF ICYC DSP56303 Technical Data
0.51 DF/MF 0.53 DF/MF
0.51 DF/MF 0.53 DF/MF
Internal clock CLKOUT cycle time with enabled
Internal clock CLKOUT cycle time with disabled Instruction cycle time Notes:
Division Factor External frequency External clock cycle Multiplication Factor Predivision Factor Internal clock cycle &ORFN *HQHUDWRU section )DPLO\ 0DQXDO detailed discussion PLL.
EXTERNAL CLOCK OPERATION
DSP56303 system clock derived from on-chip crystal oscillator, shown )LJXUH cover page, externally supplied. externally supplied square wave voltage source should connected EXTAL leaving XTAL physically connected board socket (see )LJXUH
2A-5
EXTERNAL CLOCK OPERATION (;7$/ ;7$/
Specifications: UDR2 Process Technology Masks (;7$/ ;7$/
;7$/
;7$/
Fundamental Frequency Fork Crystal Oscillator
Fundamental Frequency Crystal Oscillator
fOSC 32.768
Calculations were done 32.768 crystal with following parameters: load capacitance (CL) 12.5 shunt capacitance (C0) series resistance drive level
EXTAL
CLKOUT with disabled
CLKOUT with enabled
Note:
2A-6
fOSC
Suggested Component Values:
Suggested Component Values:
fOSC
Calculations were done 4/20 crystal with following parameters: CLof 30/20 series resistance 100/20 drive level
Figure 2A-1. Crystal Oscillator Circuits
VIHC
Midpoint
VILC
midpoint (VIHC VILC).
Figure 2A-2. External Clock Timing
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
EXTERNAL CLOCK OPERATION
Table 2A-5. Clock Operation
Characteristics Symbol
Frequency EXTAL (EXTAL Frequency) rise fall time this external clock should maximum. EXTAL input high1, With disabled (46.7%-53.3% duty cycle6) With enabled (42.5%-57.5% duty cycle6) EXTAL input low1, With disabled (46.7%-53.3% duty cycle6) With enabled (42.5%-57.5% duty cycle6) EXTAL cycle time2 With disabled With enabled
66.0
80.0
7.08 6.44 157.0 7.08 6.44 157.0 15.15 15.15 273.1 11.0 ICYC 8.53 30.3 15.15 DSP56303 Technical Data
5.84 5.31
157.0
5.84 5.31
157.0
12.50 12.50
273.1 11.0
CLKOUT change from EXTAL fall with disabled
CLKOUT rising edge from EXTAL rising edge with enabled MHz)3,5 CLKOUT rising edge from EXTAL rising edge with enabled MHz)3,5 CLKOUT falling edge from EXTAL falling edge with enabled MHz)3,5
Instruction cycle time ICYC (see Table 2A-4) (46.7%-53.3% duty cycle) With disabled With enabled
25.0 12.50
8.53
2A-7
Phase Lock Loop (PLL) Characteristics
Specifications: UDR2 Process Technology Masks
Table 2A-5. Clock Operation (Continued)
Characteristics Symbol
Notes:
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Characteristics
Table 2A-6. Characteristics
Measured percent input transition. maximum value enabled given minimum maximum Periodically sampled percent tested. maximum value enabled given minimum maximum skew guaranteed other value. indicated duty cycle specified maximum frequency which part rated. minimum clock high time required correction operation, however, remains same lower operating frequencies; therefore, when lower clock frequency used, signal symmetry vary from specified duty cycle long minimum high time time requirements met.
Unit
frequency when enabled 2/PDF) external capacitor (PCAP VCCP) (CPCAP1) Note:
425)
590)
425)
590)
CPCAP value capacitor (connected between PCAP VCCP). recommended value CPCAP computed from following equations: (500 150,
2A-8
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
Reset, Stop, Mode Select, Interrupt Timing
RESET, STOP, MODE SELECT, INTERRUPT TIMING
Table 2A-7. Reset, Stop, Mode Select, Interrupt Timing6
Characteristics Expression Delay from RESET assertion pins reset value3 Required RESET duration4 Power external clock generator, disabled Power external clock generator, enabled Power internal oscillator During STOP, XTAL disabled (PCTL During STOP, XTAL enabled (PCTL During normal operation Delay from asynchronous RESET deassertion first external address output (internal reset deassertion)5 Minimum 26.0 26.0 Unit
760.0 15.2 1.14 1.14 38.0 38.0 625.0 12.5 1000 75000 75000 31.3 31.3 MHz: 3.25 MHz: 3.25 MHz: 20.25 11.0 MHz: 20.25 9.95 51.0 42.6 318.0 15.2 3.25 20.25 50.0 30.0 312.0 41.6 30.0 DSP56303 Technical Data
263.1
Maximum
Synchronous reset setup time from RESET deassertion CLKOUT Transition Minimum Maximum
12.5
Synchronous reset deasserted, delay time from CLKOUT Transition first external address output Minimum Maximum Mode select setup time Mode select hold time
258.1
2A-9
Reset, Stop, Mode Select, Interrupt Timing
Specifications: UDR2 Process Technology Masks
Table 2A-7. Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics Expression Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory access address valid Caused first interrupt instruction fetch Caused first interrupt instruction execution 10.0 8.25 Unit
10.0
8.25
4.25 66.0 55.1 92.6 7.25 112.0 157.0 130.0 MHz8: 3.75 MHz8: 3.75 12.4 MHz8: 3.25 MHz8: 3.25 12.4 DSP56303 Technical Data
Delay from IRQA, IRQB, IRQC, IRQD, assertion general-purpose transfer output valid caused first interrupt instruction execution Delay from address output valid caused first interrupt instruction execute interrupt request deassertion level sensitive fast interrupts1 Delay from assertion interrupt request deassertion level sensitive fast interrupts1
2A-10
Specifications: UDR2 Process Technology Masks
Reset, Stop, Mode Select, Interrupt Timing
Table 2A-7. Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics Expression Delay from assertion interrupt request deassertion level sensitive fast interrupts1 DRAM Unit
SRAM
141.0 380.0 116.6 DSP56303 Technical Data
SRAM
SRAM
MHz8: 3.5) MHz8: 3.5) 12.4 MHz8: 3.5) MHz8: 3.5) 12.4 MHz8: MHz8: 12.4 MHz8: 2.5) MHz8: 2.5) 12.4
Synchronous interrupt setup time from IRQA, IRQB, IRQC, IRQD, assertion CLKOUT Transition
Synchronous interrupt delay time from CLKOUT Transition first external address output valid caused first instruction fetch after coming Wait Processing state Minimum 9.25 24.75 Maximum Duration IRQA assertion recover from Stop state
314.4
2A-11
Reset, Stop, Mode Select, Interrupt Timing
Specifications: UDR2 Process Technology Masks
Table 2A-7. Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics Expression Delay from IRQA assertion fetch first instruction (when exiting Stop)2, active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL (Implies Stop Delay) Duration level-sensitive IRQA assertion ensure interrupt service (when exiting Stop)2, active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL (implies Stop delay) Interrupt Requests Rate HI08, ESSI, SCI, Timer IRQ, (edge trigger) IRQ, (level trigger) Unit
(128 PLC/2)
64.1
17.0
(8.25 0.5) 117.4 132.6 96.9 (128K PLC/2) (20.5 0.5) 64.1 17.0 62.1 15.4 83.4 68.8 12TC 12TC 4.25 66.0 181.8 121.2 121.2 181.8 90.9 106.1 30.3 45.5 55.1 DSP56303 Technical Data
(23.75 352.3 62.1 290.6 15.4 0.5)
109.4
150.0 100.0 100.0 150.0 75.0 87.5 25.0 37.5
Requests Rate Data read from HI08, ESSI, Data write HI08, ESSI, Timer IRQ, (edge trigger) Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory (DMA source) access address valid
2A-12
Specifications: UDR2 Process Technology Masks
Reset, Stop, Mode Select, Interrupt Timing
Table 2A-7. Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics Expression Notes: Unit
When fast interrupts used with IRQA, IRQB, IRQC, IRQD defined level-sensitive, timings through apply prevent multiple interrupt service. avoid these timing restrictions, deasserted Edge-triggered mode recommended when using fast interrupts. Long interrupts recommended when using Level-sensitive mode. This timing depends several settings: disable, using internal oscillator (PLL Control Register (PCTL) oscillator disabled during Stop (PCTL stabilization delay required assure oscillator stable before executing programs. that case, resetting Stop delay (OMR will provide proper delay. While possible recommended these specifications guarantee timings that case. disable, using internal oscillator (PCTL oscillator enabled during Stop (PCTL 17=1), stabilization delay required recovery time minimal (OMR setting ignored). disable, using external clock (PCTL stabilization delay required recovery time defined PCTL settings. enable, PCTL shutdown during Stop. Recovering from Stop requires locked. lock procedure duration, Lock Cycles (PLC), range 1000 cycles. This procedure occurs parallel with stop delay counter, stop recovery will when last these events occurs. stop delay counter completes count lock procedure completion. value disable
DSP56303 Technical Data
maximum value 4096 (maximum divided desired internal frequency (that 4096/66 ms). During stabilization period, will constant, their width vary, timing vary well.
Periodically sampled percent tested. external clock generator, RESET duration measured during time which RESET asserted, valid, EXTAL input active valid. internal oscillator, RESET duration measured during time which RESET asserted valid. specified timing reflects crystal oscillator stabilization time after power-up. This number affected specifications crystal other components connected oscillator reflects worst case conditions.
When valid, other "required RESET duration" conditions specified above) have been met, device circuitry uninitialized state that result significant power consumption heat-up. Designs should minimize this state shortest possible duration. does lose lock. -40°C +100°C, number wait states (measured clock cycles, number TC). expression compute maximum value.
2A-13
Reset, Stop, Mode Select, Interrupt Timing
Specifications: UDR2 Process Technology Masks
RESET Pins Reset Value
CLKOUT
RESET
A0-A17
2A-14
Figure 2A-3. Reset Timing
A0-A17
First Fetch
Figure 2A-4. Synchronous Reset Timing
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
Reset, Stop, Mode Select, Interrupt Timing )LUVW ,QWHUUXSW ,QVWUXFWLRQ ([HFXWLRQ)HWFK
A0-A17
IRQA, IRQB, IRQC, IRQD,
IRQA, IRQB, IRQC, IRQD,
IRQA, IRQB, IRQC, IRQD,
First Interrupt Instruction Execution General Purpose IRQA, IRQB, IRQC, IRQD, General Purpose
Figure 2A-5. External Fast Interrupt Timing
Figure 2A-6. External Interrupt Timing (Negative Edge-Triggered)
DSP56303 Technical Data
2A-15
Reset, Stop, Mode Select, Interrupt Timing
Specifications: UDR2 Process Technology Masks
CLKOUT
IRQA, IRQB, IRQC, IRQD,
A0-A17
MODA, MODB, MODC, MODD, PINIT
IRQA
A0-A17
2A-16
Figure 2A-7. Synchronous Interrupt from Wait State Timing
RESET
IRQA, IRQB, IRQC, IRQD,
Figure 2A-8. Operating Mode Select Timing
)LUVW ,QVWUXFWLRQ )HWFK
Figure 2A-9. Recovery from Stop State Using IRQA
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
IRQA A0-A17 )LUVW ,54$ ,QWHUUXSW ,QVWUXFWLRQ )HWFK
Figure 2A-10. Recovery from Stop State Using IRQA Interrupt Service
IRQA, IRQB, IRQC, IRQD,
EXTERNAL MEMORY EXPANSION PORT (PORT
SRAM Timing
Characteristics
A0-A17 6RXUFH $GGUHVV First Interrupt Instruction Execution
Figure 2A-11. External Memory Access (DMA Source) Timing
Table 2A-8. SRAM Read Write Accesses3
Symbol Expression1 Address valid assertion pulse width2 tRC, 26.3 86.9 162.7 21.0 71.0 133.5
Unit
DSP56303 Technical Data
2A-17
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-8. SRAM Read Write Accesses3
Characteristics Symbol Expression1 Address valid assertion MHz: 0.25 MHz: 0.25 frequencies: 0.75 1.25
Unit
14.9 18.2 26.3 49.0 11.6 0.5) MHz: 0.25 MHz: 0.25 frequencies: 1.25 2.25 14.3 21.0 39.8 14.9 30.1 11.6 24.1 tAA, MHz: 0.75) 11.0 MHz: 0.75) MHz: 0.25) 11.0 MHz: 0.25) 15.5 tOHZ 0.75) 22.5 17.9 DSP56303 Technical Data
assertion pulse width
deassertion address valid
Address valid input data valid
12.4
assertion input data valid
deassertion data valid (data hold time) Address valid deassertion2
2A-18
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-8. SRAM Read Write Accesses3
Characteristics Symbol Expression1 Data valid deassertion (data setup time) (tDW) MHz: 0.25) MHz: 0.25) MHz: 0.25 MHz: 0.25 frequencies: 1.25 2.25
Unit
15.2 30.4 0.75 0.25 -0.25 0.25 1.25 2.25 1.25 2.25 3.25 0.75 1.75 2.75 -7.5 19.1 34.3 14.9 30.1 45.2 22.5 37.7 DSP56303 Technical Data
Data hold time from deassertion
11.8 24.3
15.8 28.3
assertion data active
-0.6 -6.8
deassertion data high impedance
Previous deassertion data active (write)
11.6 24.1 36.6 17.9 30.4
deassertion time
2A-19
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-8. SRAM Read Write Accesses3
Characteristics Symbol Expression1 deassertion time 11.7 34.4 49.5 27.8 40.3
Unit
Address valid assertion assertion pulse width deassertion address valid
setup before deassertion4 hold after deassertion Notes:
number wait states specified BCR. Timings 100, guaranteed design, tested. -40°C +100 negation: timing relative deassertion edge remains active.
2A-20
0.25) 0.25 1.25 2.25 15.1 11.8 15.9 31.0 12.6 25.1 0.25 DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
$$±$$
$$±$$
'DWD
Figure 2A-12. SRAM Read Access
'DWD
Figure 2A-13. SRAM Write Access
DSP56303 Technical Data
2A-21
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
DRAM Timing
selection guides Figure 2A-14 Figure 2A-17 page 2A-33 primary selection only. Final selection should based timing following tables. example, selection guide suggests that four wait states must used operation when using Page Mode DRAM. However, using information appropriate table, designer could choose evaluate whether fewer wait states might used determining which timing prevents operation MHz, running chip slightly lower frequency (for example, MHz), using faster DRAM becomes available), manipulating control factors such capacitive resistive load improve overall system performance.
'5$0 W\SH WS68 Note: This figure should used primary selection. exact detailed timings following tables.
2A-22
&KLS IUHTXHQF\ :DLW VWDWHV :DLW VWDWHV :DLW VWDWHV :DLW VWDWHV
Figure 2A-14. DRAM Page Mode Wait States Selection Guide
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-9. DRAM Page Mode Timings, Wait State (Low-Power Applications)1,
MHz6 Characteristics Symbol Expression Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses assertion data valid (read) tCAC 100.0 MHz6 Unit
1.25
62.5
42.5
41.7
25.8 42.5
Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion
Previous deassertion deassertion assertion pulse width
Last deassertion deassertion4 BRW[1-0] BRW[1-0] BRW[1-0] BRW[1-0] deassertion pulse width
67.5 tOFF tRSH 0.75 33.5 21.0 tRHCP tCAS 96.0 62.7 0.75 33.5 21.0 tCRP 1.75 3.25 4.25 6.25 81.5 156.5 206.5 306.5 21.0 21.0 12.7 12.7 tASC tCAH tRAL tRCS tRCH tWCH 0.75 0.75 0.25 33.5 21.0 96.0 33.7 20.8 70.5 62.7 21.2 12.5 45.5 DSP56303 Technical Data
52.3 102.2 135.5 202.1
Column address valid assertion assertion column address valid
Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width
2A-23
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-9. DRAM Page Mode Timings, Wait State (Low-Power Applications)1,
MHz6 Characteristics Symbol Expression Notes: Last assertion deassertion assertion deassertion Data valid assertion (Write) tRWL tCWL 1.75 1.75 0.25 0.75 83.2 83.2 33.5 54.0 54.0 21.0 MHz6 Unit
assertion data valid (write)
assertion assertion Last assertion deassertion
assertion data valid
deassertion data valid assertion data active
tWCS tROH 45.7 29.0 71.0 46.0 42.5 0.75 37.2 24.7 0.25 12.5 DSP56303 Technical Data
25.8
deassertion data high impedance
number wait states Page mode access specified DCR. refresh period specified DCR. timings calculated worst case. Some timings better specific cases (for example, equals read-after-read write-after-write sequences). BRW[1-0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ. Reduced clock speed allows Page Mode DRAM with Wait state (see Figure 2A-14). this time, there DRAMs fast enough with wait states Page mode 100MHz (see Figure 2A-14). However, DRAM speeds approaching two-wait-state compatibility.
2A-24
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-10. DRAM Page Mode Timings, Wait States1,
Characteristics Symbol Expression Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses 45.4 37.5 Unit
2.75
41.7
34.4
assertion data valid (read)
tCAC MHz: MHz: MHz: MHz: 15.2 30.4 tOFF tRSH 1.75 3.25 22.5 45.2 tRHCP tCAS 18.7 tCRP 24.4 47.2 62.4 92.8 1.25 1.75 1.25 14.9 tASC tCAH tRAL tRCS tRCH 11.2 22.5 41.5 15.1 DSP56303 Technical Data
12.3 24.8
Column address valid data valid (read)
deassertion data valid (read hold time) Last assertion deassertion
17.9 36.6 14.8
Previous deassertion deassertion assertion pulse width
Last deassertion deassertion5 BRW[1-0] BRW[1-0] BRW[1-0] BRW[1-0] deassertion pulse width
19.0 37.8 50.3 75.3
11.6 17.9 33.5 11.8
Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion
2A-25
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-10. DRAM Page Mode Timings, Wait States1, (Continued)
Characteristics Symbol Expression assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion tWCH tRWL tCWL 2.75 18.5 33.4 37.4 33.6 14.6 26.8 30.1 27.0 Unit
Data valid assertion (write)
MHz: 0.25 MHz: 0.25 1.75 22.5 17.9 tWCS tROH 10.9 33.9 27.3 MHz: 1.75 MHz: 1.75 19.0 0.75 11.1 0.25 DSP56303 Technical Data
assertion data valid (write)
assertion assertion Last assertion deassertion
assertion data valid
15.4
deassertion data valid6
assertion data active
deassertion data high impedance Notes:
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56303. timings calculated worst case. Some timings better specific cases (for example, equals read-after-read write-after-write sequences). BRW[1-0] (DRAM Control Register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ. this time, there DRAMs fast enough with wait states Page mode 100MHz (see Figure 2A-14). However, DRAM speeds approaching two-wait-state compatibility.
2A-26
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-11. DRAM Page Mode Timings, Three Wait States1,
Characteristics Symbol Expression Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses assertion data valid (read) tCAC 50.0 Unit
MHz: MHz: MHz: MHz:
53.0
43.7
22.8 37.9 tOFF tRSH 33.9 64.2 tRHCP tCAS 26.3 tCRP 2.25 3.75 4.75 6.75 28.2 51.0 66.0 96.3 18.7 tASC 11.2 tCAH tRAL tRCS tRCH tWCH 1.25 0.75 2.25 33.9 56.6 15.1 29.9 48.5 DSP56303 Technical Data
18.5 31.0
Column address valid data valid (read)
deassertion data valid (read hold time) Last assertion deassertion
27.3 52.3 21.0
Previous deassertion deassertion assertion pulse width
Last deassertion deassertion5 BRW[1-0] BRW[1-0] BRW[1-0] BRW[1-0] deassertion pulse width
22.2 40.9 53.4 78.4
14.8
Column address valid assertion
assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width
27.3 46.0 11.8 23.9 39.3
2A-27
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-11. DRAM Page Mode Timings, Three Wait States1, (Continued)
Characteristics Symbol Expression Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion tRWL tCWL tWCS tROH 3.75 3.25 1.25 52.5 44.9 33.9 14.6 42.6 36.3 27.3 11.3 24.8 Unit
Last assertion deassertion assertion data valid
deassertion data valid6 assertion data active
deassertion data high impedance Notes:
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56303. timings calculated worst case. Some timings better specific cases (for example, equals read-after-read write-after-write sequences). BRW[1-0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of page-access. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ.
49.0 39.8 MHz: MHz: 30.4 0.75 11.1 0.25
Table 2A-12. DRAM Page Mode Timings, Four Wait States1,
Symbol Expression
Unit
Characteristics
62.5
Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses
75.8
MHz: 2.75 MHz: 2.75
68.2
56.3
assertion data valid (read)
tCAC
34.2
27.9
2A-28
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-12. DRAM Page Mode Timings, Four Wait States1, (Continued)
Characteristics Symbol Expression Column address valid data valid (read) MHz: 3.75 MHz: 3.75
Unit
49.3
39.8 71.0
40.4
deassertion data valid (read hold time) Last assertion deassertion
tOFF tRSH
Previous deassertion deassertion assertion pulse width
Last deassertion deassertion5 BRW[1-0] BRW[1-0] BRW[1-0] BRW[1-0] deassertion pulse width
49.0 tRHCP tCAS 86.9 33.9 tCRP 2.75 4.25 5.25 7.25 35.7 58.6 73.8 103.9 26.3 tASC 11.2 tCAH tRAL 49.0 71.8 tRCS 1.25 1.25 3.25 4.75 3.75 1.25 15.1 15.2 45.0 tRCH tWCH tRWL tCWL tWCS 63.7 67.7 52.5 49.0 14.6 DSP56303 Technical Data
27.3
28.4 47.2 59.6 84.6 21.0
Column address valid assertion
assertion column address valid
39.8 58.5
Last column address valid deassertion deassertion assertion deassertion assertion
11.8 11.9 36.4
assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion
51.8 55.1 42.6 39.8 11.3
Data valid assertion (write) assertion data valid (write) assertion assertion
2A-29
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-12. DRAM Page Mode Timings, Four Wait States1, (Continued)
Characteristics Symbol Expression Last assertion deassertion assertion data valid tROH MHz: 3.25 MHz: 3.25 64.2 52.3
Unit
41.7
34.1
Notes:
assertion data active
deassertion data high impedance
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56303. timings calculated worst case. Some timings better specific cases (for example, equals read-after-read write-after-write sequences). BRW[1-0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ.
2A-30
0.75 11.1 0.25 DSP56303 Technical Data
deassertion data valid6
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
6qqr
6qqr
6qqr
Figure 2A-15. DRAM Page Mode Write Accesses
DSP56303 Technical Data
2A-31
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
6qqr
6qqr
2A-32
6qqr
Figure 2A-16. DRAM Page Mode Read Accesses
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks '5$0 7\SH WS68
External Memory Expansion Port (Port
Note:
This figure should used primary selection. exact detailed timings, following tables.
Table 2A-13. DRAM Out-of-Page Refresh Timings, Four Wait States1,
MHz4 MHz4 Unit 84.2 34.2 42.5
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion
:DLW VWDWHV :DLW VWDWHV :DLW VWDWHV :DLW VWDWHV
&KLS )UHTXHQF\
Figure 2A-17. DRAM Out-of-Page Wait States Selection Guide
Characteristics
Symbol
Expression
250.0
166.7 54.3
tRAC tCAC tOFF
2.75 1.25
130.0 55.0 67.5
1.75
83.5
DSP56303 Technical Data
2A-33
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-13. DRAM Out-of-Page Refresh Timings, Four Wait States1, (Continued)
MHz4 Characteristics3 Symbol Expression assertion pulse width assertion deassertion assertion deassertion assertion pulse width assertion assertion tRAS tRSH tCSH tCAS 3.25 1.75 2.75 1.25 158.5 83.5 133.5 58.5 104.3 54.3 87.7 37.7 MHz4 Unit
assertion column address valid deassertion assertion deassertion pulse width
address valid assertion assertion address valid
Column address valid assertion
assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion
2A-34
tRCD tRAD tCRP 73.0 60.5 77.0 64.5 48.0 39.7 1.25 2.25 1.75 1.75 1.25 0.25 108.5 83.5 83.5 58.5 71.0 54.3 54.3 37.7 tASR tRAH tASC tCAH 1.75 83.5 54.3 3.25 158.5 96.0 104.3 62.7 tRAL tRCS tRCH tRRH tWCH tWCR 0.75 0.25 71.2 33.8 70.8 145.8 46.2 21.3 45.8 95.8 DSP56303 Technical Data
52.0 43.7
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-13. DRAM Out-of-Page Refresh Timings, Four Wait States1, (Continued)
MHz4 Characteristics3 Symbol Expression Notes: assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion tRWL tCWL 4.75 4.25 2.25 1.75 220.5 233.2 208.2 108.5 83.5 145.5 154.0 137.4 71.0 125.8 MHz4 Unit
assertion assertion (refresh)
deassertion assertion (refresh) assertion deassertion
assertion data valid
deassertion data valid3
assertion data active deassertion data high impedance
54.3 tDHR 3.25 158.5 104.3 95.7 tWCS tCSR tRPC 145.7 21.0 58.5 12.7 37.7 1.25 tROH 221.0 146.0 192.5 0.75 0.25 37.2 24.7 12.5 DSP56303 Technical Data
number wait states page access specified DCR. refresh period specified DCR. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ. Reduced clock speed allows DRAM out-of-page access with four Wait states (see Figure 2A-17).
2A-35
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-14. DRAM Out-of-Page Refresh Timings, Eight Wait States1,
Characteristics3 Symbol Expression Random read write cycle time assertion data valid (read) tRAC MHz: 4.75 MHz: 4.75 MHz: 2.25 MHz: 2.25 MHz: MHz: 136.4 64.5 26.6 112.5 52.9 21.6 31.0 33.3 23.9
Unit
assertion data valid (read)
Column address valid data valid (read)
deassertion data valid (read hold time)
deassertion assertion assertion pulse width
assertion deassertion assertion deassertion assertion pulse width
assertion assertion
assertion column address valid
deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid
2A-36
tCAC 40.0 tOFF 3.25 5.75 3.25 4.75 2.25 45.2 83.1 45.2 68.0 30.1 36.6 67.9 36.6 55.4 24.1 tRAS tRSH tCSH tCAS tRCD tRAD 35.9 39.9 29.3 1.75 24.5 59.8 37.7 45.2 22.5 45.2 83.1 28.5 19.9 tCRP 4.25 2.75 3.25 1.75 0.75 3.25 5.75 49.1 30.4 36.6 17.9 36.6 67.9 tASR tRAH tASC tCAH DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-14. DRAM Out-of-Page Refresh Timings, Eight Wait States1, (Continued)
Characteristics3 Symbol Expression Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion tRAL tRCS tRCH tRRH 1.25 MHz: 0.25 MHz: 0.25 56.6 26.5 15.2 46.0 21.2 11.9 87.3
Unit
assertion deassertion assertion deassertion assertion pulse width
assertion deassertion assertion deassertion
Data valid assertion (write) assertion data valid (write) assertion data valid (write)
assertion assertion
assertion assertion (refresh)
deassertion assertion (refresh) assertion deassertion assertion data valid
deassertion data valid4 assertion data active deassertion data high impedance
tWCH tWCR 41.3 79.1 124.3 tRWL tCWL 8.75 7.75 4.75 3.25 5.75 128.3 113.1 68.0 45.2 83.1 tDHR tWCS tCSR tRPC 79.0 18.7 1.75 MHz: MHz: 0.75 0.25 22.5 tROH 124.8 11.1 106.1 DSP56303 Technical Data
33.3
64.6
101.8 105.1 92.6
55.4 36.6 67.9 64.5 14.8
17.9
102.3
2A-37
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-14. DRAM Out-of-Page Refresh Timings, Eight Wait States1, (Continued)
Characteristics3 Symbol Expression Notes:
Unit
number wait states out-of-page access specified DCR. refresh period specified DCR. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
Table 2A-15. DRAM Out-of-Page Refresh Timings, Eleven Wait States1,
Characteristics3
Symbol Expression 181.8 150.0 tRAC MHz: 6.25 MHz: 6.25 MHz: 3.75 MHz: 3.75 87.2 tCAC 49.3 MHz: MHz: 60.7 tOFF 4.25 7.75 5.25 6.25 3.75 1.75 5.75 4.25 60.4 49.1 tRAS 113.4 75.5 90.7 52.8 33.9 22.5 83.1 60.4 92.9 tRSH tCSH tCAS tRCD tRAD tCRP 41.9 30.5 61.6 74.1 42.9 27.3 17.9 67.9 49.1 DSP56303 Technical Data
Unit 71.6 40.4 49.8 35.3 25.9
Random read write cycle time
assertion data valid (read)
assertion data valid (read)
Column address valid data valid (read)
deassertion data valid (read hold time)
deassertion assertion assertion pulse width
assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width
2A-38
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-15. DRAM Out-of-Page Refresh Timings, Eleven Wait States1, (Continued)
Characteristics3 Symbol Expression address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion tASR tRAH tASC tCAH 4.25 1.75 0.75 5.25 7.75 60.4 22.5 75.5 49.1 17.9 61.6 92.9 71.0 33.5
Unit
deassertion assertion
deassertion assertion deassertion assertion
assertion deassertion assertion deassertion assertion pulse width
assertion deassertion assertion deassertion
Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh)
deassertion assertion (refresh) assertion deassertion
113.4 86.9 41.5 tRAL tRCS tRCH tRRH 1.75 MHz: 0.25 MHz: 0.25 22.5 tWCH tWCR 71.6 109.4 11.5 169.7 tRWL tCWL 11.75 10.25 5.75 5.25 7.75 2.75 11.5 173.7 151.0 83.1 75.5 tDHR tWCS tCSR tRPC tROH 113.4 94.2 18.7 37.7 170.2 DSP56303 Technical Data
17.9
58.3 89.6
139.3
142.7 130.1 67.9 61.6 92.9 77.0 14.8 30.4 139.8
2A-39
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-15. DRAM Out-of-Page Refresh Timings, Eleven Wait States1, (Continued)
Characteristics3 Symbol Expression assertion data valid MHz: MHz:
Unit
144.0
118.5
deassertion data valid4 assertion data active deassertion data high impedance Notes:
0.75
11.1
number wait states out-of-page access specified DCR. refresh period specified DCR. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
Table 2A-16. DRAM Out-of-Page Refresh Timings, Fifteen Wait States1,
Characteristics3
0.25 Symbol Expression 242.4 90.7 143.7 90.7 121.0 200.0 MHz: 8.25 MHz: 8.25 MHz: 4.75 MHz: 4.75 117.5 64.5 MHz: MHz: 6.25 9.75 6.25 8.25 75.8 74.1 117.9 74.1 99.1 tOFF tRAS tRSH tCSH DSP56303 Technical Data
Unit 96.6 52.9 62.3
Random read write cycle time
assertion data valid (read)
assertion data valid (read)
Column address valid data valid (read)
deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion assertion deassertion
2A-40
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-16. DRAM Out-of-Page Refresh Timings, Fifteen Wait States1, (Continued)
Characteristics3 Symbol Expression assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width tCAS tRCD tRAD tCRP 4.75 2.75 7.75 6.25 6.25 2.75 0.75 68.0 51.0 39.7 113.4 90.7 90.7 37.7 55.0 43.7 55.4 41.8 32.4 92.9 74.1 74.1 30.4 45.8 36.4
Unit
address valid assertion assertion address valid Column address valid assertion
assertion column address valid assertion column address valid Column address valid deassertion
deassertion assertion
deassertion assertion deassertion assertion
assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion
Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh)
tASR tRAH tASC tCAH 6.25 9.75 90.7 143.7 tRAL 102.1 72.0 tRCS tRCH tRRH 1.75 MHz: 0.25 MHz: 0.25 22.8 tWCH tWCR tRWL tCWL tWCS tCSR 86.7 139.7 15.5 15.75 14.25 8.75 6.25 9.75 230.3 234.3 211.6 128.6 90.7 143.7 139.6 18.7 DSP56303 Technical Data
74.1
117.9 83.5
58.7
18.2
70.8
114.6
189.3 192.6 173.8 105.4 74.1 117.9 114.5 14.8
2A-41
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-16. DRAM Out-of-Page Refresh Timings, Fifteen Wait States1, (Continued)
Characteristics3 Symbol Expression deassertion assertion (refresh) assertion deassertion assertion data valid tRPC tROH 4.75 15.5 MHz: MHz: 68.0 230.8 204.6 55.4 189.8 168.5
Unit
deassertion data valid3 assertion data active
deassertion data high impedance Notes:
number wait states out-of-page access specified DCR. refresh period specified DCR. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
2A-42
0.75 0.25 11.1 DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
$GGUHVV &ROXPQ $GGUHVV
Figure 2A-18. DRAM Out-of-Page Read Access
DSP56303 Technical Data
2A-43
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
2A-44
$GGUHVV &ROXPQ $GGUHVV 'DWD
Figure 2A-19. DRAM Out-of-Page Write Access
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Figure 2A-20. DRAM Refresh Access
DSP56303 Technical Data
2A-45
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Synchronous Timings (SRAM)
Table 2A-17. External Synchronous Timings (SRAM Access)3
Characteristics Expression1 CLKOUT high address, valid4 MHz: 0.25 MHz: 0.25
Unit
13.9
CLKOUT high address, invalid valid CLKOUT high (setup time)
CLKOUT high invalid (hold time) CLKOUT high data active CLKOUT high data valid
CLKOUT high data invalid
CLKOUT high data high impedance
Data valid CLKOUT high (setup)
CLKOUT high data invalid (hold) CLKOUT high assertion
CLKOUT high deassertion CLKOUT high assertion2
0.25 0.25 MHz: 0.25 MHz: 0.25 0.25 MHz: 0.25 MHz: 0.25 MHz: 0.75 MHz: 0.75 12.4 16.4 10.4 MHz: MHz: frequencies: 12.9 DSP56303 Technical Data
11.1
CLKOUT high deassertion
2A-46
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-17. External Synchronous Timings (SRAM Access)3 (Continued)
Characteristics Expression1 Notes:
Unit
number wait states specified BCR. assertion refers next rising edge CLKOUT. External synchronous timings should used only reference clock relative timings. T198 T199 valid Address Trace mode set. status (See T212) determine whether access referenced A0-A17 internal external, when this mode enabled.
&/.287 $$±$$
'DWD 'DWD
DSP56303 Technical Data
Figure 2A-21. Synchronous Timings SRAM (BCR Controlled)
2A-47
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
&/.287 $$±$$
Figure 2A-22. Synchronous Timings SRAM Controlled)
2A-48
'DWD 'DWD
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Arbitration Timings
Table 2A-18. Arbitration Timings
Characteristics Expression CLKOUT high assertion/deassertion1 asserted/deasserted CLKOUT high (setup) CLKOUT high deasserted/asserted (hold) deassertion CLKOUT high (input setup) CLKOUT high assertion (input hold) CLKOUT high assertion (output) Unit
CLKOUT high deassertion (output) high high impedance (output)
CLKOUT high address controls active CLKOUT high address controls high impedance
CLKOUT high active
CLKOUT high deassertion
CLKOUT high high impedance
Notes:
0.25 MHz: 0.25 MHz: 0.25 0.25 MHz: 0.25 MHz: 0.25 MHz: 0.75 MHz: 0.75 12.4 DSP56303 Technical Data
T212 valid Address Trace mode when set. deasserted internal accesses asserted external accesses.
2A-49
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
&/.287
$$±$$
2A-50
Figure 2A-23. Acquisition Timings
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
&/.287
$$±$$
DSP56303 Technical Data
Figure 2A-24. Release Timings Case (BRT Cleared)
2A-51
Host Interface Timing
Specifications: UDR2 Process Technology Masks
&/.287
$$±$$
HOST INTERFACE TIMING
Figure 2A-25. Release Timings Case (BRT Set)
Table 2A-19. Host Interface Timing1,
Expression
Unit
Characteristic10
Read data strobe assertion width5 HACK assertion MHz: width 15.0 MHz: 12.4 Read data strobe deassertion width5 HACK deassertion width Read data strobe deassertion width5 after "Last Data Register" reads8,11, between consecutive CVR, ICR, reads3 HACK deassertion width after "Last Data Register" reads8,11 MHz: 10.0 MHz:
30.2 15.0
24.9 12.4
47.9
39.5
2A-52
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
Host Interface Timing
Table 2A-19. Host Interface Timing1, (Continued)
Characteristic10 Expression Write data strobe assertion width6 Write data strobe deassertion width6 HACK write deassertion width after HCTR, HCVR "Last Data Register" writes 20.0 16.5 Unit
after TXH:TXM writes (with HLEND=0)8 after TXL:TXM writes (with HLEND=1)8
MHz: MHz: 25.0 15.0 15.0 30.0 15.0 MHz: 15.0 MHz: 12.4 30.2 15.0 25.0 DSP56303 Technical Data
MHz: 10.0 MHz:
47.9
39.5 20.6 12.4
assertion width
deassertion data strobe assertion4
Host data input setup time before write data strobe deassertion6 Host data input hold time after write data strobe deassertion6
12.4
Read data strobe assertion output data active from high impedance5 HACK assertion output data active from high impedance Read data strobe assertion output data valid5 HACK assertion output data valid
26.68 12.4
Read data strobe deassertion output data high impedance5 HACK deassertion output data high impedance Output data hold time after read data strobe deassertion5 Output data hold time after HACK deassertion
assertion read data strobe deassertion5
24.9 12.4
20.6
assertion write data strobe deassertion6 assertion output data valid hold time after data strobe deassertion4 Address (HAD7-HAD0) setup time before deassertion (HMUX=1) Address (HAD7-HAD0) hold time after deassertion (HMUX=1)
2A-53
Host Interface Timing
Specifications: UDR2 Process Technology Masks
Table 2A-19. Host Interface Timing1, (Continued)
Characteristic10 Expression HA10-HA8 (HMUX=1), A2-A0 (HMUX=0), HR/W setup time before data strobe assertion4 Read Write HA10-HA8 (HMUX=1), A2-A0 (HMUX=0), HR/W hold time after data strobe deassertion4 Delay from read data strobe deassertion host request assertion "Last Data Register" read5, MHz: 25.0 MHz: 20.6 Unit
55.3 45.6 MHz: 25.0 MHz: 20.6 47.7 39.4 25.0 300.0 DSP56303 Technical Data
22.55
Delay from write data strobe deassertion host request assertion "Last Data Register" write6,
Delay from data strobe assertion host request deassertion "Last Data Register" read write (HROD=0)4, Delay from data strobe assertion host request deassertion "Last Data Register" read write (HROD=1, open drain host request)4, Notes:
300.0
Host Port Usage Considerations page 1-10. timing diagrams below, controls pins drawn active low. polarity programmable. This timing applicable only consecutive reads from these registers executed. data strobe Host Read (HRD) Host Write (HWR) Dual Data Strobe mode Host Data Strobe (HDS) Single Data Strobe mode. read data strobe Dual Data Strobe mode Single Data Strobe mode. write data strobe Dual Data Strobe mode Single Data Strobe mode. host request HREQ Single Host Request mode HRRQ HTRQ Double Host Request mode. "Last Data Register" register address which last location read written data transfers. This RXL/TXL Little Endian mode (HLEND RXH/TXH Endian mode (HLEND this calculation, host request signal pulled resistor Open-drain mode. -40°C +100 This timing applicable only read from "Last Data Register" followed read from RXL, RXM, registers without first polling RXDF HREQ bits, waiting assertion HREQ signal.
2A-54
Specifications: UDR2 Process Technology Masks
Host Interface Timing
+$&. +'±+'
+5(4 +554 +754
+$±+$ +'±+'
+5(4
Figure 2A-26. Host Interrupt Vector Register (IVR) Read Timing Diagram
Figure 2A-27. Read Timing Diagram, Non-Multiplexed
DSP56303 Technical Data
2A-55
Host Interface Timing
Specifications: UDR2 Process Technology Masks
+$±+$
2A-56
+'±+' +5(4 +554 +754
Figure 2A-28. Write Timing Diagram, Non-Multiplexed
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
Host Interface Timing
+$±+$
+$'±+$' $GGUHVV 'DWD +5(4 +554 +754
Figure 2A-29. Read Timing Diagram, Multiplexed
DSP56303 Technical Data
2A-57
Timing
Specifications: UDR2 Process Technology Masks
+$±+$
+$'±+$'
+5(4 +554 +754
TIMING
Characteristics1
$GGUHVV 'DWD
Figure 2A-30. Write Timing Diagram, Multiplexed
Table 2A-20. Timing
Expression
Unit
Symbol tSCC2
Synchronous clock cycle Clock period Clock high period Output data setup clock falling edge (internal clock) Output data hold after clock rising edge (internal clock)
tSCC/2 10.0 tSCC/2 10.0 tSCC/4 -17.0
121.0 50.5 50.5 20.8
100.0 40.0 40.0 14.3
tSCC/4
22.7
18.8
2A-58
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
Timing
Table 2A-20. Timing (Continued)
Characteristics1 Symbol Expression Input data setup time before clock rising edge (internal clock) Input data valid before clock rising edge (internal clock) Clock falling edge output data valid (external clock) tSCC/4 25.0 62.8 56.3 Unit
tSCC/4
32.3
25.8
32.0 23.2 tACC3 969.7 tACC/2 10.0 474.8 474.8 454.9 tACC/2 10.0 tACC/2 30.0 tACC/2 30.0 454.9 DSP56303 Technical Data
32.0
Output data hold after clock rising edge (external clock) Input data setup time before clock rising edge (external clock)
20.5
Input data hold time after clock rising edge (external clock) Asynchronous clock cycle Clock period
800.0 390.0 390.0 370.0
Clock high period
Output data setup clock rising edge (internal clock) Output data hold after clock rising edge (internal clock) Notes:
370.0
-40°C +100 tSCC synchronous clock cycle time. (For internal clock, tSCC determined clock control register TC.) tACC asynchronous clock cycle time; value given Clock mode. (For internal clock, tACC determined clock control register TC.)
2A-59
Timing
Specifications: UDR2 Process Technology Masks
SCLK (Output)
Data Valid
SCLK (Input)
SCLK (Output) Data Valid
2A-60
Data Valid Internal Clock Data Valid Data Valid External Clock
Figure 2A-31. Synchronous Mode Timing
Figure 2A-32. Asynchronous Mode Timing
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
ESSI0/ESSI1 Timing
ESSI0/ESSI1 TIMING
Table 2A-21. ESSI Timings
Characteristics4, Symbol Expression Clock cycle1 Clock high period internal clock external clock Clock period internal clock external clock tSSICC 10.0 10.0 60.6 45.5 20.3 22.7 20.3 22.7 50.0 37.5 15.0 18.8 15.0 18.8 Condition6 Unit
37.0 22.0 37.0 22.0 39.0 37.0 39.0 37.0 36.0 21.0 37.0 22.0 10.0 19.0 10.0 19.0 23.0 23.0 19.0 23.0 23.0 19.0 DSP56303 Technical Data
rising edge (bl) high rising edge (bl) rising edge (wr) high2 rising edge (wr) low2 rising edge (wl) high rising edge (wl)
37.0 22.0 37.0 22.0
39.0 37.0 39.0 37.0 36.0 21.0
37.0 22.0
Data setup time before (SCK Synchronous mode) falling edge Data hold time after falling edge
input (bl, high before falling edge2 input (wl) high before falling edge input hold time after falling edge Flags input setup before falling edge Flags input hold time after falling edge
2A-61
ESSI0/ESSI1 Timing
Specifications: UDR2 Process Technology Masks
Table 2A-21. ESSI Timings (Continued)
Characteristics4, Symbol Expression rising edge (bl) high rising edge (bl) rising edge (wr) high2 rising edge (wr) low2 rising edge (wl) high rising edge (wl) 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 Condition6 Unit
rising edge data enable from high impedance
rising edge Transmitter drive enable assertion rising edge data valid
rising edge data high impedance3
rising edge Transmitter drive enable deassertion3 input (bl, setup time before falling edge2
input (wl) data enable from high impedance
input (wl) Transmitter drive enable assertion input (wl) setup time before falling edge
input hold time after falling edge Flag output valid after rising edge
2A-62
30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 21.0 42.6 21.0 41.3 21.0 31.0 16.0 34.0 20.0 31.0 16.0 34.0 20.0 21.0 21.0 27.0 27.0 31.0 32.0 18.0 31.0 32.0 18.0 21.0 21.0 DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
ESSI0/ESSI1 Timing
Table 2A-21. ESSI Timings (Continued)
Characteristics4, Symbol Expression Notes: Condition6 Unit
DSP56303 Technical Data
internal clock, external clock cycle defined Icyc ESSI control register. word-relative frame sync signal waveform relative clock operates same manner bit-length frame sync signal waveform, spreads from serial clock before first clock (same Length Frame Sync signal), until before last clock first word frame. Periodically sampled percent tested. -40°C +100 (SCK Pin) Transmit Clock (SC0 Pin) Receive Clock (SC2 Pin) Transmit Frame Sync (SC1 Pin) Receive Frame Sync Internal Clock External Clock Internal Clock, Asynchronous Mode (Asynchronous implies that different clocks) Internal Clock, Synchronous Mode (Synchronous implies that same clock) length word length word length relative
2A-63
ESSI0/ESSI1 Timing
Specifications: UDR2 Process Technology Masks
(Input/ Output) (Bit) (Word)
Data
Transmitter Drive Enable
(Bit)
(Word)
Flags Note:
2A-64
First Last Note
Network mode, output flag transitions occur start each time slot within frame. Normal mode, output flag state asserted entire frame period.
Figure 2A-33. ESSI Transmitter Timing
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
Timer Timing
(Input/ Output) (Bit)
TIMER TIMING
(Word) Data First Last (Bit) (Word) Flags
Figure 2A-34. ESSI Receiver Timing
Table 2A-22. Timer Timing
Characteristics Expression High Timer setup time from (Input) assertion CLKOUT rising edge 32.5 32.5 15.15 27.0 27.0 12.5 Unit
DSP56303 Technical Data
2A-65
Timer Timing
Specifications: UDR2 Process Technology Masks
Table 2A-22. Timer Timing (Continued)
Characteristics Expression Synchronous timer delay time from CLKOUT rising edge external memory access address valid caused first interrupt instruction execution 10.25 156.0 129.1 Unit
CLKOUT rising edge (Output) deassertion Minimum Maximum Note:
60.5 19.8 11.1 28.1
CLKOUT rising edge (Output) assertion Minimum Maximum 19.8
11.1
28.1
26.1
26.1
-40°C +100
Figure 2A-35. Timer Event Input Restrictions
&/.287
,QSXW
$GGUHVV
)LUVW ,QWHUUXSW ,QVWUXFWLRQ ([HFXWLRQ
Figure 2A-36. Timer Interrupt Generation
2A-66
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
GPIO Timing
&/.287
2XWSXW
Figure 2A-37. External Pulse Generation
GPIO TIMING
Table 2A-23. GPIO Timing
Expression
Unit 31.0
Characteristics
Note:
CLKOUT edge GPIO valid (GPIO delay time)
31.0
CLKOUT edge GPIO valid (GPIO hold time)
GPIO valid CLKOUT edge (GPIO set-up time) CLKOUT edge GPIO valid (GPIO hold time)
12.0
12.0
Fetch CLKOUT edge before GPIO change
6.75
102.3
84.4
-40°C +100
DSP56303 Technical Data
2A-67
JTAG Timing
Specifications: UDR2 Process Technology Masks
&/.287 2XWSXW
*3,2 2XWSXW *3,2 ,QSXW 9DOLG
JTAG TIMING
)HWFK LQVWUXFWLRQ 029( FRQWDLQV YDOXH *3,2 FRQWDLQV DGGUHVV *3,2 GDWD UHJLVWHU
Figure 2A-38. GPIO Timing
Table 2A-24. JTAG Timing
frequencies
Characteristics
Unit
frequency operation (1/(TC maximum MHz) cycle time Crystal mode
22.0
45.0
clock pulse width measured rise fall times
20.0
Boundary scan input data setup time Boundary scan input data hold time output data valid output high impedance TMS, data setup time TMS, data hold time data valid
24.0 25.0
40.0 40.0 44.0
2A-68
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
JTAG Timing
Table 2A-24. JTAG Timing (Continued)
frequencies Characteristics Notes: high impedance TRST assert time TRST setup time 100.0 40.0 44.0 Unit
-40°C +100 timings apply OnCE module data transfers because uses JTAG port interface.
,QSXW
,QSXW 'DWD ,QSXWV
'DWD 2XWSXWV
'DWD 2XWSXWV
'DWD 2XWSXWV
Figure 2A-39. Test Clock Input Timing Diagram
,QSXW 'DWD 9DOLG
2XWSXW 'DWD 9DOLG
2XWSXW 'DWD 9DOLG
Figure 2A-40. Boundary Scan (JTAG) Timing Diagram
DSP56303 Technical Data
2A-69
OnCE Module TimIng
Specifications: UDR2 Process Technology Masks
,QSXW ,QSXW
,QSXW 'DWD 9DOLG
2XWSXW 2XWSXW
2XWSXW 'DWD 9DOLG
2XWSXW
,QSXW
7567 ,QSXW
OnCE MODULE TIMING
2XWSXW 'DWD 9DOLG
Figure 2A-41. Test Access Port Timing Diagram
Figure 2A-42. TRST Timing Diagram
Table 2A-25. OnCE Module Timing
Expression
Characteristics frequency operation assertion time order enter Debug mode Response time when DSP56303 executing instructions from internal memory Debug acknowledge assertion time 1/(TC 22.0 10.0 30.0 10.0 32.7 55.5 22.0 113.3
Unit 28.8 47.5 22.0 98.8
2A-70
DSP56303 Technical Data
Specifications: UDR2 Process Technology Masks
OnCE Module TimIng
Table 2A-25. OnCE Module Timing (Continued)
Characteristics Expression Note: -40°C +100 Unit
Figure 2A-43. OnCE-Debug Request
DSP56303 Technical Data
2A-71
OnCE Module TimIng
Specifications: UDR2 Process Technology Masks
2A-72
DSP56303 Technical Data
SECTION SPECIFICATIONS: CDR2 PROCESS TECHNOLOGY MASKS
INTRODUCTION
DSP56303 fabricated high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs outputs. DSP56303 specifications preliminary from design simulations, they fully tested guaranteed. Finalized specifications will published after full characterization device qualifications complete.
CAUTION
This Section contains specifications masks 0H82G, 1HB2G, OK36A more recent masks DSP56303 that Motorola's Communications Design Rules (CDR2) process technology. Section specifications earlier masks DSP56303 that Motorola's Universal Design Rules (UDR2) process technology.
DSP56303 Technical Data
2B-1
Maximum Ratings
Specifications: CDR2 Process Technology Masks
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting against damage high static voltage electrical fields; however, normal precautions should taken avoid exceeding maximum voltage ratings. Reliability enhanced unused inputs tied appropriate logic voltage level (for example, either VCC).
Note: calculation timing requirements, adding maximum value specification minimum value another specification does yield reasonable sum. maximum specification calculated using worst case variation process parameter values direction. minimum specification calculated using worst case same parameters opposite direction. Therefore, "maximum" value specification will never occur same device that "minimum" value another specification; adding maximum minimum represents condition that never exist.
Table 2B-1. Maximum Ratings
Symbol Rating1 Value1,
Unit
Supply Voltage
-0.3 +4.0
input voltages excluding tolerant" inputs3 tolerant" input voltages
VIN5
3.95
Current drain excluding Operating temperature range Storage temperature Notes:
+100 +150
TSTG
-40C +100C, Absolute maximum ratings stress ratings only, functional operation maximum guaranteed. Stress beyond maximum rating affect device reliability cause permanent damage device. CAUTION: Tolerant" input voltages cannot more than 3.95 greater than supply voltage; this restriction applies "power on," well during normal operation. case, input voltages must higher than 5.75 Tolerant" inputs inputs that tolerate
2B-2
DSP56303 Technical Data
Specifications: CDR2 Process Technology Masks
Thermal Characteristics
THERMAL CHARACTERISTICS
Table 2B-2. Thermal Characteristics
Characteristic Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2 Thermal characterization parameter Notes: Symbol RqJA RqJC TQFP Value 55.7 11.4 PBGA3 Value PBGA4 Value Unit
°C/W °C/W °C/W
ELECTRICAL CHARACTERISTICS
Table 2B-3. Electrical Characteristics6
Symbol Characteristics VIHP VIHX VILP VILX ITSI 0.01 -0.3 -0.3 -0.3 DSP56303 Technical Data
Junction-to-ambient thermal resistance based measurements horizontal single-sided printed circuit board SEMI G38-87 natural convection.(SEMI Semiconductor Equipment Materials International, East Middlefield Rd., Mountain View, 94043, (415) 964-5111). Junction-to-case thermal resistance based measurements using cold plate SEMI G30-88, with exception that cold plate temperature used case temperature. These simulated values; testing complete. note test board conditions. These simulated values; testing complete. test board 2-ounce signal layers 1-ounce solid ground planes internal test board.
Unit
Supply voltage
Input high voltage D(0-23), MOD1/IRQ1, RESET, PINIT/NMI JTAG/ESSI/SCI/Timer/HI08 pins EXTAL8 Input voltage D(0-23), MOD1/IRQ1, RESET, PINIT JTAG/ESSI/SCI/Timer/HI08 pins EXTAL8 Input leakage current
3.95
High impedance (off-state) input current Output high voltage (IOH -0.4 mA)5,7 CMOS (IOH mA)5
2B-3
Electrical Characteristics
Specifications: CDR2 Process Technology Masks
Table 2B-3. Electrical Characteristics6 (Continued)
Characteristics Output voltage (IOL open-drain pins mA)5,7 CMOS (IOL mA)5 Internal supply current2: Normal mode Wait mode3 Symbol ICCI MHz: MHz: MHz: MHz: MHz: MHz: MHz: MHz: MHz: 0.01 Unit
Stop mode4
supply current Input capacitance5 Notes:
Refers MODA/IRQA, MODB/IRQB, MODC/IRQC, MODD/IRQD pins. Power Consumption Considerations page provides formula compute estimated current requirements Normal mode. order obtain these results, inputs must terminated (that allowed float). Measurements based synthetic intensive benchmarks (see $SSHQGL[ power consumption numbers this specification percent measured results this benchmark. This reflects typical applications. Typical internal supply current measured with 100°C. order obtain these results, inputs must terminated (that allowed float). order obtain these results, inputs that disconnected Stop mode must terminated (that allowed float). XTAL signals disabled during Stop state. Periodically sampled percent tested. -40°C +100 This characteristic does apply XTAL PCAP. Driving EXTAL VIHX high VILX value cause additional power consumption current). minimize power consumption, minimum VIHX should lower than maximum VILX should higher than VCC.
ELECTRICAL CHARACTERISTICS
timing waveforms shown electrical characteristics section tested with maximum minimum pins except EXTAL, which tested using input levels shown 1RWH Table 2B-3. timing specifications, which referenced device input signal, measured production with respect percent point respective input signal's transition. DSP56303 output levels measured with production test machine reference levels respectively.
2B-4
ICCW ICCS DSP56303 Technical Data
Specifications: CDR2 Process Technology Masks
Internal Clocks
Note: Although minimum value frequency EXTAL MHz, device test conditions rated speed.
INTERNAL CLOCKS
Table 2B-4. Internal Clocks, CLKOUT
Expression1, Characteristics Symbol Internal operation frequency CLKOUT with enabled MF)/ (PDF Ef/2
Internal operation frequency CLKOUT with disabled Internal clock CLKOUT high period With disabled With enabled With enabled Internal clock CLKOUT period With disabled With enabled With enabled
0.49 DF/MF 0.47 DF/MF 0.49 DF/MF 0.47 DF/MF DF/MF ICYC DSP56303 Technical Data
0.51 DF/MF 0.53 DF/MF
0.51 DF/MF 0.53 DF/MF
Internal clock CLKOUT cycle time with enabled
Internal clock CLKOUT cycle time with disabled Instruction cycle time Notes:
Division Factor External frequency External clock cycle Multiplication Factor Predivision Factor Internal clock cycle &ORFN *HQHUDWRU section )DPLO\ 0DQXDO detailed discussion PLL.
2B-5
EXTERNAL CLOCK OPERATION
Specifications: CDR2 Process Technology Masks
EXTERNAL CLOCK OPERATION
DSP56303 system clock derived from on-chip crystal oscillator, shown Figure cover page, externally supplied. externally supplied square wave voltage source should connected EXTAL, leaving XTAL physically connected board socket (see Figure 2B-2).
(;7$/ ;7$/ (;7$/ ;7$/
Fundamental Frequency Fork Crystal Oscillator
Suggested Component Values:
fOSC 32.76
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