Embedded Programmable Logic Devices January 2001, ver. Featu
|
|
|
Top Searches for this datasheet
FLEX 10KE
Embedded Programmable Logic Devices
January 2001, ver.
Features.
Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip integration single device Enhanced embedded array implementing megafunctions such efficient memory specialized logic functions Dual-port capability with 16-bit width embedded array block (EAB) Logic array general logic functions High density 30,000 200,000 typical gates (see Tables 98,304 bits (4,096 bits EAB), which used without reducing logic capacity System-level features MultiVoltI/O pins drive driven 2.5-V, 3.3-V, 5.0-V devices power consumption Bidirectional performance (tSU tCO) Fully compliant with Special Interest Group (PCI SIG) Local Specification, Revision 3.3-V operation speed grade devices compliant with Local Specification, Revision 2.2, 5.0-V operation Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic
information 5.0-V FLEX® 3.3-V FLEX 10KA devices, FLEX Embedded Programmable Logic Family Data Sheet.
Table FLEX 10KE Device Features Feature
Typical gates Maximum system gates Logic elements (LEs) EABs Total bits Maximum user pins
EPF10K30E
30,000 119,000 1,728 24,576
EPF10K50E EPF10K50S
50,000 199,000 2,880 40,960
EPF10K100B
100,000 158,000 4,992 24,576
Altera Corporation
A-DS-F10KE-02.2
FLEX 10KE Embedded Programmable Logic Devices
Table FLEX 10KE Device Features Feature
Typical gates Maximum system gates Logic elements (LEs) EABs Total bits Maximum user pins Note tables:
embedded IEEE Std. 1149.1 JTAG circuitry adds 31,250 gates addition listed typical maximum system gates.
EPF10K100E
100,000 257,000 4,992 49,152
EPF10K130E
130,000 342,000 6,656 65,536
EPF10K200E EPF10K200S
200,000 513,000 9,984 98,304
.and More Features
Fabricated advanced process operate with 2.5-V internal supply voltage In-circuit reconfigurability (ICR) external configuration devices, intelligent controller, JTAG port ClockLockand ClockBoostoptions reduced clock delay/skew clock multiplication Built-in low-skew clock distribution trees 100% functional testing devices; test vectors scan chains required Pull-up pins before during configuration Flexible interconnect FastTrack® Interconnect continuous routing structure fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such fast adders, counters, comparators (automatically used software tools megafunctions) Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used software tools megafunctions) Tri-state emulation that implements internal tri-state buses global clock signals four global clear signals Powerful pins Individual tri-state output enable control each Open-drain option each Programmable output slew-rate control reduce switching noise Clamp VCCIO user-selectable pin-by-pin basis Supports hot-socketing
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Software design support automatic place-and-route provided Altera's development systems Windows-based SPARCstation, 9000 Series 700/800 Flexible package options Available variety packages with pins, including innovative FineLine BGApackages (see Tables SameFramepin-out compatibility with FLEX 10KA FLEX 10KE devices across range device densities counts Additional design entry simulation support provided EDIF netlist files, library parameterized modules (LPM), DesignWare components, Verilog HDL, VHDL, other interfaces popular tools from manufacturers such Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, Viewlogic Notes (1),
Table FLEX 10KE Package Options Count Device 144-Pin 208-Pin TQFP PQFP
240-Pin PQFP RQFP
256-Pin 356-Pin 484-Pin 599-Pin 600-Pin 672-Pin FineLine FineLine FineLine
EPF10K30E EPF10K50E EPF10K50S EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K200S Notes:
FLEX 10KE device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), pin-grid array (PGA), ball-grid array (BGA) packages. Devices same package pin-compatible, although some devices have more pins than others. When planning device migration, pins that common devices. This option supported with 484-pin FineLine package. using SameFrame migration, FineLine packages pin-compatible. example, board designed support 256-pin, 484-pin, 672-pin FineLine packages. Altera software automatically avoids conflicting pins when future migration set.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table FLEX 10KE Package Sizes Device 144Pin TQFP
0.50
208-Pin PQFP
0.50
240-Pin PQFP RQFP
0.50 1,197
256-Pin FineLine
356Pin
1.27 1,225
484-Pin FineLine
599-Pin
3,904
600Pin
1.27 2,025
672-Pin FineLine
Pitch (mm) Area (mm2)
Length width 30.6 30.6 34.6 34.6 62.5 62.5
General Description
Altera FLEX 10KE devices enhanced versions FLEX devices. Based reconfigurable CMOS SRAM elements, FLEX architecture incorporates features necessary implement common gate array megafunctions. With 200,000 typical gates, FLEX 10KE devices provide density, speed, features integrate entire systems, including multiple 32-bit buses, into single device. ability reconfigure FLEX 10KE devices enables 100% testing prior shipment allows designer focus simulation design verification. FLEX 10KE reconfigurability eliminates inventory management gate array designs generation test vectors fault coverage. Table shows FLEX 10KE performance some common designs. performance values were obtained with Synopsys DesignWare functions. Special design techniques required implement applications; designer simply infers instantiates function Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), schematic design file.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table FLEX 10KE Performance Application Resources Used EABs
16-bit loadable counter 16-bit accumulator 16-to-1 multiplexer 16-bit multiplier with 3-stage pipeline read cycle speed write cycle speed Notes:
This application uses combinatorial inputs outputs. This application uses registered inputs outputs.
Performance Speed Grade
Units
Table shows FLEX 10KE performance more complex designs. These designs available Altera MegaCore® functions. Table FLEX 10KE Performance Complex Designs Application Used Performance Speed Grade
8-bit, 16-tap parallel finite impulse response (FIR) filter 8-bit, 512-point fast Fourier transform (FFT) function a16450 universal asynchronous receiver/transmitter (UART) Note:
These values calculation time. Calculation time number clocks required/fmax. Number clocks required ceiling [log (points)/2] [points ceiling]
Units
28.7
38.9 20.5 MSPS
1,854
23.4
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Similar FLEX 10KE architecture, embedded gate arrays fastest-growing segment gate array market. with standard gate arrays, embedded gate arrays implement general logic conventional "sea-of-gates" architecture. Additionally, embedded gate arrays have dedicated areas implementing large, specialized functions. embedding functions silicon, embedded gate arrays reduce area increase speed when compared standard gate arrays. While embedded megafunctions typically cannot customized, FLEX 10KE devices programmable, providing designer with full control over embedded megafunctions general logic, while facilitating iterative design changes during debugging. Each FLEX 10KE device contains embedded array logic array. embedded array used implement variety memory functions complex logic functions, such digital signal processing (DSP), wide data-path manipulation, microcontroller applications, datatransformation functions. logic array performs same function sea-of-gates gate array used implement general logic such counters, adders, state machines, multiplexers. combination embedded logic arrays provides high performance high density embedded gate arrays, enabling designers implement entire system single device. FLEX 10KE devices configured system power-up with data stored Altera serial configuration device provided system controller. Altera offers EPC1, EPC2, EPC4, EPC16, EPC1441 configuration devices, which configure FLEX 10KE devices serial data stream. Configuration data also downloaded from system Altera BitBlasterTM, ByteBlasterMVTM, MasterBlaster download cables. After FLEX 10KE device been configured, reconfigured in-circuit resetting device loading data. Because reconfiguration requires less than real-time changes made during system operation. FLEX 10KE devices contain interface that permits microprocessors configure FLEX 10KE devices serially in-parallel, synchronously asynchronously. interface also enables microprocessors treat FLEX 10KE device memory configure writing virtual memory location, making easy reconfigure device.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
more information FLEX device configuration, following documents:
Configuration Devices APEX FLEX Devices Data Sheet BitBlaster Serial Download Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet MasterBlaster Download Cable Data Sheet Application Note (Configuring APEX 20K, FLEX 10K, FLEX 6000 Devices)
FLEX 10KE devices supported Altera development systems, which integrated packages that offer schematic, text (including AHDL), waveform design entry, compilation logic synthesis, full simulation worst-case timing analysis, device configuration. Altera software provides EDIF LPM, VHDL, Verilog HDL, other interfaces additional design entry simulation support from other industry-standard UNIX workstation-based tools. Altera software works easily with common gate array tools synthesis simulation. example, Altera software generate Verilog files simulation with tools such Cadence Verilog-XL. Additionally, Altera software contains libraries that devicespecific features such carry chains, which used fast counter arithmetic functions. instance, Synopsys Design Compiler library supplied with Altera development system includes DesignWare functions that optimized FLEX 10KE architecture. Altera development system runs Windows-based SPARCstation, 9000 Series 700/800.
MAX+PLUS Programmable Logic Development System Software Data Sheet Quartus Programmable Logic Development System Software Data Sheet more information.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Functional Description
Each FLEX 10KE device contains enhanced embedded array implement memory specialized logic functions, logic array implement general logic. embedded array consists series EABs. When implementing memory functions, each provides 4,096 bits, which used create RAM, ROM, dual-port RAM, first-in first-out (FIFO) functions. When implementing logic, each contribute gates towards complex logic functions, such multipliers, microcontrollers, state machines, functions. EABs used independently, multiple EABs combined implement larger functions. logic array consists logic array blocks (LABs). Each contains eight local interconnect. consists four-input look-up table (LUT), programmable flipflop, dedicated signal paths carry cascade functions. eight used create medium-sized blocks logic-such 8-bit counters, address decoders, state machines-or combined across LABs create larger logic blocks. Each represents about usable gates logic. Signal interconnections within FLEX 10KE devices well from device pins) provided FastTrack Interconnect routing structure, which series fast, continuous column channels that entire length width device. Each element (IOE) located each column FastTrack Interconnect routing structure. Each contains bidirectional buffer flipflop that used either output input register feed input, output, bidirectional signals. When used with dedicated clock pin, these registers provide exceptional performance. inputs, they provide setup times hold times outputs, these registers provide clock-to-output times IOEs provide variety features, such JTAG support, slew-rate control, tri-state buffers, open-drain outputs.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure shows block diagram FLEX 10KE architecture. Each group combined into LAB; groups LABs arranged into rows columns. Each also contains single EAB. LABs EABs interconnected FastTrack Interconnect routing structure. IOEs located each column FastTrack Interconnect routing structure. Figure FLEX 10KE Device Block Diagram
Embedded Array Block (EAB) Element (IOE)
Column Interconnect
Logic Array
Logic Array Block (LAB)
Logic Element (LE) Interconnect
Local Interconnect Logic Array
Embedded Array
FLEX 10KE devices provide dedicated inputs that drive flipflops' control inputs ensure efficient distribution high-speed, lowskew (less than control signals. These signals dedicated routing channels that provide shorter delays lower skews than FastTrack Interconnect routing structure. Four dedicated inputs drive four global signals. These four global signals also driven internal logic, providing ideal solution clock divider internally generated asynchronous clear signal that clears many registers device.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Embedded Array Block
flexible block RAM, with registers input output ports, that used implement common gate array megafunctions. Because large flexible, suitable functions such multipliers, vector scalars, error correction circuits. These functions combined applications such digital filters microcontrollers. Logic functions implemented programming with readonly pattern during configuration, thereby creating large LUT. With LUTs, combinatorial functions implemented looking results, rather than computing them. This implementation combinatorial functions faster than using algorithms implemented general logic, performance advantage that further enhanced fast access times EABs. large capacity EABs enables designers implement complex functions logic level without routing delays associated with linked field-programmable gate array (FPGA) blocks. example, single implement function with inputs outputs. Parameterized functions such functions take advantage automatically. FLEX 10KE provides advantages over FPGAs, which implement on-board arrays small, distributed blocks. These small FPGA blocks must connected together make blocks manageable size. blocks connected together using multiplexers implemented with more logic blocks. These extra multiplexers cause extra delay, which slows down block. FPGA blocks also prone routing problems because small blocks must connected together make larger blocks. contrast, EABs used implement large, dedicated blocks that eliminate these timing routing concerns. FLEX 10KE enhanced adds dual-port capability existing structure. dual-port structure ideal FIFO buffers with clocks. FLEX 10KE also support 16-bit-wide blocks backward-compatible with design containing FLEX EABs. FLEX 10KE dual-port single-port mode. When dual-port mode, separate clocks used read write sections, which allows written read different rates. also separate synchronous clock enable signals read write sections, which allow independent control these sections.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
also used bidirectional, dual-port memory applications where ports read write simultaneously. implement this type dual-port memory, EABs used support simultaneous read writes. Alternatively, clock clock enable used control input registers EAB, while different clock clock enable control output registers (see Figure Figure FLEX 10KE Device Dual-Port Mode
Dedicated Inputs Global Signals Dedicated Clocks
Notes (1),
Interconnect
data[
RAM/ROM Data 1,024 2,048
Data
rdaddress[ Local Interconnect wraddress[
Read Address
Write Address
rden wren outclocken
Read Enable
Write Enable
inclocken
inclock outclock
Write Pulse Generator
Multiplexers allow read address read enable registers clocked inclock outclock signals. Column Interconnect
Notes:
registers asynchronously cleared local interconnect signals, global signals, chip-wide reset. EPF10K100B device does offer dual-port mode. EPF10K30E EPF10K50E devices have local interconnect channels; EPF10K100E, EPF10K130E, EPF10K200E devices have local interconnect channels.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
also Altera megafunctions implement dual-port applications where both ports read write, shown Figure Figure FLEX 10KE Dual-Port Mode
Port address_a[] data_a[] we_a clkena_a Clock Port address_b[] data_b[] we_b clkena_b Clock
FLEX 10KE used single-port mode, which useful backward-compatibility with FLEX designs (see Figure
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure FLEX 10KE Device Single-Port Mode
Dedicated Clocks Dedicated Inputs Global Signals Chip-Wide Reset
Interconnect
RAM/ROM Data 1,024 2,048
Data
Local Interconnect
Address
Write Enable
Column Interconnect
Note:
EPF10K30E, EPF10K50E, EPF10K50S devices have local interconnect channels; EPF10K100E, EPF10K100B, EPF10K130E, EPF10K200E, EPF10K200S devices have local interconnect channels.
EABs used implement synchronous RAM, which easier than asynchronous RAM. circuit using asynchronous must generate write enable signal, while ensuring that data address signals meet setup hold time specifications relative write enable signal. contrast, EAB's synchronous generates write enable signal self-timed with respect input write clock. circuit using EAB's self-timed must only meet setup hold time specifications global clock.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
When used RAM, each configured following sizes: 1,024 2,048 (see Figure Figure FLEX 10KE Memory Configurations
1,024
2,048
Larger blocks created combining multiple EABs. example, blocks combined form block; blocks combined form block (see Figure Figure Examples Combining FLEX 10KE EABs
necessary, EABs device cascaded form single block. EABs cascaded form blocks 2,048 words without impacting timing. Altera software automatically combines EABs meet designer's specifications.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
EABs provide flexible options driving controlling clock signals. Different clocks clock enables used reading writing EAB. Registers independently inserted data input, output, write address, write enable signals, read address, read enable signals. global signals local interconnect drive write enable, read enable, clock enable signals. global signals, dedicated clock pins, local interconnect drive clock signals. Because drive local interconnect, control write enable, read enable, clear, clock, clock enable signals. interconnect drive column interconnects. Each output drive channels column channels; unused channel driven other LEs. This feature increases routing resources available outputs (see Figures column interconnect, which adjacent EAB, twice many channels other columns device.
Logic Array Block
consists eight LEs, their associated carry cascade chains, control signals, local interconnect. provides coarse-grained structure FLEX 10KE architecture, facilitating efficient routing with optimum device utilization high performance (see Figure
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure FLEX 10KE
Dedicated Inputs Global Signals
Interconnect
Local Interconnect
Carry-In Cascade-In
Figure details.
Control Signals
Column-to-Row Interconnect
Column Interconnect
Carry-Out Cascade-Out
Notes:
EPF10K30E, EPF10K50E, EPF10K50S devices have inputs local interconnect channel from row; EPF10K100E, EPF10K100B, EPF10K130E, EPF10K200E, EPF10K200S devices have EPF10K30E, EPF10K50E, EPF10K50S devices have local interconnect channels; EPF10K100E, EPF10K100B, EPF10K130E, EPF10K200E, EPF10K200S devices have EPF10K100B devices, four channels drive column channels each intersection.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Each provides four control signals with programmable inversion that used eight LEs. these signals used clocks, other used clear/preset control. clocks driven dedicated clock input pins, global signals, signals, internal signals local interconnect. preset clear control signals driven global signals, signals, internal signals local interconnect. global control signals typically used global clock, clear, preset signals because they provide asynchronous control with very skew across device. logic required control signal, generated more driven into local interconnect target LAB. addition, global control signals generated from outputs.
Logic Element
smallest unit logic FLEX 10KE architecture, compact size that provides efficient logic utilization. Each contains four-input LUT, which function generator that quickly compute function four variables. addition, each contains programmable flipflop with synchronous clock enable, carry chain, cascade chain. Each drives both local FastTrack Interconnect routing structure (see Figure Figure FLEX 10KE Logic Element
Carry-In Cascade-In
Register Bypass
Programmable Register
data1 data2 data3 data4
Look-Up Table (LUT)
Carry Chain
Cascade Chain
FastTrack Interconnect
CLRN Local Interconnect
labctrl1 labctrl2
Chip-Wide Reset
Clear/ Preset Logic
Clock Select
labctrl3 labctrl4
Carry-Out Cascade-Out
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
programmable flipflop configured operation. clock, clear, preset control signals flipflop driven global signals, general-purpose pins, internal logic. combinatorial functions, flipflop bypassed output drives output outputs that drive interconnect: drives local interconnect other drives either column FastTrack Interconnect routing structure. outputs controlled independently. example, drive output while register drives other output. This feature, called register packing, improve utilization because register used unrelated functions. FLEX 10KE architecture provides types dedicated high-speed data paths that connect adjacent without using local interconnect paths: carry chains cascade chains. carry chain supports high-speed counters adders cascade chain implements wide-input functions with minimum delay. Carry cascade chains connect well LABs same row. Intensive carry cascade chains reduce routing flexibility. Therefore, these chains should limited speed-critical portions design.
Carry Chain
carry chain provides very fast carry-forward function between LEs. carry-in signal from lower-order drives forward into higher-order carry chain, feeds into both next portion carry chain. This feature allows FLEX 10KE architecture implement high-speed counters, adders, comparators arbitrary width efficiently. Carry chain logic created automatically Altera Compiler during design processing, manually designer during design entry. Parameterized functions such DesignWare functions automatically take advantage carry chains. Carry chains longer than eight automatically implemented linking LABs together. enhanced fitting, long carry chain skips alternate LABs row. carry chain longer than skips either from even-numbered even-numbered LAB, from oddnumbered odd-numbered LAB. example, last first carries first third row. carry chain does cross middle row. instance, EPF10K50E device, carry chain stops eighteenth begins nineteenth LAB.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure shows n-bit full adder implemented with carry chain. portion generates bits using input signals carry-in signal; routed output register bypassed simple adders used accumulator function. Another portion carry chain logic generates carry-out signal, which routed directly carry-in signal next-higher-order bit. final carry-out signal routed where used general-purpose signal. Figure FLEX 10KE Carry Chain Operation (n-Bit Full Adder)
Carry-In
Register
Carry Chain
Register
Carry Chain
Register
Carry Chain
Register
Carry-Out
Carry Chain
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Cascade Chain
With cascade chain, FLEX 10KE architecture implement functions that have very wide fan-in. Adjacent LUTs used compute portions function parallel; cascade chain serially connects intermediate values. cascade chain logical logical (via Morgan's inversion) connect outputs adjacent LEs. delay each additional provides four more inputs effective width function. Cascade chain logic created automatically Altera Compiler during design processing, manually designer during design entry. Cascade chains longer than eight bits implemented automatically linking several LABs together. easier routing, long cascade chain skips every other row. cascade chain longer than skips either from even-numbered even-numbered LAB, from odd-numbered odd-numbered (e.g., last first cascades first third LAB). cascade chain does cross center (e.g., EPF10K50E device, cascade chain stops eighteenth begins nineteenth LAB). This break EAB's placement middle row. Figure shows cascade function connect adjacent form functions with wide fan-in. These examples show functions variables implemented with LEs. delay cascade chain delay With cascade chain, needed decode 16-bit address. Figure FLEX 10KE Cascade Chain Operation
Cascade Chain Cascade Chain
d[3.0]
d[3.0]
d[7.4]
d[7.4]
d[(4n 1).(4n
d[(4n 1).(4n
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Operating Modes
FLEX 10KE operate following four modes:
Normal mode Arithmetic mode Up/down counter mode Clearable counter mode
Each these modes uses resources differently. each mode, seven available inputs LE-the four data inputs from local interconnect, feedback from programmable register, carry-in cascade-in from previous LE-are directed different destinations implement desired logic function. Three inputs provide clock, clear, preset control register. Altera software, conjunction with parameterized functions such DesignWare functions, automatically chooses appropriate mode common functions such counters, adders, multipliers. required, designer also create special-purpose functions that specific operating mode optimal performance. architecture provides synchronous clock enable register four modes. Altera software DATA1 enable register synchronously, providing easy implementation fully synchronous designs.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure shows operating modes. Figure FLEX 10KE Operating Modes
Normal Mode
Carry-In data1 data2 data3 4-Input LE-Out Local Interconnect Cascade-In LE-Out FastTrack Interconnect
CLRN data4 Cascade-Out
Arithmetic Mode
Carry-In Cascade-In LE-Out data1 data2 CLRN
3-Input
3-Input Carry-Out Cascade-Out
Up/Down Counter Mode
Carry-In Cascade-In
data1 (ena) data2 (u/d) data3 (data)
3-Input
LE-Out
3-Input data4 (nload) Carry-Out Cascade-Out
CLRN
Clearable Counter Mode
Carry-In
data1 (ena) data2 (nclr) data3 (data)
3-Input
LE-Out
3-Input data4 (nload) Carry-Out Cascade-Out
CLRN
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Normal Mode normal mode suitable general logic applications wide decoding functions that take advantage cascade chain. normal mode, four data inputs from local interconnect carry-in inputs four-input LUT. Altera Compiler automatically selects carry-in DATA3 signal inputs LUT. output combined with cascade-in signal form cascade chain through cascade-out signal. Either register used drive both local interconnect FastTrack Interconnect routing structure same time. register used independently (register packing). support register packing, outputs; drives local interconnect, other drives FastTrack Interconnect routing structure. DATA4 signal drive register directly, allowing compute function that independent registered signal; three-input function computed LUT, fourth independent signal registered. Alternatively, four-input function generated, inputs this function used drive register. register packed still clock enable, clear, preset signals packed register drive FastTrack Interconnect routing structure while drives local interconnect, vice versa. Arithmetic Mode arithmetic mode offers three-input LUTs that ideal implementing adders, accumulators, comparators. computes three-input function; other generates carry output. shown Figure page first uses carry-in signal data inputs from local interconnect generate combinatorial registered output. example, adder, this output three signals: carry-in. second uses same three signals generate carry-out signal, thereby creating carry chain. arithmetic mode also supports simultaneous cascade chain. Up/Down Counter Mode up/down counter mode offers counter enable, clock enable, synchronous up/down control, data loading options. These control signals generated data inputs from local interconnect, carry-in signal, output feedback from programmable register. three-input LUTs: generates counter data, other generates fast carry bit. 2-to-1 multiplexer provides synchronous loading. Data also loaded asynchronously with clear preset register control signals without using resources.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Clearable Counter Mode clearable counter mode similar up/down counter mode, supports synchronous clear instead up/down control. clear function substituted cascade-in signal up/down counter mode. three-input LUTs: generates counter data, other generates fast carry bit. Synchronous loading provided 2-to-1 multiplexer. output this multiplexer with synchronous clear signal.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-states without limitations physical tri-state bus. physical tri-state bus, tri-state buffers' output enable (OE) signals select which signal drives bus. However, multiple signals active, contending signals driven onto bus. Conversely, signals active, will float. Internal tri-state emulation resolves contending tri-state buffers value floating buses high value, thereby eliminating these problems. Altera software automatically implements tri-state functionality with multiplexer.
Clear Preset Logic Control
Logic programmable register's clear preset functions controlled DATA3, LABCTRL1, LABCTRL2 inputs clear preset control structure asynchronously loads signals into register. Either LABCTRL1 LABCTRL2 control asynchronous clear. Alternatively, register that LABCTRL1 implements asynchronous load. data loaded driven DATA3; when LABCTRL1 asserted, DATA3 loaded into register. During compilation, Altera Compiler automatically selects best control signal implementation. Because clear preset functions active-low, Compiler automatically assigns logic high unused clear preset. clear preset logic implemented following modes chosen during design entry:
Asynchronous clear Asynchronous preset Asynchronous clear preset Asynchronous load with clear Asynchronous load with preset Asynchronous load without clear preset
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
addition clear preset modes, FLEX 10KE devices provide chip-wide reset that reset registers device. this feature during design entry. clear preset modes, chip-wide reset overrides other signals. Registers with asynchronous presets preset when chip-wide reset asserted. Inversion used implement asynchronous preset. Figure shows examples setup preset clear inputs desired functionality. Figure FLEX 10KE Clear Preset Modes
Asynchronous Clear
Chip-Wide Reset labctrl1 labctrl2 labctrl2 Chip-Wide Reset
Asynchronous Preset
Asynchronous Preset Clear
labctrl1
labctrl1 labctrl2 Chip-Wide Reset CLRN
CLRN
CLRN
Asynchronous Load with Clear
labctrl1 (Asynchronous Load) data3 (Data) labctrl2 (Clear) Chip-Wide Reset
Asynchronous Load without Clear Preset
labctrl1 (Asynchronous Load) data3 (Data)
CLRN
CLRN
Asynchronous Load with Preset
labctrl1 (Asynchronous Load) labctrl2 (Preset) data3 (Data) CLRN
Chip-Wide Reset
Chip-Wide Reset
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Asynchronous Clear flipflop cleared either LABCTRL1 LABCTRL2. this mode, preset signal tied deactivate Asynchronous Preset asynchronous preset implemented asynchronous load, with asynchronous clear. DATA3 tied VCC, asserting LABCTRL1 asynchronously loads into register. Alternatively, Altera software provide preset control using clear inverting input output register. Inversion control available inputs both IOEs. Therefore, register preset only LABCTRL signals, DATA3 input needed used operating modes. Asynchronous Preset Clear When implementing asynchronous clear preset, LABCTRL1 controls preset LABCTRL2 controls clear. DATA3 tied VCC, that asserting LABCTRL1 asynchronously loads into register, effectively presetting register. Asserting LABCTRL2 clears register. Asynchronous Load with Clear When implementing asynchronous load conjunction with clear, LABCTRL1 implements asynchronous load DATA3 controlling register preset clear. LABCTRL2 implements clear controlling register clear; LABCTRL2 does have feed preset circuits. Asynchronous Load with Preset When implementing asynchronous load conjunction with preset, Altera software provides preset control using clear inverting input output register. Asserting LABCTRL2 presets register, while asserting LABCTRL1 loads register. Altera software inverts signal that drives DATA3 account inversion register's output. Asynchronous Load without Preset Clear When implementing asynchronous load without preset clear, LABCTRL1 implements asynchronous load DATA3 controlling register preset clear.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
FastTrack Interconnect Routing Structure
FLEX 10KE architecture, connections between LEs, EABs, device pins provided FastTrack Interconnect routing structure, which series continuous horizontal vertical routing channels that traverses device. This global routing structure provides predictable performance, even complex designs. contrast, segmented routing FPGAs requires switch matrices connect variable number routing paths, increasing delays between logic resources reducing performance. FastTrack Interconnect routing structure consists column interconnect channels that span entire device. Each LABs served dedicated interconnect. interconnect drive pins feed other LABs row. column interconnect routes signals between rows drive pins. channels drive into local interconnect. signal buffered every reduce effect fan-out delay. channel driven three column channels. These four signals feed dual 4-to-1 multiplexers that connect specific channels. These multiplexers, which connected each allow column channels drive channels even when eight drive interconnect. Each column LABs EABs served dedicated column interconnect. column interconnect that serves EABs twice many channels other column interconnects. column interconnect then drive pins another row's interconnect route signals other LABs EABs device. signal from column interconnect, which either output input from pin, must routed interconnect before enter EAB. Each channel that driven drive specific column channel. Access column channels switched between adjacent pairs LABs. example, drive column channels normally driven particular adjacent same row, vice versa. This flexibility enables routing resources used more efficiently (see Figure 13).
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure FLEX 10KE Connections Column Interconnect
Column Channels
Channels
Other Columns
each intersection, channels drive column channels (1).
Each drive channels.
From Adjacent Adjacent
Each switch interconnect access with adjacent LAB.
Local Interconnect
Other Rows
Note:
EPF10K100B devices, four channels drive column channels each intersection.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
improved routing, interconnect consists combination full-length half-length channels. full-length channels connect LABs row; half-length channels connect LABs half row. driven half-length channels left half full-length channels. drives fulllength channels. addition providing predictable, row-wide interconnect, this architecture provides increased routing resources. neighboring LABs connected using half-row channel, thereby saving other half channel other half row. Table summarizes FastTrack Interconnect routing structure resources available each FLEX 10KE device. Table FLEX 10KE FastTrack Interconnect Resources Device
EPF10K30E EPF10K50E EPF10K50S EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K200S
Rows
Channels
Columns
Channels Column
addition general-purpose pins, FLEX 10KE devices have dedicated input pins that provide low-skew signal distribution across device. These inputs used global clock, clear, preset, peripheral output enable clock enable control signals. These signals available control signals LABs IOEs device. dedicated inputs also used general-purpose data inputs because they feed local interconnect each device. Figure shows interconnection adjacent LABs EABs, with row, column, local interconnects, well associated cascade carry chains. Each labeled according location: letter represents number represents column. example, column
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure FLEX 10KE Interconnect Resources
Figure details. Element (IOE)
Interconnect
Figure details.
Column Interconnect
Cascade Carry Chains
Element
contains bidirectional buffer register that used either input register external data that requires fast setup time, output register data that requires fast clock-to-output performance. some cases, using register input register will result faster setup time than using register. IOEs used input, output, bidirectional pins. bidirectional registered implementation, output register should IOE, data input output enable registers should registers placed adjacent bidirectional pin. Altera Compiler uses programmable inversion option invert signals from column interconnect automatically where appropriate. Figure shows bidirectional register.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure FLEX 10KE Bidirectional Registers
Column Interconnect Dedicated Clock Inputs
Dedicated Inputs
Peripheral Control
Register
CLRN
Chip-Wide Reset
OE[7.0]
Chip-Wide Output Enable
Programmable Delay
Output Register
CLK[1.0] CLK[3.2] ENA[5.0] CLRN[1.0] CLRN
Open-Drain Output Slew-Rate Control
Chip-Wide Reset Input Register
CLRN
Chip-Wide Reset
Note:
FLEX 10KE devices (except EPF10K50E EPF10K200E devices) have programmable input delay buffer input path.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
FLEX 10KE devices (except EPF10K50E EPF10K200E devices), input path from FastTrack Interconnect programmable delay element that used guarantee zero hold time. EPF10K50S EPF10K200S devices also support this feature. Depending placement relative what driving, designer choose turn programmable delay ensure zero hold time turn minimize setup time. This feature used reduce setup time complex pin-to-register paths (e.g., designs). Each selects clock, clear, clock enable, output enable controls from network control signals called peripheral control bus. peripheral control uses high-speed drivers minimize signal skew across device provides peripheral control signals that allocated follows:
eight output enable signals clock enable signals clock signals clear signals
more than clock enable eight output enable signals required, each device controlled clock enable output enable signals driven specific LEs. addition clock signals available peripheral control bus, each dedicated clock pins. Each peripheral control signal driven dedicated input pins first each particular row. addition, different drive column interconnect, which causes interconnect drive peripheral control signal. chipwide reset signal resets registers, overriding other control signals. When dedicated clock drives registers, inverted IOEs device. IOEs must same sense clock. example, uses inverted clock, IOEs must inverted clock non-inverted clock. However, still true complement clock LAB-by-LAB basis. incoming signal inverted dedicated clock will drive IOEs. true complement clock used drive IOEs, drive into both global clock pins. global clock will supply true, other will supply complement. When true complement dedicated input drives clocks, signals peripheral control consumed, each sense clock.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
When dedicated inputs drive non-inverted inverted peripheral clears, clock enables, output enables, signals peripheral control will used. Tables list sources each peripheral control signal, show output enable, clock enable, clock, clear signals share peripheral control signals. tables also show rows that drive global signals. Table Peripheral Sources EPF10K30E, EPF10K50E EPF10K50S Devices Peripheral Control Signal
CLKENA0/CLK0/GLOBAL0 CLKENA1/OE6/GLOBAL1 CLKENA2/CLR0 CLKENA3/OE7/GLOBAL2 CLKENA4/CLR1 CLKENA5/CLK1/GLOBAL3
EPF10K30E
EPF10K50E EPF10K50S
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table Peripheral Sources EPF10K100B, EPF10K100E, EPF10K130E, EPF10K200E EPF10K200S Devices Peripheral Control Signal
CLKENA0/CLK0/GLOBAL0 CLKENA1/OE6/GLOBAL1 CLKENA2/CLR0 CLKENA3/OE7/GLOBAL2 CLKENA4/CLR1 CLKENA5/CLK1/GLOBAL3
EPF10K100B EPF10K100E
EPF10K130E
EPF10K200E EPF10K200S
Signals peripheral control also drive four global signals, referred GLOBAL0 through GLOBAL3 Tables internally generated signal drive global signal, providing same low-skew, low-delay characteristics signal driven input pin. drives global signal driving line that drives peripheral bus, which then drives global signal. This feature ideal internally generated clear clock signals with high fan-out. However, internally driven global signals offer advantage over general-purpose interconnect routing data signals. chip-wide output enable active-low that used tri-state pins device. This option Altera software. EPF10K50E EPF10K200E devices, built-in pull-up resistors (which active during configuration) active when chip-wide output enable asserted. registers also reset chip-wide reset pin.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Row-to-IOE Connections
When used input signal, drive separate channels. signal accessible within that row. When used output, signal driven multiplexer that selects signal from channels. eight IOEs connect each side each channel (see Figure 16). Figure FLEX 10KE Row-to-IOE Connections
values provided Table
IOE1
FastTrack Interconnect
IOE8
Each driven m-to-1 multiplexer. Each drive channels.
Table lists FLEX 10KE row-to-IOE interconnect resources. Table FLEX 10KE Row-to-IOE Interconnect Resources Device
EPF10K30E EPF10K50E EPF10K50S EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K200S
Channels
Channels
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Column-to-IOE Connections
When used input, drive separate column channels. When used output, signal driven multiplexer that selects signal from column channels. IOEs connect each side column channels. Each driven column channels multiplexer. column channels different each (see Figure 17). Figure FLEX 10KE Column-to-IOE Connections
values provided Table
Each driven m-to-1 multiplexer
IOE1
Column Interconnect
IOE1
Each drive column channels.
Table lists FLEX 10KE column-to-IOE interconnect resources. Table FLEX 10KE Column-to-IOE Interconnect Resources Device
EPF10K30E EPF10K50E EPF10K50S EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K200S
Channels Column
Column Channels
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
SameFrame Pin-Outs
FLEX 10KE devices support SameFrame pin-out feature FineLine packages. SameFrame pin-out feature arrangement balls FineLine packages such that lower-ballcount packages form subset higher-ball-count packages. SameFrame pin-outs provide flexibility migrate only from device device within same package, also from package another. given printed circuit board (PCB) layout support multiple device density/package combinations. example, single board layout support range devices from EPF10K30E device 256-pin FineLine package EPF10K200S device 672-pin FineLine package. Altera software provides support design PCBs with SameFrame pin-out devices. Devices defined present future use. Altera software generates pin-outs describing board take advantage this migration (see Figure 18). Figure SameFrame Pin-Out Example
Printed Circuit Board Designed 256-Pin FineLine Package
100-Pin FineLine
256-Pin FineLine
100-Pin FineLine Package (Reduced Count Logic Requirements)
256-Pin FineLine Package (Increased Count Logic Requirements)
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
ClockLock ClockBoost Features
support high-speed designs, FLEX 10KE devices offer optional ClockLock ClockBoost circuitry containing phase-locked loop (PLL) used increase design speed reduce resource usage. ClockLock circuitry uses synchronizing that reduces clock delay skew within device. This reduction minimizes clock-to-output setup times while maintaining zero hold times. ClockBoost circuitry, which provides clock multiplier, allows designer enhance device area efficiency resource sharing within device. ClockBoost feature allows designer distribute low-speed clock multiply that clock on-device. Combined, ClockLock ClockBoost features provide significant improvements system performance bandwidth. FLEX 10KE devices, except EPF10K50E EPF10K200E devices, support ClockLock ClockBoost circuitry. EPF10K50S EPF10K200S devices support this circuitry. Devices that support ClockLock ClockBoost circuitry distinguished with suffix ordering code; instance, EPF10K200SFC672-1X device supports this circuit. ClockLock ClockBoost features FLEX 10KE devices enabled through Altera software. External devices required these features. output ClockLock ClockBoost circuits available device pins. ClockLock ClockBoost circuitry locks onto rising edge incoming clock. circuit output drive clock inputs registers only; generated clock cannot gated inverted. dedicated clock (GCLK1) supplies clock ClockLock ClockBoost circuitry. When dedicated clock driving ClockLock ClockBoost circuitry, cannot drive elsewhere device. designs that require both multiplied non-multiplied clock, clock trace board connected GCLK1 pin. Altera software, GCLK1 feed both ClockLock ClockBoost circuitry FLEX 10KE device. However, when both circuits used, other clock cannot used.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
ClockLock ClockBoost Timing Parameters
ClockLock ClockBoost circuitry function properly, incoming clock must meet certain requirements. these specifications met, circuitry lock onto incoming clock, which generates erroneous clock within device. clock generated ClockLock ClockBoost circuitry must also meet certain specifications. incoming clock meets these requirements during configuration, ClockLock ClockBoost circuitry will lock onto clock during configuration. circuit will ready immediately after configuration. Figure shows incoming generated clock specifications. Figure Specifications Incoming Generated Clocks
parameter refers nominal input clock period; parameter refers nominal output clock period.
tCLK1
Input Clock
tINDUTY
fCLKDEV
tOUTDUTY
tINCLKSTB
ClockLockGenerated Clock
tJITTER
tJITTER
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Tables summarize ClockLock ClockBoost parameters speed-grade devices, respectively. Table ClockLock ClockBoost Parameters Speed-Grade Devices Symbol
INDUTY CLK1 fCLK2 CLKDEV
Parameter
Input rise time Input fall time Input duty cycle Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Input deviation from user specification MAX+PLUS software Input clock stability (measured between adjacent clocks) Time required ClockLock ClockBoost acquire lock Jitter ClockLock ClockBoostgenerated clock Duty cycle ClockLock ClockBoost-generated clock
Condition
Unit
25,000
INCLKSTB LOCK JITTER
INCLKSTB INCLKSTB
tOUTDUTY
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table ClockLock ClockBoost Parameters Speed-Grade Devices Symbol
INDUTY CLK1 fCLK2 CLKDEV
Parameter
Input rise time Input fall time Input duty cycle Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Input deviation from user specification MAX+PLUS software Input clock stability (measured between adjacent clocks) Time required ClockLock ClockBoost acquire lock Jitter ClockLock ClockBoostgenerated clock Duty cycle ClockLock ClockBoost-generated clock
Condition
Unit
37.5 25,000
INCLKSTB LOCK JITTER
INCLKSTB INCLKSTB
tOUTDUTY
Notes tables:
implement ClockLock ClockBoost circuitry with MAX+PLUS software, designers must specify input frequency. Altera software tunes ClockLock ClockBoost circuitry this frequency. fCLKDEV parameter specifies much incoming clock differ from specified frequency during device operation. Simulation does reflect this parameter. Twenty-five thousand parts million (PPM) equates 2.5% input clock period. During device configuration, ClockLock ClockBoost circuitry configured before rest device. incoming clock supplied during configuration, ClockLock ClockBoost circuitry locks during configuration because tLOCK value less than time required configuration. tJITTER specification measured under long-term observation. maximum value tJITTER tINCLKSTB lower than
Configuration
This section discusses peripheral component interconnect (PCI) pull-up clamping diode option, slew-rate control, open-drain output option, MultiVolt interface FLEX 10KE devices. pull-up clamping diode, slew-rate control, open-drain output options controlled pin-by-pin Altera software logic options. MultiVolt interface controlled connecting VCCIO different voltage than VCCINT. effect simulated Altera software Global Project Device Options dialog (Assign menu).
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Pull-Up Clamping Diode Option
FLEX 10KE devices have pull-up clamping diode every I/O, dedicated input, dedicated clock pin. clamping diodes clamp signal VCCIO value required 3.3-V compliance. Clamping diodes also used limit overshoot other systems. Clamping diodes controlled pin-by-pin basis. When VCCIO that clamping diode option turned driven 2.5-V 3.3-V signal, 5.0-V signal. When VCCIO that clamping diode option turned driven 2.5-V signal, 3.3-V 5.0-V signal. Additionally, clamping diode activated subset pins, which would allow device bridge between 3.3-V 5.0-V device.
Slew-Rate Control
output buffer each adjustable output slew rate that configured low-noise high-speed performance. slower slew rate reduces system noise adds maximum delay fast slew rate should used speed-critical outputs systems that adequately protected against noise. Designers specify slew rate pin-by-pin assign default slew rate pins device-wide basis. slow slew rate setting affects falling edge output.
Open-Drain Output Option
FLEX 10KE devices provide optional open-drain output (electrically equivalent open-collector output) each pin. This open-drain output enables device provide system-level control signals (e.g., interrupt write enable signals) that asserted several devices. also provide additional wired-OR plane.
MultiVolt Interface
FLEX 10KE device architecture supports MultiVolt interface feature, which allows FLEX 10KE devices packages interface with systems differing supply voltages. These devices have pins internal operation input buffers (VCCINT), another output drivers (VCCIO).
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
VCCINT pins must always connected 2.5-V power supply. With 2.5-V VCCINT level, input voltages compatible with 2.5-V, 3.3-V, 5.0-V inputs. VCCIO pins connected either 2.5-V 3.3-V power supply, depending output requirements. When VCCIO pins connected 2.5-V power supply, output levels compatible with 2.5-V systems. When VCCIO pins connected 3.3-V power supply, output high therefore compatible with 3.3-V 5.0-V systems. Devices operating with VCCIO levels higher than achieve faster timing delay tOD2 instead tOD1. Table summarizes FLEX 10KE MultiVolt support. Table FLEX 10KE MultiVolt Support VCCIO
Notes:
clamping diode must disabled drive input with voltages higher than VCCIO. When VCCIO FLEX 10KE device drive 2.5-V device that 3.3-V tolerant inputs.
Input Signal
v(1)
Output Signal
v(2)
v(1) v(1)
Open-drain output pins FLEX 10KE devices (with pull-up resistor 5.0-V supply) drive 5.0-V CMOS input pins that require When open-drain active, will drive low. When inactive, trace will pulled resistor. opendrain will only drive tri-state; will never drive high. rise time dependent value pull-up resistor load impedance. current specification should considered when selecting pull-up resistor.
Power Sequencing Hot-Socketing
Because FLEX 10KE devices used mixed-voltage environment, they have been designed specifically tolerate possible power-up sequence. VCCIO VCCINT power planes powered order. Signals driven into FLEX 10KE devices before during power without damaging device. Additionally, FLEX 10KE devices drive during power Once operating conditions reached, FLEX 10KE devices operate specified user.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
FLEX 10KE devices provide JTAG circuitry that complies with IEEE Std. 1149.1-1990 specification. FLEX 10KE devices also configured using JTAG pins through BitBlaster ByteBlasterMV download cable, hardware that uses JamSTAPL programming test language. JTAG boundary-scan testing performed before after configuration, during configuration. FLEX 10KE devices support JTAG instructions shown Table
Table FLEX 10KE JTAG Instructions JTAG Instruction
SAMPLE/PRELOAD
Description
Allows snapshot signals device pins captured examined during normal device operation, permits initial data pattern output device pins. Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins. Places 1-bit bypass register between pins, which allows data pass synchronously through selected device adjacent devices during normal device operation. Selects user electronic signature (USERCODE) register places between pins, allowing USERCODE serially shifted TDO. Selects IDCODE register places between TDO, allowing IDCODE serially shifted TDO. These instructions used when configuring FLEX 10KE device JTAG ports with BitBlaster ByteBlasterMV download cable, using File (.jam) Byte-Code File (.jbc) embedded processor.
EXTEST BYPASS
USERCODE IDCODE Instructions
instruction register length FLEX 10KE devices bits. USERCODE register length FLEX 10KE devices bits; bits determined user, bits pre-determined. Tables show boundary-scan register length device IDCODE information FLEX 10KE devices. Table FLEX 10KE Boundary-Scan Register Length Device
EPF10K30E EPF10K50E EPF10K50S EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K200S
Boundary-Scan Register Length
1,050 1,308 1,446
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table 32-Bit IDCODE FLEX 10KE Devices Device Version Bits)
EPF10K30E EPF10K50E EPF10K50S EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K200S Notes:
Note
IDCODE Bits) Part Number Bits)
0001 0000 0011 0000 0001 0000 0101 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0011 0000 0000 0010 0000 0000
Manufacturer's Bit) Identity Bits)
00001101110 00001101110 00001101110 00001101110 00001101110 00001101110
0001 0001 0001 0010 0001 0001
most significant (MSB) left. least significant (LSB) JTAG IDCODEs
FLEX 10KE devices include weak pull-up resistors JTAG pins.
more information, following documents:
Application Note (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) BitBlaster Serial Download Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet Programming Test Language Specification
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure shows timing requirements JTAG signals. Figure FLEX 10KE JTAG Waveforms
tJPZX tJSSU Signal Captured Signal Driven tJSH JPCO JPXZ JPSU
tJSZX
tJSCO
tJSXZ
Table shows timing parameters values FLEX 10KE devices. Table FLEX 10KE JTAG Timing Parameters Values Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock output Update register high impedance valid output Update register valid output high impedance
Parameter
Unit
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Generic Testing
Each FLEX 10KE device functionally tested. Complete testing each configurable static random access memory (SRAM) logic functionality ensures 100% yield. test measurements FLEX 10KE devices made under conditions equivalent those shown Figure Multiple test patterns used configure devices during stages production flow. Figure FLEX 10KE Test Conditions
Power supply transients affect measurements. Simultaneous transitions multiple outputs should avoided accurate measurement. Threshold tests [481 must performed under Device conditions. Large-amplitude, fastOutput ground-current transients normally occur device outputs discharge load capacitances. When these 8.06 transients flow through parasitic [481 inductance between device ground Device input test system ground, rise fall significant reductions observable times noise immunity result. Numbers brackets 2.5-V devices outputs. Numbers without brackets 3.3-V.
VCCIO
Test System
(includes capacitance)
Operating Conditions
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, capacitance 2.5-V FLEX 10KE devices. Note
-0.5 -0.5 -2.0 bias Under bias PQFP, TQFP, FineLine packages, under bias Ceramic packages, under bias
Table FLEX 10KE 2.5-V Device Absolute Maximum Ratings Symbol
CCINT CCIO input voltage output current, Storage temperature Ambient temperature Junction temperature
Parameter
Supply voltage
Conditions
With respect ground
5.75
Unit
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table 2.5-V EPF10K50E EPF10K200E Device Recommended Operating Conditions Symbol
CCINT CCIO
Parameter
Supply voltage internal logic input buffers
Conditions
(3),
2.30 (2.30) 3.00 (3.00) 2.30 (2.30) -0.5
2.70 (2.70) 3.60 (3.60) 2.70 (2.70) 5.75 CCIO
Unit
Supply voltage output buffers, (3), 3.3-V operation Supply voltage output buffers, (3), 2.5-V operation
Input voltage Output voltage Ambient temperature Operating temperature Input rise time Input fall time
commercial industrial commercial industrial
Table 2.5-V EPF10K30E, EPF10K50S, EPF10K100E, EPF10K130E EPF10K200S Device Recommended Operating Conditions Symbol
CCINT CCIO
Parameter
Supply voltage internal logic input buffers
Conditions
(3),
2.375 (2.375) 3.00 (3.00) 2.375 (2.375) -0.5
2.625 (2.625) 3.60 (3.60) 2.625 (2.625) 5.75 CCIO
Unit
Supply voltage output buffers, (3), 3.3-V operation Supply voltage output buffers, (3), 2.5-V operation
Input voltage Output voltage Ambient temperature Operating temperature Input rise time Input fall time
commercial industrial commercial industrial
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table FLEX 10KE 2.5-V Device Operating Conditions Symbol
Notes (6),
5.75 0.8, VCCIO
Parameter
High-level input voltage Low-level input voltage 3.3-V high-level output voltage 3.3-V high-level CMOS output voltage 3.3-V high-level output voltage 2.5-V high-level output voltage
Conditions
Unit
1.7, VCCIO -0.5 CCIO 3.00 -0.1 CCIO 3.00 -0.5 CCIO 3.00 3.60 -0.1 CCIO 2.30 CCIO 2.30 CCIO 2.30 CCIO VCCIO
0.45 VCCIO
3.3-V low-level output voltage 3.3-V low-level CMOS output voltage 3.3-V low-level output voltage 2.5-V low-level output voltage
CCIO 3.00 (10) CCIO 3.00 (10) CCIO 3.00 3.60 (10) CCIO 2.30 (10) CCIO 2.30 (10) CCIO 2.30 (10)
Input leakage current Tri-stated leakage current supply current (standby)
-0.5 -0.5 ground, load, toggling inputs ground, load, toggling inputs (11)
CONF
Value pull-up resistor before during configuration
CCIO (12) CCIO (12)
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table FLEX 10KE Device Capacitance Symbol
CINCLK COUT
Note (13) Conditions
Parameter
Input capacitance Input capacitance dedicated clock Output capacitance
Unit
VOUT
Notes tables:
Operating Requirements Altera Devices Data Sheet. Minimum input voltage -0.5 During transitions, inputs undershoot -2.0 input currents less than periods shorter than Numbers parentheses industrial-temperature-range devices. Maximum rise time must rise monotonically. pins, including dedicated inputs, clock, I/O, JTAG pins, driven before VCCINT VCCIO powered. Typical values CCINT CCIO These values specified under FLEX 10KE Recommended Operating Conditions shown Tables FLEX 10KE input buffers compatible with 2.5-V, 3.3-V (LVTTL LVCMOS), 5.0-V CMOS signals. Additionally, input buffers 3.3-V compliant when VCCIO VCCINT meet relationship shown Figure parameter refers high-level TTL, PCI, CMOS output current. parameter refers low-level TTL, PCI, CMOS output current. This parameter applies open-drain pins well output pins. This parameter applies speed grade commercial temperature devices speed grade industrial temperature devices. pull-up resistance values will lower driven higher than VCCIO external source. Capacitance sample-tested only.
(10) (11) (12) (13)
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure shows required relationship between VCCIO VCCINT 3.3-V compliance. Figure Relationship between VCCIO VCCINT 3.3-V Compliance
CCINT
PCI-Compliant Region
VCCIO
Figure shows typical output drive characteristics FLEX 10KE devices with 3.3-V 2.5-V VCCIO. output driver compliant 3.3-V Local Specification, Revision (when VCCIO pins connected FLEX 10KE devices with speed grade also comply with drive strength requirements Local Specification, Revision (when VCCINT pins powered with minimum supply 2.375 VCCIO pins connected Therefore, these devices used open 5.0-V systems.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure Output Drive Characteristics FLEX 10KE Devices
Typical Output Current (mA)
VCCINT VCCIO Room Temperature
Typical Output Current (mA)
VCCINT VCCIO Room Temperature
Output Voltage
Output Voltage
Timing Model
continuous, high-performance FastTrack Interconnect routing resources ensure predictable performance accurate simulation timing analysis. This predictable performance contrasts with that FPGAs, which segmented connection scheme therefore have unpredictable performance. Device performance estimated following signal path from source, through interconnect, destination. example, registered performance between same calculated adding following parameters:
register clock-to-output delay (tCO) Interconnect delay (tSAMEROW) look-up table delay (tLUT) register setup time (tSU)
routing delay depends placement source destination LEs. more complex registered path involve multiple combinatorial between source destination LEs. Timing simulation delay prediction available with Altera Simulator Timing Analyzer, with industry-standard tools. Simulator offers both pre-synthesis functional simulation evaluate logic design accuracy post-synthesis timing simulation with 0.1-ns resolution. Timing Analyzer provides point-to-point timing delay information, setup hold time analysis, device-wide performance analysis.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure shows overall timing model, which maps possible paths from various elements FLEX 10KE device. Figure FLEX 10KE Device Timing Model
Dedicated Clock/Input Interconnect Element
Logic Element
Embedded Array Block
Figures through show delays that correspond various paths functions within IOE, EAB, bidirectional timing models. Figure FLEX 10KE Device Timing Model
Carry-In Cascade-In
Delay Data-In
Register Delays
tLUT tRLUT tCLUT
Packed Register Delay tPACKED Register Control Delay
tCOMB tPRE tCLR
Data-Out
Control-In
Carry Chain Delay tCGENR
tCGEN tCICO tLABCARRY
tCASC
tLABCASC
Carry-Out
Cascade-Out
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure FLEX 10KE Device Timing Model
Output Data Delay Data-In Register Delays Output Delays
tIOD
Element Contol Delay Clock Enable Clear Clock Output Enable
tIOCO tIOCOMB tIOSU tIOH tIOCLR
tIOC tINREG
Input Register Delay Register Feedback Delay
tOD1 tOD2 tOD3 tZX1 tZX2 tZX3
Data Feedback into FastTrack Interconnect
tIOFD
Input Delay
tINCOMB
Figure FLEX 10KE Device Timing Model
Data Input Delays Data-In Address Input Register Delays RAM/ROM Block Delays Output Register Delays Output Delay
tEABDATA1 tEABDATA2
Write Enable Input Delays
tEABWE1 tEABWE2
Clock Delay
tEABCO tEABBYPASS tEABSU tEABH tEABCH tEABCL
Input Register Clock Output Register Clock
tWDSU tWDH tWASU tWAH tRASU tRAH
tEABCO tEABBYPASS tEABSU tEABH tEABCH tEABCL
tEABOUT
Data-Out
tEABCLK
Read Enable Input Delays
tEABRE1 tEABRE2
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure Synchronous Bidirectional External Timing Model
Register
Dedicated Clock
tXZBIDIR tZXBIDIR tOUTCOBIDIR
CLRN Output Register Bidirectional
CLRN
tINSUBIDIR tINHBIDIR
Input Register
CLRN
Tables through describe FLEX 10KE device internal timing parameters. Tables through describe FLEX 10KE external timing parameters their symbols. Detailed timing information these devices will released available. Table Timing Microparameters (Part Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC tCOMB tPRE delay data-in delay carry-in delay register feedback Data-in packed register delay register enable delay Carry-in carry-out delay Data-in carry-out delay register feedback carry-out delay Cascade-in cascade-out delay register control signal delay register clock-to-output delay Combinatorial delay register setup time data enable signals before clock; register recovery time after asynchronous clear, preset, load register hold time data enable signals after clock register preset delay
Note Condition
Parameter
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table Timing Microparameters (Part Symbol
tCLR register clear delay Minimum clock high time from clock Minimum clock time from clock
Note Condition
Parameter
Table Timing Microparameters Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB data delay
Note Parameter Conditions
register control signal delay register clock-to-output delay combinatorial delay register setup time data enable signals before clock; register recovery time after asynchronous clear register hold time data enable signals after clock register clear time Output buffer delay, slow slew rate off, VCCIO Output buffer delay, slow slew rate off, VCCIO Output buffer delay, slow slew rate output buffer disable delay output buffer enable delay, slow slew rate off, VCCIO output buffer enable delay, slow slew rate off, VCCIO output buffer enable delay, slow slew rate input buffer register delay register feedback delay input buffer FastTrack Interconnect delay
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table Timing Microparameters Symbol
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tWDSU tWDH tWASU tWAH tRASU tRAH tEABOUT tEABCH tEABCL
Note Parameter Conditions
Data address delay combinatorial input Data address delay registered input Write enable delay combinatorial input Write enable delay registered input Read enable delay combinatorial input Read enable delay registered input register clock delay register clock-to-output delay Bypass register delay register setup time before clock register hold time after clock register asynchronous clear time output delay Address access delay (including read enable output delay) Write pulse width Read pulse width Data setup time before falling edge write pulse Data hold time after falling edge write pulse Address setup time before rising edge write pulse Address hold time after falling edge write pulse Address setup time with respect falling edge read enable Address hold time with respect falling edge read enable Write enable data output valid delay Data-in data-out valid delay Data-out delay Clock high time Clock time
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table Timing Macroparameters Symbol
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO address access delay
Note (1), Parameter Conditions
asynchronous read cycle time synchronous read cycle time write pulse width asynchronous write cycle time synchronous write cycle time data-in data-out valid delay clock-to-output delay when using output registers data/address setup time before clock when using input register data/address hold time after clock when using input register setup time before clock when using input register hold time after clock when using input register data setup time before falling edge write pulse when using input registers data hold time after falling edge write pulse when using input registers address setup time before rising edge write pulse when using input registers address hold time after falling edge write pulse when using input registers write enable data output valid delay
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table Interconnect Timing Microparameters Symbol
tDIN2IOE tDIN2LE tDCLK2IOE tDCLK2LE tDIN2DATA tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note Conditions
Parameter
Delay from dedicated input control input Delay from dedicated input control input Delay from dedicated clock clock Delay from dedicated clock clock Delay from dedicated input clock data Routing delay driving another same Routing delay IOE, driving IOE, same Routing delay driving same column Routing delay column IOE, driving different Routing delay driving different Routing delay driving control signal peripheral control Routing delay carry-out signal driving carry-in signal different different Routing delay cascade-out signal driving cascade-in signal different different
Table External Timing Parameters Symbol
tDRR tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Note Parameter Conditions
Register-to-register delay four LEs, three interconnects, four local interconnects Setup time with global clock register Hold time with global clock register Clock-to-output delay with global clock register Setup time with global clock registers used designs Hold time with global clock registers used designs Clock-to-output delay with global clock registers used designs
(8),(10) (8),(10) (8),(10)
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tINH tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes tables:
Note Conditions
Parameter
Setup time bi-directional pins with global clock same-row samecolumn register Hold time bidirectional pins with global clock same-row same-column register Hold time with global clock register Clock-to-output delay bidirectional pins with global clock register Synchronous output buffer disable delay Synchronous output buffer enable delay, slow slew rate=
Microparameters timing delays contributed individual architectural elements. These parameters cannot measured explicitly. Operating conditions: VCCIO commercial industrial use. Operating conditions: VCCIO commercial industrial EPF10K30E, EPF10K50S, EPF10K100E, EPF10K130E, EPF10K200S devices. Operating conditions: VCCIO Because self-timed, this parameter ignored when signal registered. macroparameters internal parameters that simplify predicting behavior boundary; these parameters calculated summing selected microparameters. These parameters worst-case values typical applications. Post-compilation timing simulation timing analysis required determine actual worst-case performance. This timing parameters sample-tested only. Contact Altera Applications test circuit specifications test conditions. (10) This parameter measured with measurement test conditions, including load, specified Local Specification, revision 2.2.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figures show asynchronous synchronous timing waveforms, respectively, macroparameters Tables Figure Asynchronous Timing Waveforms
Asynchronous Read
Address
tEABAA
tEABRCCOMB
Data-Out
Asynchronous Write
tEABWP tEABWDSU tEABWDH
Data-In
din0
tEABWASU tEABWCCOMB
din1
tEABWAH
Address
tEABDD
Data-Out
din0
din1
dout2
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure Synchrounous Timing Waveforms
Synchronous Read
Address
tEABDATASU
tEABDATAH
tEABRCREG
tEABDATACO
Data-Out
Synchronous Write (EAB Output Registers Used)
Data-In
din1
din2
din3
Address
tEABWESU tEABDATASU
tEABDATAH
tEABWEH
tEABWCREG tEABDATACO
Data-Out
dout0
dout1
din1
din2
din3
din2
Tables through show EPF10K30E device internal external timing parameters. Table EPF10K30E Device Timing Microparameters (Part Symbol
tLUT tCLUT tRLUT tPACKED
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K30E Device Timing Microparameters (Part Symbol
tCICO tCGEN tCGENR tCASC tCOMB tPRE tCLR
Note Unit
Speed Grade
Table EPF10K30E Device Timing Microparameters (Part Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG Altera Corporation
Note Unit
Speed Grade
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K30E Device Timing Microparameters (Part Symbol
tIOFD tINCOMB
Note Unit
Speed Grade
Table EPF10K30E Device Internal Microparameters Symbol
tEABDATA1 tEABDATA1 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tWDSU tWDH tWASU tWAH tRASU tRAH tEABOUT tEABCH tEABCL
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K30E Device Internal Timing Macroparameters Symbol
tEABAA tEABRCOMB tEABRCREG tEABWP tEABWCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K30E Device Interconnect Timing Microparameters Symbol
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note Unit
Speed Grade
Table EPF10K30E External Timing Parameters Symbol
tDRR tINSU tINH tOUTCO tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Notes (1), Unit
Speed Grade
12.5
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K30E External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes tables:
Notes (1), Unit
Speed Grade
timing parameters described Tables through this data sheet. These parameters specified characterization. This parameter measured without ClockLock ClockBoost circuits. This parameter measured with ClockLock ClockBoost circuits.
Tables through show EPF10K50E device internal external timing parameters. Table EPF10K50E Device Timing Microparameters (Part Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K50E Device Timing Microparameters (Part Symbol
tCOMB tPRE tCLR
Note Unit
Speed Grade
Table EPF10K50E Device Timing Microparameters Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K50E Device Internal Microparameters Symbol
tEABDATA1 tEABDATA1 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tWDSU tWDH tWASU tWAH tRASU tRAH tEABOUT tEABCH tEABCL
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K50E Device Internal Timing Macroparameters Symbol
tEABAA tEABRCOMB tEABRCREG tEABWP tEABWCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note Unit
Speed Grade
10.2 10.6
10.2
Table EPF10K50E Device Interconnect Timing Microparameters (Part Symbol
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K50E Device Interconnect Timing Microparameters (Part Symbol
tLEPERIPH tLABCARRY tLABCASC
Note Unit
Speed Grade
Table EPF10K50E External Timing Parameters Symbol
tDRR tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Notes (1), Unit
10.0
Speed Grade
13.5
Table EPF10K50E External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes tables:
Notes (1), Unit
Speed Grade
10.1 10.1
timing parameters described Tables through this data sheet. These parameters specified characterization.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Tables through show EPF10K100E device internal external timing parameters. Table EPF10K100E Device Timing Microparameters Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC tCOMB tPRE tCLR
Note Unit
Speed Grade
Table EPF10K100E Device Timing Microparameters (Part Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K100E Device Timing Microparameters (Part Symbol
tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Note Unit
Speed Grade
Table EPF10K100E Device Internal Microparameters (Part Symbol
tEABDATA1 tEABDATA1 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tWDSU tWDH
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K100E Device Internal Microparameters (Part Symbol
tWASU tWAH tRASU tRAH tEABOUT tEABCH tEABCL
Note Unit
Speed Grade
Table EPF10K100E Device Internal Timing Macroparameters Symbol
tEABAA tEABRCOMB tEABRCREG tEABWP tEABWCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note Unit
Speed Grade
10.3
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K100E Device Interconnect Timing Microparameters Symbol
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note Unit
Speed Grade
Table EPF10K100E External Timing Parameters Symbol
tDRR tINSU tINH tOUTCO tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Notes (1), Unit
12.0
Speed Grade
16.0
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K100E External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes tables:
Notes (1), Unit
Speed Grade
10.1 10.1
timing parameters described Tables through this data sheet. These parameters specified characterization. This parameter measured without ClockLock ClockBoost circuits. This parameter measured with ClockLock ClockBoost circuits.
Tables through show EPF10K130E device internal external timing parameters. Table EPF10K130E Device Timing Microparameters (Part Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K130E Device Timing Microparameters (Part Symbol
tCOMB tPRE tCLR
Note Unit
Speed Grade
Table EPF10K130E Device Timing Microparameters Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K130E Device Internal Microparameters Symbol
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tWDSU tWDH tWASU tWAH tRASU tRAH tEABOUT tEABCH tEABCL
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K130E Device Internal Timing Macroparameters Symbol
tEABAA tEABRCOMB tEABRCREG tEABWP tEABWCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note Unit
Speed Grade
10.3
Table EPF10K130E Device Interconnect Timing Microparameters (Part Symbol
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH Altera Corporation
Note Unit
Speed Grade
14.6
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K130E Device Interconnect Timing Microparameters (Part Symbol
tLABCARRY tLABCASC
Note Unit
Speed Grade
Table EPF10K130E External Timing Parameters Symbol
tDRR tINSU tINH tOUTCO tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Notes (1), Unit
12.0
Speed Grade
16.0
Table EPF10K130E External Bidirectional Timing Parameters (Part Symbol
tINSUBIDIR tINHBIDIR tINSUBIDIR tINHBIDIR tOUTCOBIDIR tZXBIDIR tXZBIDIR tOUTCOBIDIR
Notes (1), Unit
Speed Grade
10.8 10.8
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K130E External Bidirectional Timing Parameters (Part Symbol
tXZBIDIR tZXBIDIR Notes tables:
timing parameters described Tables through this data sheet. These parameters specified characterization. This parameter measured without ClockLock ClockBoost circuits. This parameter measured with ClockLock ClockBoost circuits.
Notes (1), Unit
Speed Grade
Tables through show EPF10K200E device internal external timing parameters. Table EPF10K200E Device Timing Microparameters Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC tCOMB tPRE tCLR
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K200E Device Timing Microparameters Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Note Unit
Speed Grade
10.1
Table EPF10K200E Device Internal Microparameters (Part Symbol
tEABDATA1 tEABDATA1 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K200E Device Internal Microparameters (Part Symbol
tEABH tEABCLR tWDSU tWDH tWASU tWAH tRASU tRAH tEABOUT tEABCH tEABCL
Note Unit
Speed Grade
Table EPF10K200E Device Internal Timing Macroparameters (Part Symbol
tEABAA tEABRCOMB tEABRCREG tEABWP tEABWCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU
Note Unit
Speed Grade
10.7 10.6
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K200E Device Internal Timing Macroparameters (Part Symbol
tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note Unit
Speed Grade
Table EPF10K200E Device Interconnect Timing Microparameters Symbol
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note Unit
Speed Grade
11.3
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K200E External Timing Parameters Symbol
tDRR tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Notes (1), Unit
12.0
Speed Grade
10.0
16.0
Table EPF10K200E External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes tables:
Notes (1), Unit
Speed Grade
13.0 13.0
timing parameters described Tables through this data sheet. These parameters specified characterization.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Tables through show EPF10K100B device internal external timing parameters. Table EPF10K100B Device Timing Microparameters Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC tCOMB tPRE tCLR
Note Unit
Speed Grade
Table EPF10K100B Device Timing Microparameters (Part Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K100B Device Timing Microparameters (Part Symbol
tIOCLR tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Note Unit
Speed Grade
Table EPF10K100B Device Internal Microparameters (Part Symbol
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tWDSU tWDH tWASU tWAH
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K100B Device Internal Microparameters (Part Symbol
tEABOUT tEABCH tEABCL
Note Unit
Speed Grade
Table EPF10K100B Device Internal Timing Macroparameters Symbol
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note Unit
Speed Grade
11.2
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K100B Device Interconnect Timing Microparameters Symbol
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note Unit
Speed Grade
Table EPF10K100B External Timing Parameters Symbol
tDRR tINSU tINH tOUTCO
Note Unit
12.0
Speed Grade
11.0
14.5
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K100B External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes tables:
timing parameters described Tables through These parameters specified characterization.
Notes (1), Unit
Speed Grade
10.6 10.6
Tables through show EPF10K50S EPF10K200S device external timing parameters. Table EPF10K50S Device Timing Microparameters (Part Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC tCOMB tPRE tCLR
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K50S Device Timing Microparameters (Part Symbol
Note Unit
Speed Grade
Table EPF10K50S Device Timing Microparameters Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K50S Device Internal Microparameters Symbol
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tWDSU tWDH tWASU tWAH tRASU tRAH tEABOUT tEABCH tEABCL
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K50S Device Internal Timing Macroparameters Symbol
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note Unit
Speed Grade
10.6
Table EPF10K50S Device Interconnect Timing Microparameters (Part Symbol
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K50S Device Interconnect Timing Microparameters (Part Symbol
tLEPERIPH tLABCARRY tLABCASC
Note Unit
Speed Grade
Table EPF10K50S External Timing Parameters Symbol
tDRR tINSU tINH tOUTCO tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Note Unit
Speed Grade
12.5
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K50S External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes tables:
Note Unit
Speed Grade
10.1 10.1
timing parameters described Tables through This parameter measured without ClockLock ClockBoost circuits. This parameter measured with ClockLock ClockBoost circuits
Table EPF10K200S Device Internal External Timing Parameters (Part Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC tCOMB Altera Corporation
Note Unit
Speed Grade
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K200S Device Internal External Timing Parameters (Part Symbol
tPRE tCLR
Note Unit
Speed Grade
Table EPF10K200S Device Timing Microparameters Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Note Unit
Speed Grade
10.1
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K200S Device Internal Microparameters Symbol
tEABDATA1 tEABDATA1 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tWDSU tWDH tWASU tWAH tRASU tRAH tEABOUT tEABCH tEABCL
Note Unit
Speed Grade
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K200S Device Internal Timing Macroparameters Symbol
tEABAA tEABRCOMB tEABRCREG tEABWP tEABWCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note Unit
Speed Grade
10.7 10.6
Table EPF10K200S Device Interconnect Timing Microparameters (Part Symbol
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS
Note Unit
Speed Grade
14.1
12.1 17.8
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K200S Device Interconnect Timing Microparameters (Part Symbol
tLEPERIPH tLABCARRY tLABCASC
Note Unit
Speed Grade
Table EPF10K200S External Timing Parameters Symbol
tDRR tINSU tINH tOUTCO tINSU(3) tINH tOUTCO(3) tPCISU tPCIH tPCICO
Note Unit
12.0
Speed Grade
16.0
Table EPF10K200S External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINSUBIDIR tINHBIDIR tINHBIDIR tOUTCOBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Altera Corporation
Note Unit
Speed Grade
FLEX 10KE Embedded Programmable Logic Devices
Table EPF10K200S Application Performance Feature
16-bit loadable counter 16-bit accumulator 16-to-1 multiplier read cycle speed write cycle speed 32-bit counter Notes tables:
timing parameters described Tables through this data sheet. This parameter measured without ClockLock ClockBoost circuits. This parameter measured with ClockLock ClockBoost circuits.
Speed Grade
166.7 166.7
Power Consumption
supply power FLEX 10KE devices calculated with following equation: PINT CCSTANDBY ICCACTIVE) ICCACTIVE value depends switching frequency application logic. This value calculated based amount current that each typically consumes. value, which depends device output load characteristics switching frequency, calculated using guidelines given Application Note (Evaluating Power Altera Devices). Compared rest device, embedded array consumes negligible amount power. Therefore, embedded array ignored when calculating supply current. ICCACTIVE value calculated with following equation: ICCACTIVE fMAX togLC -MHz Where: fMAX togLC Maximum operating frequency Total number used device Average percent toggling each clock (typically 12.5%) Constant
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table provides constant values FLEX 10KE devices. Table FLEX 10KE Constant Values Device
EPF10K30E EPF10K50E EPF10K50S EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K200S
Value
This calculation provides estimate based typical conditions with output load. actual should verified during operation because this measurement sensitive actual pattern device environmental operating conditions. better reflect actual designs, power model (and constant power calculation equations) continuous interconnect FLEX devices assumes that drive FastTrack Interconnect channels. contrast, power model segmented FPGAs assumes that drive only short interconnect segment. This assumption lead inaccurate results when compared measured power consumption actual designs segmented FPGAs. Figure shows relationship between current operating frequency FLEX 10KE devices.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure FLEX 10KE ICCACTIVE Operating Frequency (Part
EPF10K30E
EPF10K50E
Supply
Current (mA)
Supply Current (mA)
Frequency (MHz)
Frequency (MHz)
EPF10K50S
EPF10K100E
Supply
Supply
Current (mA)
Current (mA)
Frequency (MHz)
Frequency (MHz) EPF10K130E
EPF10K100B
Supply
Supply
Current (mA)
Current (mA)
Frequency (MHz)
Frequency (MHz)
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Figure FLEX 10KE ICCACTIVE Operating Frequency (Part
EPF10K200E
EPF10K200S
Supply
Supply
Current (mA)
Current (mA)
Frequency (MHz)
Frequency (MHz)
Configuration Operation
FLEX 10KE architecture supports several configuration schemes. This section summarizes device operating modes available device configuration schemes.
Operating Modes
FLEX 10KE architecture uses SRAM configuration elements that require configuration data loaded every time circuit powers process physically loading SRAM data into device called configuration. Before configuration, rises, device initiates Power-On Reset (POR). This event clears device prepares configuration. FLEX 10KE time does exceed When configuring with configuration device, refer respective configuration device data sheet timing information. During initialization, which occurs immediately after configuration, device resets registers, enables pins, begins operate logic device. pins tri-stated during power-up, before during configuration. Together, configuration initialization processes called command mode; normal device operation called user mode. SRAM configuration elements allow FLEX 10KE devices reconfigured in-circuit loading configuration data into device. Real-time reconfiguration performed forcing device into command mode with device pin, loading different configuration data, reinitializing device, resuming user-mode operation. entire reconfiguration process requires less than used reconfigure entire system dynamically. In-field upgrades performed distributing configuration files.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Before during configuration, pins (except dedicated inputs, clock, configuration pins) pulled high weak pull-up resistor.
Programming Files
Despite being function- pin-compatible, FLEX 10KE devices programming- configuration file-compatible with FLEX FLEX 10KA devices. design therefore must recompiled before transferred from FLEX FLEX 10KA device equivalent FLEX 10KE device. This recompilation should performed both create programming configuration file check design timing FLEX 10KE devices, which different timing characteristics than FLEX FLEX 10KA devices. FLEX 10KE devices generally pin-compatible with equivalent FLEX 10KA devices. some cases, FLEX 10KE devices have fewer pins than equivalent FLEX 10KA devices. Table shows which FLEX 10KE devices have fewer pins than equivalent FLEX 10KA devices. However, power, ground, JTAG, configuration pins same FLEX 10KA FLEX 10KE devices, enabling migration from FLEX 10KA design FLEX 10KE design. Additionally, Altera software offers several features that help plan future device migration preventing conflicting pins. Table Counts FLEX 10KA FLEX 10KE Devices FLEX 10KA Device
EPF10K30AF256 EPF10K30AF484 EPF10K50VB356 EPF10K50VF484 EPF10K50VF484 EPF10K100AF484
FLEX 10KE Count
Device
EPF10K30EF256 EPF10K30EF484 EPF10K50SB356 EPF10K50EF484 EPF10K50SF484 EPF10K100EF484
Count
Configuration Schemes
configuration data FLEX 10KE device loaded with five configuration schemes (see Table 90), chosen basis target application. EPC2, EPC1, EPC4, EPC16, EPC1441 configuration device, intelligent controller, JTAG port used control configuration FLEX 10KE device, allowing automatic configuration system power-up.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Multiple FLEX 10KE devices configured five configuration schemes connecting configuration enable (nCE) configuration enable output (nCEO) pins each device. Additional FLEX 10K, FLEX 10KA, FLEX 10KE, FLEX 6000 devices configured same serial chain. Table Data Sources FLEX 10KE Configuration Configuration Scheme
Configuration device Passive serial (PS) Passive parallel asynchronous (PPA) Passive parallel synchronous (PPS) JTAG
Data Source
EPC1, EPC2, EPC4, EPC16, EPC1441 configuration device BitBlaster ByteBlasterMV download cables, serial data source Parallel data source Parallel data source BitBlaster ByteBlasterMV download cables, microprocessor with File File
Device Pin-Outs
Tables shows dedicated pin-outs FLEX 10KE devices 144-pin TQFP, 208-pin PQFP, 240-pin PQFP, 356-pin BGA, 599-pin PGA, 600-pin packages. Note
240-Pin PQFP (2), EPF10K50E EPF10K50S EPF10K100E EPF10K100B
Table FLEX 10KE Device Pin-Outs (Part
Name 144-Pin TQFP EPF10K30E EPF10K50E EPF10K50S 208-Pin PQFP EPF10K30E EPF10K50E EPF10K50S EPF10K100E EPF10K100B
240-Pin PQFP EPF10K130E
240-Pin RQFP EPF10K200S
MSEL0 MSEL1 nSTATUS nCONFIG DCLK CONF_DONE INIT_DONE nCEO
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table FLEX 10KE Device Pin-Outs (Part
Name 144-Pin TQFP EPF10K30E EPF10K50E EPF10K50S 208-Pin PQFP EPF10K30E EPF10K50E EPF10K50S EPF10K100E EPF10K100B
Note
240-Pin PQFP (2), EPF10K50E EPF10K50S EPF10K100E EPF10K100B
240-Pin PQFP EPF10K130E
240-Pin RQFP EPF10K200S
RDYnBUSY CLKUSR DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 (4), TRST Dedicated Inputs Dedicated Clock Pins GCLK1 Lock (10) DEV_CLRn DEV_OE VCCINT (2.5
124, 182, 210, 210, 210,
106, 109, 117, 122, 130, 150, 137, 145, 115, 110, 118, 112, 140, 160, 138, 146, 165, 189, 205, 178, (12) (12)
122, 130, 122, 130, 150, 159, 139, 150, 159, 170, 187, 112, 140, 160, 189, 205, 112, 140, 160, 189, 205,
VCCIO (2.5
VCC_CKLK (11)
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table FLEX 10KE Device Pin-Outs (Part
Name 144-Pin TQFP EPF10K30E EPF10K50E EPF10K50S 208-Pin PQFP EPF10K30E EPF10K50E EPF10K50S EPF10K100E EPF10K100B
123, 124, 129, 130, 151, 152, 171, 185, 188, (13)
Note
240-Pin PQFP (2), EPF10K50E EPF10K50S EPF10K100E EPF10K100B
104, 125, 135, 145, 155, 165, 176, 197, 216, (13)
240-Pin PQFP EPF10K130E
240-Pin RQFP EPF10K200S
GNDINT
103, 104, 127, 129,
104, 125, 135, 145, 155, 165, 176, 197, 216,
104, 125, 135, 145, 155, 165, 176, 197, 216,
GNDIO GND_CKLK (11)
Total User Pins (14)
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table FLEX 10KE Device Pin-Outs (Part
Name 356-Pin EPF10K50S 356-Pin EPF10K100E EPF10K130E EPF10K200S
AC24 AC22 AE24 AE23 AD24 AD23 AA24 AC23 AD25
Note
599-Pin EPF10K200E EPF10K200S
BC43 AM40 BF44 BB40 BA37 AY38 BA39 AW47 AY42 BD14 BA17 BB16 BF12 BG11 BF10 BB42 BE43
600-Pin EPF10K130E
600-Pin EPF10K200E EPF10K200S
AM32 AE32 AP35 AR29 AM28 AL29 AN29 AG35 AM34 AM13 AR12 AN12 AP11 AM11 AR10 AN10 AN34 AL31 C18, D18, AM18, AN18 AL18,
MSEL0 MSEL1 nSTATUS nCONFIG DCLK CONF_DONE INIT_DONE nCEO RDYnBUSY CLKUSR DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 (4), TRST Dedicated Inputs Dedicated Clock Pins GCLK1 Lock (10)
AC24 AC22 AE24 AE23 AD24 AD23 AA24 AC23 AD25
AM32 AE32 AP35 AR29 AM28 AL29 AN29 AG35 AM34 AM13 AR12 AN12 AP11 AM11 AR10 AN10 AN34 AL31
A13, B14, AF14, A13, B14, AF14, B24, C25, BG25, C18, D18, AE13 AE13 BG23 AM18, AN18 A14, AF13 A14, AF13 BF24, AL18,
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table FLEX 10KE Device Pin-Outs (Part
Name 356-Pin EPF10K50S 356-Pin EPF10K100E EPF10K130E EPF10K200S
AD13 AE14 A26, C26, H22, M26, T26, AA1, AD26, AF1, AF26
Note
599-Pin EPF10K200E EPF10K200S
BE23 BC25 A45, C11, C19, C29, C37, C47, G25, L45, W45, AJ3, AJ45, AU3, AU45, BE1, BE11, BE19, BE29, BE37, BE47, BG3, BG45 D24, E15, E21, E27, E33, E39, G41, J43, R43, AA5, AA43, AD4, AD44, AG5, AG43, AN5, AN43, AW5, AW43, BA7, BA41, BC9, BC15, BC21, BC27, BC33, BC39, BD24
600-Pin EPF10K130E
600-Pin EPF10K200E EPF10K200S
AR17 AR19 A11, A19, D24, F31, F35, K32, N34, T35, V32, AA33, AB5, AD35, AE4, AF32, AG5, AK31, AK35, AL3, AP24, AR11, AR18 E12, C15, A20, C23, A27, AM26, AR23, AM19, AN15, AL12, AN8, C33, C32, D31, E31, AL5, AM5, AN4, AN3, AM31, AN32, AN33, AP34
DEV_CLRn DEV_OE VCCINT (2.5
AD13 AE14 A26, C26, H22, M26, T26, AA1, AD26, AF1, AF26
AR17 AR19 A11, A19, D24, F31, F35, K32, N34, T35, V32, AA33, AB5, AD35, AE4, AF32, AG5, AK31, AK35, AL3, AP24, AR11, AR18 E12, C15, A20, C23, A27, AM26, AR23, AM19, AN15, AL12, AN8, C33, C32, D31, E31, AL5, AM5, AN4, AN3, AM31, AN32, AN33, AP34
VCCIO (2.5
A23, C15, D25, H24, M23, T25, W22, AB1, AC25, AD18, AF3, AF7, AF16
A23, C15, D25, H24, M23, T25, W22, AB1, AC25, AD18, AF3, AF7, AF16
VCC_CKLK (11)
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table FLEX 10KE Device Pin-Outs (Part
Name 356-Pin EPF10K50S 356-Pin EPF10K100E EPF10K130E EPF10K200S
A10, A20, B22, B25, B26, C13, C25, H23, J26, N26, R26, U26, AD2, AD14, AD20, AE1, AE2, AE7, AE25, AE26, AF11, AF19, AF25
Note
599-Pin EPF10K200E EPF10K200S
A47, C13, C21, C27, C35, C45, G23, N45, AA3, AA45, AG3, AG45, AR3, AR45, BD44, BE3, BE13, BE21, BE27, BE35, BE45, BG1, BG47
600-Pin EPF10K130E
600-Pin EPF10K200E EPF10K200S
A31, A32, A33, A34, A35, B31, B32, B33, B34, B35, C30, C31, D30, E30, AL6, AL30, AM6, AM30, AN5, AN6, AN30, AN31, AN35, AP2, AP3, AP4, AP5, AP6, AP30, AP31, AP32, AP33, AR1, AR2, AR3, AR4, AR5, AR30, AR31, AR32, AR33, AR34, AR35
GNDINT
A10, A20, B22, B25, B26, C13, C25, H23, J26, N26, R26, U26, AD2, AD14, AD20, AE1, AE2, AE7, AE25, AE26, AF11, AF19, AF25
A31, A32, A33, A34, A35, B31, B32, B33, B34, B35, C30, C31, D30, E30, AL6, AL30, AM6, AM30, AN5, AN6, AN30, AN31, AN35, AP2, AP3, AP4, AP5, AP6, AP30, AP31, AP32, AP33, AR1, AR2, AR3, AR4, AR5, AR30, AR31, AR32, AR33, AR34, AR35
GNDIO
E13, E19, E29, E35, E41, F24, G43, H40, N43, W43, AD6, AD42, AJ5, AJ43, AR5, AR43, AY8, AY40, BA5, BA43, BB24, BC7, BC13, BC19, BC29, BC35, BC41
GND_CKLK (11)
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices
Table FLEX 10KE Device Pin-Outs (Part
Name 356-Pin EPF10K50S 356-Pin EPF10K100E EPF10K130E EPF10K200S
Note
599-Pin EPF10K200E EPF10K200S
600-Pin EPF10K130E
600-Pin EPF10K200E EPF10K200S
Connect (N.C.) E22, E25, F23, F26, G22, G25, J23, J24, K25, K26, L23, L26, M22, M25, N25, P22, P23, T22, U23, U24, W24, W26, AA3, AA22, AA25, AB3, AB5, AB22, AB24, AB26 Total User Pins (14)
D35, F34, J32, L31, N33, N35, P33, R32, U34, V34, W31, W35, Y31, AA2, AA34, AB1, AB31, AB34, AB35, AC31, AC34, AE33, AE35, AF1, AG3, AH2, AJ32, AK2, AK32, AL33
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet Notes tables:
pins that listed user pins. EPF10K50E, EPF10K100E, EPF10K100B devices pin-compatible with EPF10K130E devices same package pins connected VCCINT. MAX+PLUS software performs this function automatically when future migration set. EPF10K50E, EPF10K100E, EPF10K100B devices pin-compatible with EPF10K200E devices same package pins 139, 159, 187, connected VCCINT. MAX+PLUS software performs this function automatically when future migration set. This dedicated pin; available user pin. This used user used device-wide configuration function. This used user after configuration. This tri-stated user mode. optional JTAG TRST used 144-pin TQFP package. This drives ClockLock ClockBoost circuitry. This shows status ClockLock ClockBoost circuitry. When ClockLock ClockBoost circuitry locked incoming clock generates internal clock, LOCK driven high. LOCK remains high periodic clock stops clocking. LOCK function optional; LOCK output used, this user pin. This power ground ClockLock ClockBoost circuitry. ensure noise resistance, power ground supply ClockLock ClockBoost circuitry should isolated from power ground rest device. ClockLock ClockBoost circuitry used, this power ground should connected VCCINT GNDINT, respectively. When using EPF10K100B device, connec
Other recent searches
ZNI1000 - ZNI1000 ZNI1000 Datasheet
SGB-4533 - SGB-4533 SGB-4533 Datasheet
S1C17701 - S1C17701 S1C17701 Datasheet
PI74AVC+16374 - PI74AVC+16374 PI74AVC+16374 Datasheet
Builder - Builder Builder Datasheet
Errata - Errata Errata Datasheet
Sheet - Sheet Sheet Datasheet
2SA1892 - 2SA1892 2SA1892 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
