GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER output, skew signal buff

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GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER output, skew signal buff

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QS5805T/AT/BT GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
output, skew signal buffer Guaranteed skew: 0.7ns output skew (same bank) 0.9ns output skew (different bank) part-to-part skew Input hysteresis better noise margin Monitor output Undershoot clamp diodes inputs Std., speed grades Available QSOP SOIC packages
QS5805T/AT/BT
DESCRIPTION:
QS5805T clock buffer/driver circuits used clock buffering schemes where skew parameter. This device offers banks five non-inverting outputs. This device provides propagation delay buffering with on-chip skew 0.7ns same-transition, same-bank signals. QS5805T characterized operation -40°C +85°C.
FUNCTIONAL BLOCK DIAGRAM
1999 Integrated Device Technology, Inc.
JULY 2000
DSC-5267
QS5805T/AT/BT GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
CONFIGURATION
SO20-2 SO20-8
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) IOUT TSTG Description Supply Voltage Ground Output Voltage VOUT Input Voltage Input Voltage (pulse width 20ns) Input Diode Current Output Current Max. Sink Current/Pin Storage Temperature Junction Temperature
Unit
Max. +150
QSOP/ SOIC VIEW
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Terminals. terminals except Vcc.
CAPACITANCE
Pins COUT
+25OC, 1.0MHz,
Max. Unit
Typ.
NOTE: This parameter guaranteed production tested.
DESCRIPTION
Names OEA, INA, OAn, Description Output Enable Inputs Clock Inputs Clock Outputs Unbuffered Monitor Output
QS5805T/AT/BT GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: -40°C +85°C, 5.0V
Symbol IOFF Parameter Input HIGH Voltage Input Voltage Clamp Diode Voltage Output HIGH Voltage Output Voltage Input Leakage Current Input/Output Power Leakage Output Leakage Current Short Circuit Current Input Hysteresis
(2,3)
Test Conditions Guaranteed Logic HIGH Inputs Guaranteed Logic Inputs Min., -18mA Min., -24mA Min., -32mA Min., 64mA Max., VOUT Max., VOUT Max., VOUT VTLH VTHL Inputs
Min.
Typ.(1) -0.7
Max. -1.2 0.55 -250
Unit
NOTES: Typical values 5.0V, 25°C. more than output should used test this high power condition. Duration less than second. Guaranteed design tested.
POWER SUPPLY CHARACTERISTICS
Symbol ICCD Parameter Quiescent Power Supply Current Supply Current Input HIGH Dynamic Power Supply Current Output Total Power Supply Current Examples (2,4) Test Conditions Max., Max., 3.4V, 0MHz Max., Outputs Enabled, duty cycle Max., duty cycle, 10MHz Five outputs toggling Unused inputs Max., duty cycle, 2.5MHz outputs toggling Typ. 0.005 0.08 3.4V Max. 0.18 10.8 Unit mA/MHz
3.4V
NOTES: conditions shown Min. Max., appropriate values specified under Electrical Characteristics. Guaranteed design tested. 0pF. Typical values reference only. Conditions 5.0V, 25°C. (ICC)(DH)(NT) ICCD (fO)(NO) where: Input Duty Cycle Number HIGH inputs (one two) Output Frequency Number outputs
QS5805T/AT/BT GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
SKEW CHARACTERISTICS OVER OPERATING RANGE
-40°C +85°C, 5.0V CLOAD 50pF; RLOAD
QS5805T Symbol tSK(01) tSK(02) tSK(P) tSK(T) Parameter Skew between outputs, same transition, same bank Skew between outputs, same transition, different banks Pulse Skew; opposite transition skew, same output (tPHL tPLH) Part-to-part skew Min. Max. QS5805AT Min. Max. QS5805BT Min. Max. Unit
NOTES: Skew parameters guaranteed across temperature range, tested. Skew parameters apply propagation delays only. tSK(T) only applies devices same transition, part type, temperature, power supply voltage, loading, package, speed grade.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
-40°C +85°C, 5.0V CLOAD 50pF; RLOAD
QS52805T Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ Parameter Propagation Delay Output Enable Time Output Disable Time Output Rise Time, 0.8V Output Fall Time, 0.8V Min. Max. QS52805AT Min. Max. QS5805BT Min. Max. Unit
NOTES: Minimums guaranteed production tested. propagation delay other range indicated Min. Max. specifications results from process environmental variables. These propagation delays imply limit skew. This parameter guaranteed tested.
QS5805T/AT/BT GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
TEST CIRCUITS WAVEFORMS
Parameter Tested
Switch Position
tPLZ, tPZL Others Pulse Generator 50pF
Closed Open
Pulse generator pulses: 1.0MHz; 2.5ns; 2.5ns
PROPAGATION DELAY
INPUT tPLH tPHL 2.0V 1.5V 0.8V 1.5V INPUT
PULSE SKEW tSK(P)
1.5V tPLH OUTPUT tPHL 1.5V tSK(p) tPLH
OUTPUT
OUTPUT SKEW (SAME BANK) tSK(O1)
INPUT tPLH1 tPHL1 OUTPUT 1.5V tSK(01) OUTPUT tSK(01) 1.5V tPLH2 tPHL2 1.5V INPUT
OUPUT SKEW (DIFFERENT BANKS) tSK(O2)
1.5V tPLHA tPHLA OUTPUT 1.5V tSK(02) OUTPUT tSK(02) 1.5V tPLHB tPHLB
tSK(01) tPLH2 tPLH1 tPHL2 tPHL1
tSK(02) tPLHB tPLHA tPHLB tPHLA
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY SWITCH CLOSED tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 1.5V tPLZ 1.5V 0.3V tPHZ 0.3V PART OUTPUT PART OUTPUT DISABLE 1.5V INPUT
PART-TO-PART SKEW tSK(T)
1.5V tPLH1 tPHL1 1.5V tSK(t) tSK(t) 1.5V tPLH2 tPHL2
tSK(t) PLH2 tPLH1 tPHL2 tPHL1
QS5805T/AT/BT GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
ORDERING INFORMATION
XXXX Device Type Package
Quarter Size Small Outline Package (SO20-8) Small Outline (SO20-2)
5805T 5805AT 5805BT
Guaranteed Skew CMOS Clock Driver/Buffer
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GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER output, skew signal buff

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