Speed essence- explosion network bandwidth driven convergence voi

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Speed essence- explosion network bandwidth driven convergence voi

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SR40 0.095 High-Speed Copper Standard Cell/Gate Array ASIC
Speed essence-
explosion network bandwidth driven convergence voice data communications requires specialized ASIC product. Optimized high-speed communications market, SR40 provides unparalleled performance time-to-market. SR40 gives network equipment ASIC designers tools they need enable next-generation Dense Wavelength Division Multiplexing (DWDM) systems, backbone routers, multi-gigabit Ethernet switches, Internet appliances, mobile equipment.
SR40 Product Specifications
Ldrawn Leff 130-nm class layers second-generation dual-damascene copper with low-K dielectric optimized high performance 0.35 metal pitch Transistor performance 37.4 (ring oscillator fanout Gate delays 25ps (2-input NAND gate) Power dissipation nW/MHz/gate Power supply: 1.2v power supply: 2.5v 3.3v Synthesis-optimized libraries with macros 5-11 drive strengths Extremely high density SRAM compilers 450K bits/mm2 based industry's smallest SRAM cell 1.95 Broad range wirebond packages 1000 pins High-performance flipchip packaging 2500 pins Scalable SERDES technology providing excess 40Gbps synchronous 2.5Gbps serial bandwidth 640Gbps full duplex device
High-performance silicon high-performance Internetwork
TI's advanced process technology
Breaking bandwidth barrier provides top-tier performance
SR40, newest offering from ASIC, performance, integration, low-peak power benefits make these nextgeneration internetwork applications reality. SR40 brings market TI's industry-leading high-performance processor silicon process maximum core speed. When combined with TI's barrier-breaking SERDES technology integration expertise, ASIC designers create scalable aggregate bandwidth required today's exploding network demand. reduced risk using secondgeneration copper metal system used TI's high-performance processors. This provides 46percent reduction interconnect delay 56-percent reduction gate delay when compare previous ASIC products. Combined with 1.2v core power supply low-peak power dissipation, SR40 provides speed power management capabilities critical power-budgeted broadband equipment.
Data serialization deserialization Synchronous, uni- bi-directional interfaces Clock generation Clock recovery physical layer interface Selectable 8-bit 10-bit interface
applications such synchronous digital hierarchy (SDH) asynchronous transfer mode (ATM), SR40 includes macros phase alignment digital clock recovery with selectable interface options. These provide implementation OC768 channels through variety speeds excellent choice costeffective optical interfaces.
SERDES Solution
SERDES high-speed interface solutions transceiver cores that support channels full duplex data rates from Gbps excess 2.5Gbps. These ideal gigabit Ethernet applications. Features include:
Data eyes channels Gbps
Integrating systems chip
Optimized libraries, wide variety interface types leading-edge SRAM density combined with wide array intellectual property (IP) robust design environment make SR40 clear choice true System Level Integration. TImeBuildermodule library production-proven provides configurable building blocks flexibility integration needed network applications including: SERDES family highspeed transceiver cores Single- multiple-channel HDLC controllers Ethernet PHYs MACs 32-bit RISC processors MIPS 64-bit RISC processors DSPs Wide range processor support peripherals controllers Interface controllers PCI, USB, 1394, 1284
Memories
Bits
1Mbit 1Mbit 1Mbit 128K 128K 128K 128K 1Mbit 128K 128K
Description
2-port (1W/1R) 1-port Clocked RAM, density optimized, write 1-port CRAM, density optimized, write, testability 1-port CROM, fast, via2 program Dual-port CRAM, write 1-port CRAM, multistrobe, page mode, power 1-port CRAM, multistrobe, page mode, power, testability 2-port register file (1W/1R), write 1-port CRAM, area optimized, write 1-port CROM, moat program 2-port CRAM (1W/1R), large, compiler
Bits/ Bits Words Word
TI's unique Architectcapability enables creation processor-based subsystems within days.
High-density fast SRAM maximum throughput
With TI's wide range high-density SRAM compiler technology, ASIC designers easily integrate large amounts on-chip memory maximum integration. well standard 2-port compilers, SR40 includes custom function compilers such contentaddressable memories (CAMs).
approach lets designer take full advantage high-performance characteristics that deep-submicron technology offers. TImePilot open system that integrates best technology from both industry design tools from multiple vendors environment that facilitates predictably meeting timing goals. TImePilot hierarchical design viewing editing, timing analysis allow designers achieve accurate representation silicon through timing closure.
partners take design through design process from system specification, through early evaluation, hierarchical design, layout, test production. Flexible support includes foundry turnkey design services. TI's global supply chain, with manufacturing facilities worldwide, speeds time-to-market, putting manufacturing where customer needs ensuring just-in-time delivery while lowering shipping inventory management costs. more information, visit site http://www.ti.com/sc/docs/asic/ homepage.htm
Flexible, worldwide, experienced service
offers worldwide service support with local Customer Design Centers (CDCs) committed timely success customer's design. With service centers time zones around world, support structure take shape 24-hour virtual office.
TImePilot gets there
TImePilot design system high-performance design methodology focused meeting designer's predictability time-to-market needs. This design
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