High Speed Translator Buffers: Single ended PECL LVDS FEATURES Differe

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High Speed Translator Buffers: Single ended PECL LVDS FEATURES Differe

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PLL130-68/-69
High Speed Translator Buffers: Single ended PECL LVDS FEATURES Differential PECL (PLL130-68) LVDS (PLL130-69) output. Accepts single-ended REFIN input (with 100mV swing). Internal coupling REFIN Input range from 1.0MHz GHz. Vref required. external current source required. 3.3V operation. Available 3x3mm QFN. CONFIGURATION
Q_bar
REFIN
Q_bar OESEL
PLL130-6x
DESCRIPTION PLL130-68 PLL130-69 cost, high performance, high speed, translator buffers that reproduce input frequency from 1.0GHz. They provide pair differential outputs (PECL PLL130-68 LVDS PLL13069). Thanks internal coupling reference input (REFIN), input signal with least 100mV swing used reference signal, regardless value. These chips ideal conversion from clipped sine wave, TTL, CMOS, differential signal LVDS PECL.
OUTPUT ENABLE LOGICAL LEVELS PLL130-68
OESEL (Default) OECTRL (Default) (Default) OUTPUT STATE Output enabled Tri-state Tri-state Output enabled
OECTRL input: Logical states defined PECL levels.
PLL130-69
OESEL (Default) OECTRL (Default) (Default) OUTPUT STATE Tri-state Output enabled Output enabled Tri-state
OECTRL input: Logical states defined CMOS levels.
BLOCK DIAGRAM
OECTRL
REFIN
Coupling
Input
Q_BAR
Amplifier
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 09/09/04 Page
PLL130-68/-69
High Speed Translator Buffers: Single ended PECL LVDS DESCRIPTION
Name
REFIN OECTRL OESEL Q_BAR Q_BAR
number
Type
connection.
Description
Reference input signal. frequency this signal will reproduced output (after translation PECL LVDS level). Output enable input (See Logic Table page Ground connector. Output enable logic selector (See Logic Table page Complementary output. PECL_bar PLL130-68, LVDS_bar PLL130-69. True output. PECL PLL130-68, LVDS PLL130-69. 3.3V Power supply. Additional true output. PECL PLL130-68, LVDS PLL130-69. This output same Additional complementary output. PECL_bar PLL130-68, LVDS_bar PLL130-69. This output same
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) Protection, Human Body Model
SYMBOL
MIN.
-0.5 -0.5
MAX.
+0.5 +0.5
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied. Note: Operating Temperature guaranteed design parts (COMMERCIAL INDUSTRIAL), tested COMMERCIAL grade only.
General Electrical Specifications PARAMETERS
Supply Current (both outputs loaded) Operating Voltage Output Clock Duty Cycle Short Circuit Current
SYMBOL
CONDITIONS
Fout 156.25MHz, PECL Fout 156.25MHz, LVDS 1.3V (PECL) 1.25V (LVDS)
MIN.
2.97
TYP.
Same input Same input
MAX.
3.63
UNITS
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 11/29/04 Page
PLL130-68/-69
High Speed Translator Buffers: Single ended PECL LVDS
Specifications PARAMETERS
Input Frequency Input signal swing Output Frequency
CONDITIONS
REFIN input
MIN.
TYP.
MAX.
1000 1000
UNITS
PECL Electrical Characteristics PARAMETERS
Output High Voltage Output Voltage
SYMBOL
CONDITIONS
(see figure)
MIN.
1.025 1.810
MAX.
0.880 1.620
UNITS
PECL Switching Characteristics PARAMETERS
Clock Rise Time Clock Fall Time
SYMBOL
CONDITIONS
@20/80% PECL @80/20% PECL
MIN.
TYP.
MAX.
UNITS
PECL Levels Test Circuit
PECL Output Skew
2.0V
tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 11/29/04 Page
PLL130-68/-69
High Speed Translator Buffers: Single ended PECL LVDS
LVDS Electrical Characteristics PARAMETERS
Output Differential Voltage Magnitude Change Output High Voltage Output Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current
SYMBOL
CONDITIONS
MIN.
1.125
TYP.
-5.7
MAX.
1.375
UNITS
(see figure)
LVDS Switching Characteristics PARAMETERS
Differential Clock Rise Time Differential Clock Fall Time
LVDS Levels Test Circuit
SYMBOL
CONDITIONS (see figure)
MIN.
TYP.
MAX.
UNITS
LVDS Switching Test Circuit
10pF
VDIFF
10pF
LVDS Transistion Time Waveform
(Differential)
VDIFF
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 11/29/04 Page
PLL130-68/-69
High Speed Translator Buffers: Single ended PECL LVDS
PACKAGE INFORMATION
Important note: indicator (bottom side) metallized connected through leadframe. Traces contact with indicator result short circuit GND.
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PLL130-6X
PART NUMBER
TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE Q=QFN
Order Number PLL130-68QC-R PLL130-68QC PLL130-69QC-R PLL130-69QC
Marking P130-68 P130-68 P130-69 P130-69
Package Option Tape Reel Tube Tape Reel Tube
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 11/29/04 Page

High Speed Translator Buffers: Single ended PECL LVDS FEATURES Differe

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