The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

Synchronous DRAM MT48LC2M32B2 512K banks latest data sheet,


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



64Mb: SDRAM Features
Synchronous DRAM
MT48LC2M32B2 512K banks
latest data sheet, refer Micron's site
Features
PC100 functionality Fully synchronous; signals registered positive edge system clock Internal pipelined operation; column address changed every clock cycle Internal banks hiding access/precharge Programmable burst lengths: full page Auto precharge, includes concurrent auto precharge, auto refresh modes Self refresh mode 64ms, 4,096-cycle refresh (15.6µs/row) LVTTL-compatible inputs outputs Single +3.3V ±0.3V power supply Supports latency (CL)
Table
Address Table
Configuration Refresh count addressing Bank addressing Column addressing
512K banks (A0-A10) (BA0, BA1) (A0-A7)
Table
Timing Parameters
(READ) latency Access Time 4.5ns 5.5ns 5.5ns
Speed Grade
Clock Frequency
Setup Time 1.5ns 1.5ns 1.5ns
Hold Time
Options
Configuration (512K banks) Plastic package OCPL1 86-pin TSOP (400 mil) 86-pin TSOP (400 mil) Pb-free 90-ball VFBGA (8mm 13mm) leadfree Timing (cycle time) (200 MHz) 5.5ns (183 MHz) (166 MHz) (143 MHz) revision Operating temperature range Commercial +70°C) Extended (-40°C +85°C) Notes: Off-center parting line. Available Part Number Example:
Marking
2M32B2
Table
64Mb (x32) SDRAM Part Number
Architecture
Part Number
None
MT48LC2M32B2TG MT48LC2M32B2P MT48LC2M32B2B51
Notes: FBGA Device Decode: http://
MT48LC2M32B2P-7:G
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_1.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
Products specifications discussed herein subject change Micron without notice.
64Mb: SDRAM General Description
General Description
Micron® 64Mb SDRAM high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. internally configured quad-bank DRAM with synchronous interface (all signals registered positive edge clock signal, CLK). Each 16,777,216-bit banks organized 2,048 rows columns bits. Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select bank accessed (BA0, select bank, A0-A10 select row). address bits registered coincident with READ WRITE command used select starting column location burst access. SDRAM provides programmable read write burst lengths (BL) locations, full page, with burst terminate option. auto precharge function enabled provide self-timed precharge that initiated burst sequence. 64Mb SDRAM uses internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows column address changed every clock cycle achieve high-speed, fully random access. Precharging bank while accessing other three banks will hide PRECHARGE cycles provide seamless, high-speed, random-access operation. 64Mb SDRAM designed operate 3.3V, low-power memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs outputs LVTTL-compatible. SDRAMs offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with automatic column-address generation, ability interleave between internal banks hide precharge time capability randomly change column addresses each clock cycle during burst access.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_1.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Table Contents Table Contents
Features Options General Description Functional Block Diagram. Pin/Ball Assignments Descriptions. Functional Description Initialization Register Definition Mode Register. Burst Length Burst Type Latency Operating Mode. Write Burst Mode. Commands COMMAND INHIBIT. OPERATION (NOP). LOAD MODE REGISTER ACTIVE READ WRITE PRECHARGE Auto Precharge BURST TERMINATE AUTO REFRESH SELF REFRESH Operations Bank/Row Activation READs WRITEs PRECHARGE. Power-Down. Clock Suspend Burst Read/Single Write. Concurrent Auto Precharge Electrical Specifications. Temperature Thermal Impedance Notes Timing Diagrams. Package Dimensions
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32TOC.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM List Figures List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure SDRAM 86-Pin TSOP (Top View) 90-Ball VFBGA (Top View, Ball Down) Mode Register Definition Latency Activating Specific Specific Bank Example: Meeting tRCD (MIN) when tRCD (MIN)/tCK READ Command Latency Consecutive READ Bursts Random READ Accesses READ-to-WRITE READ-to-WRITE With Extra Clock Cycle READ-to-PRECHARGE Terminating READ Burst WRITE Command WRITE Burst WRITE-to-WRITE Random WRITE Cycles WRITE-to-READ WRITE-to-PRECHARGE Terminating WRITE Burst PRECHARGE Command Power-Down Clock Suspend During WRITE Burst Clock Suspend During READ Burst READ with Auto Precharge Interrupted READ READ with Auto Precharge Interrupted WRITE WRITE with Auto Precharge Interrupted READ WRITE with Auto Precharge Interrupted WRITE Example Temperature Test Point Location, 86-Pin TSOP (Top View) Example Temperature Test Point Location, 90-Ball FBGA (Top View) Initialize Load Mode Register Power-Down Mode Clock Suspend Mode Auto Refresh Mode Self Refresh Mode Single READ Single READ Without Auto Precharge READ with Auto Precharge Alternating Bank Read Accesses READ Full-Page Burst READ Operation Single WRITE WRITE Without Auto Precharge WRITE with Auto Precharge Alternating Write Accesses WRITE Full-Page Burst WRITE Operation 86-Pin Plastic TSOP (400 mil) 90-Ball VFBGA (8mm 13mm)
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32LOF.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM List Tables List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Address Table Timing Parameters 64Mb (x32) SDRAM Part Number Pin/Ball Descriptions. Burst Definition. Latency Truth Table Commands Operation Truth Table Truth Table Current State Bank Command Bank Truth Table Current State Bank Command Bank Absolute Maximum Ratings Temperature Limits Thermal Impedance Simulated Values Electrical Characteristics Operating Conditions. Specifications Conditions TSOP Capacitance VFBGA Capacitance Electrical Characteristics Recommended Operating Conditions Functional Characteristics
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32LOT.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Functional Block Diagram
Functional Block Diagram
Figure SDRAM
CAS# RAS# CONTROL LOGIC BANK BANK BANK BANK
COMMAND DECODE
MODE REGISTER
REFRESH COUNTER
ROWADDRESS
BANK ROWADDRESS LATCH DECODER
2048
BANK0 MEMORY ARRAY (2,048
DQM0- DQM3
SENSE AMPLIFIERS 8192
DATA OUTPUT REGISTER
A0-A10, BA0, ADDRESS REGISTER BANK CONTROL LOGIC
GATING MASK LOGIC READ DATA LATCH WRITE DRIVERS (x32)
DQ0- DQ31
DATA INPUT REGISTER
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Pin/Ball Assignments Descriptions
Pin/Ball Assignments Descriptions
Figure 86-Pin TSOP (Top View)
VDDQ VSSQ VDDQ VSSQ DQM0 CAS# RAS# DQM2 DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23
DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ DQM1 DQM3 DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24
Note:
symbol indicates signal active LOW.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Pin/Ball Assignments Descriptions
Figure 90-Ball VFBGA (Top View, Ball Down)
DQ26 DQ24 DQ23 DQ21
DQ28 VDDQ VSSQ VDDQ VSSQ DQ19
VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ
VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ
VDDQ DQ31 DQ16 VSSQ
DQM3 DQM2
RAS#
DQM1 CAS# DQM0
VDDQ VSSQ
VSSQ DQ10 VDDQ
VSSQ DQ12 DQ14 VDDQ
DQ11 VDDQ VSSQ VDDQ VSSQ
DQ13 DQ15
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Pin/Ball Assignments Descriptions
Table Pin/Ball Descriptions
90-Ball VFBGA Numbers Symbol Type Input Description Clock: driven system clock. SDRAM input signals sampled positive edge CLK. also increments internal burst counter controls output registers. Clock enable: activates (HIGH) deactivates (LOW) signal. Deactivating clock provides PRECHARGE powerdown SELF REFRESH operation (all banks idle), ACTIVE power-down (row active bank), CLOCK SUSPEND operation (burst/access progress). synchronous except after device enters power-down self refresh modes, where becomes asynchronous until after exiting same mode. input buffers, including CLK, disabled during power-down self refresh modes, providing standby power. tied HIGH. Chip select: enables (registered LOW) disables (registered HIGH) command decoder. commands masked when registered HIGH, READ/WRITE bursts already progress will continue operation will retain mask capability while HIGH. provides external bank selection systems with multiple banks. considered part command code. Command inputs: WE#, CAS#, RAS# (along with CS#) define command being entered. Input/output mask: sampled HIGH input mask signal write accesses output enable signal read accesses. Input data masked during WRITE cycle. output buffers placed High-Z state (2-clock latency) during READ cycle. DQM0 corresponds DQ0-DQ7; DQM1 corresponds DQ8-DQ15; DQM2 corresponds DQ16-DQ23; DQM3 corresponds DQ24-DQ31. DQM0-DQM3 considered same state when referenced DQM. Bank address input(s): define which bank ACTIVE, READ, WRITE, PRECHARGE command being applied. Address inputs: A0-A10 sampled during ACTIVE command (row-address A0-A10) READ/WRITE command (column-address A0-A7 with defining auto precharge) select location memory array respective bank. sampled during PRECHARGE command determine whether banks precharged (A10 HIGH) bank selected BA0, (LOW). address inputs also provide op-code during LOAD MODE REGISTER command. Data I/Os: Data bus.
86-Pin TSOP Numbers
Input
Input
WE#, CAS#, RAS# DQM0- DQM3
Input
Input
BA0,
Input
25-27, 60-66,
A0-A10
Input
DQ0- DQ31
Input/ Output
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Functional Description
Table Pin/Ball Descriptions (continued)
90-Ball VFBGA Numbers Symbol VDDQ Type Supply Description power supply: Isolated improved noise immunity. ground: Provide isolated ground improved noise immunity. Power supply: +3.3V ±0.3V. (See note page 50.) Ground. connect: These pins/balls should left unconnected. reserved SSTL reference voltage supply. connect this part used future designs. used 128Mb, 256Mb, 512Mb FBGAs. designs that accommodate different densities must account with stuffing options.
86-Pin TSOP Numbers
VSSQ
Supply
Supply Supply
Functional Description
general, this 64Mb SDRAM (512K banks) 4-bank DRAM that operates 3.3V includes synchronous interface (all signals registered positive edge clock signal, CLK). Each 16,777,216-bit banks organized 2,048 rows columns bits. Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select bank accessed (BA0 select bank, A0-A10 select row). address bits (A0-A7) registered coincident with READ WRITE command used select starting column location burst access. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions, device operation.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. After power applied VDDQ (simultaneously) clock stable (stable clock defined signal cycling within timing constraints specified clock pin), SDRAM requires 100µs delay prior issuing command other than COMMAND INHIBIT NOP. Starting some point during this 100µs period, continuing least through this period, COMMAND INHIBIT commands must applied. When 100µs delay been satisfied with least COMMAND INHIBIT command having been applied, PRECHARGE command should applied. banks must then precharged, thereby placing device banks idle state.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Functional Description
When idle state, least AUTO REFRESH cycles must performed. After AUTO REFRESH cycles complete, SDRAM ready mode register programming. Because mode register will power unknown state, must loaded prior applying operational command. desired, AUTO REFRESH commands issued after LOAD MODE REGISTER command. recommended power-up sequence SDRAMs: Simultaneously apply power VDDQ. Assert hold LVTTL logic since inputs outputs LVTTLcompatible. Provide stable CLOCK signal. Stable clock defined signal cycling within timing constraints specified clock pin. Wait least 100µs prior issuing command other than COMMAND INHIBIT NOP. Starting some point during this 100µs period, bring HIGH. Continuing least through this period, more COMMAND INHIBIT commands must applied. Perform PRECHARGE command. Wait least time; during this time,0 NOPs DESELECT commands must given. banks will complete their precharge, thereby placing device banks idle state. Issue AUTO REFRESH command. Wait least tRFC time, during which only NOPs COMMAND INHIBIT commands allowed. Issue AUTO REFRESH command. Wait least tRFC time, during which only NOPs COMMAND INHIBIT commands allowed. SDRAM ready mode register programming. Because mode register will power unknown state, should loaded with desired values prior applying operational command. Using command, program mode register. mode register programmed MODE REGISTER command with retains stored information until programmed again device loses power. programming mode register upon initialization will result default settings which desired. Outputs guaranteed High-Z after command issued. Outputs should High-Z already before command issued. Wait least tMRD time, during which only DESELECT commands allowed. this point DRAM ready valid command. Note: desired, more than AUTO REFRESH commands issued sequence. After steps complete, repeat them until desired number AUTO REFRESH tRFC loops achieved.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Functional Description Register Definition
Mode Register mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, operating mode write burst mode, shown Figure page mode register programmed LOAD MODE REGISTER command will retain stored information until programmed again device loses power. Mode register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), M4-M6 specify specify operating mode, specifies write burst mode, reserved future use. mode register must loaded when banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation. Burst Length Read write accesses SDRAM burst oriented, with burst length being programmable, shown Figure burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. fullpage burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached. block uniquely selected A1-A7 when A2-A7 when A3-A7 when remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Functional Description
Figure Mode Register Definition
Address
Reserved
Mode Register (Mx)
Mode
Latency
Burst Length
Program A10, BA0, ensure compatibility with future devices.
Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Write Burst Mode Programmed Burst Length Single Location Access
M6-M0 Defined
Operating Mode Standard Operation other states reserved
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved
Burst Type Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type, starting column address, shown Table page
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Functional Description
Table Burst Definition
Burst Length Order Accesses Within Burst Starting Column Address Type Sequential 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Type Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 supported
Full page (256) Notes:
A0-A10 (location 0-256)
A1-A7 select block-of-two burst; selects starting column within block. A2-A7 select block-of-four burst; A0-A1 select starting column within block. A3-A7 select block-of-eight burst; A0-A2 select starting column within block. full-page burst, full selected A0-A7 select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. A0-A7 select unique column accessed, mode register ignored.
Latency latency delay, clock cycles, between registration READ command availability first piece output data. latency clocks. READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, READ command registered latency programmed clocks, will start driving after data will valid shown Figure page Table page indicates operating frequencies which each latency setting used. Reserved states should used because unknown operation incompatibility with future versions result.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Functional Description
Figure Latency
COMMAND
READ
DOUT
COMMAND
READ
DOUT
COMMAND
READ
DOUT
DON'T CARE UNDEFINED
Table
Latency
Allowable Operating Frequency (MHz)
Speed
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Operating Mode normal operating mode selected setting zero; other combinations values reserved future and/or test modes. programmed burst length applies both read write bursts. Test modes reserved states should used because unknown operation incompatibility with future versions result. Write Burst Mode When burst length programmed M0-M2 applies both read write bursts; when programmed burst length applies read bursts, write accesses single-location (nonburst) accesses.
Commands
Truth Table provides quick reference available commands. This followed written description each command. Three additional Truth Tables appear following "Operations" page these tables provide current state/next state information. Table Truth Table Commands Operation
HIGH commands shown except SELF REFRESH Name (Function) COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER WRITE ENABLE/OUTPUT ENABLE WRITE INHIBIT/OUTPUT HIGH-Z Notes: RAS# CAS# L/H7 L/H7 ADDR Bank/row Bank/col Bank/col Code Op-code Valid Active Active High-Z Notes
A0-A10 provide address, determine which bank made active. A0-A7 provide column address; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge feature; determine which bank being read from written LOW: determine bank being precharged. HIGH: banks precharged "Don't Care." This command AUTO REFRESH HIGH; SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. A0-A10 define op-code written mode register. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay). DQM0 controls DQ0-DQ7; DQM1 controls DQ8-DQ15; DQM2 controls DQ16-DQ23; DQM3 controls DQ24-DQ31.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands COMMAND INHIBIT
COMMAND INHIBIT function prevents commands from being executed SDRAM, regardless whether signal enabled. SDRAM effectively deselected. Operations already progress affected.
OPERATION (NOP)
OPERATION (NOP) command used perform SDRAM that selected (CS# LOW). This prevents unwanted commands from being registered during idle wait states. Operations already progress affected.
LOAD MODE REGISTER
mode register loaded inputs A0-A10. "Mode Register" page LOAD MODE REGISTER command only issued when banks idle, subsequent executable command cannot issued until tMRD met.
ACTIVE
ACTIVE command used open activate) particular bank subsequent access. value BA0, inputs selects bank, address provided inputs A0-A10 selects row. This remains active open) accesses until PRECHARGE command issued that bank. PRECHARGE command must issued before opening different same bank.
READ
READ command used initiate burst read access active row. value (B1) inputs selects bank, address provided inputs A0-A7 selects starting column location. value input determines whether auto precharge used. auto precharge selected, being accessed will precharged read burst; auto precharge selected, will remain open subsequent accesses. Read data appears subject logic level inputs clocks earlier. given DQMx signal registered HIGH, corresponding will High-Z clocks later; DQMx signal registered LOW, corresponding will provide valid data. DQM0 corresponds DQ0-DQ7, DQM1 corresponds DQ8-DQ15, DQM2 corresponds DQ16-DQ23, DQM3 corresponds DQ24-DQ31.
WRITE
WRITE command used initiate burst write access active row. value inputs selects bank, address provided inputs A0-A7 selects starting column location. value input determines whether auto precharge used. auto precharge selected, being accessed will precharged write burst; auto precharge selected, will remain open subsequent accesses. Input data appearing written memory array subject input logic level appearing coincident with data. given signal registered LOW, corresponding data will written memory; signal registered HIGH, corresponding data inputs will ignored, write will executed that byte/column location.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands PRECHARGE
PRECHARGE command used deactivate open particular bank open banks. bank(s) will available subsequent access specified time (tRP) after PRECHARGE command issued. Input determines whether banks precharged, case where only bank precharged, inputs select bank. Otherwise treated "Don't Care." After bank been precharged, idle state must activated prior READ WRITE commands being issued that bank.
Auto Precharge
Auto precharge feature that performs same individual-bank precharge function described above, without requiring explicit command. This accomplished using enable auto precharge conjunction with specific READ WRITE command. precharge bank/row that addressed with READ WRITE command automatically performed upon completion READ WRITE burst, except full-page burst mode, where AUTO PRECHARGE does apply. Auto precharge nonpersistent that either enabled disabled each READ WRITE command. Auto precharge ensures that precharge initiated earliest valid stage within burst. user must issue another command same bank until precharge time (tRP) completed. This determined explicit PRECHARGE command issued earliest possible time, described each burst type "Operations" page
BURST TERMINATE
BURST TERMINATE command used truncate either fixed-length full-page bursts. most recently registered READ WRITE command prior BURST TERMINATE command will truncated, shown "Operations" page BURST TERMINATE command does precharge row; will remain open until PRECHARGE command issued.
AUTO REFRESH
AUTO REFRESH used during normal operation SDRAM analogous CAS#-BEFORE-RAS# (CBR) refresh conventional DRAMs. This command nonpersistent, must issued each time refresh required. addressing generated internal refresh controller. This makes address bits "Don't Care" during AUTO REFRESH command. 64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (tREF), regardless width option. Providing distributed AUTO REFRESH command every 15.625µs will meet refresh requirement ensure that each refreshed. Alternatively, 4,096 AUTO REFRESH commands issued burst minimum cycle rate (tRC), once every 64ms.
SELF REFRESH
SELF REFRESH command used retain data SDRAM, even rest system powered down. When self refresh mode, SDRAM retains data without external clocking. SELF REFRESH command initiated like AUTO REFRESH command except disabled (LOW). When SELF REFRESH command registered, inputs SDRAM become "Don't Care" with exception CKE, which must remain LOW.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
After self refresh mode engaged, SDRAM provides internal clocking, causing perform AUTO REFRESH cycles. SDRAM must remain self refresh mode minimum period equal tRAS remain self refresh mode indefinite period beyond that. procedure exiting self refresh requires sequence commands. First, must stable (stable clock defined signal cycling within timing constraints specified clock pin) prior going back HIGH. After HIGH, SDRAM must have commands issued minimum clocks) tXSR because time required completion internal refresh progress. Upon exiting self refresh mode, AUTO REFRESH commands must issued every 15.625µs less both SELF REFRESH AUTO REFRESH utilize refresh counter.
Operations
Bank/Row Activation Before READ WRITE commands issued bank within SDRAM, that bank must "opened." This accomplished ACTIVE command, which selects both bank activated. Figure page After opening (issuing ACTIVE command), READ WRITE command issued that row, subject tRCD specification. tRCD (MIN) should divided clock period rounded next whole number determine earliest clock edge after ACTIVE command which READ WRITE command issued. example, tRCD specification 20ns with clock (8ns period) results clocks, rounded This reflected Figure page which covers case where tRCD (MIN)/tCK (the same procedure used convert other specification limits from time units clock cycles). subsequent ACTIVE command different same bank only issued after previous active been "closed" (precharged). minimum time interval between successive ACTIVE commands same bank defined tRC. subsequent ACTIVE command another bank issued while first bank being accessed, which results reduction total row-access overhead. minimum time interval between successive ACTIVE commands different banks defined RRD.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Figure Activating Specific Specific Bank
HIGH
RAS#
CAS#
A0-A10
ADDRESS
BA0,
BANK ADDRESS
CARE
Figure
Example: Meeting tRCD (MIN) when tRCD (MIN)/tCK
COMMAND ACTIVE tRCD (MIN) tRCD (MIN) +0.5 READ WRITE
DON'T CARE
Notes:
tRCD
(MIN) 20ns, 8ns. (MIN) where number clocks equation true.
READs READ bursts initiated with READ command, shown Figure page starting column bank addresses provided with READ command, auto precharge either enabled disabled that burst access. auto precharge enabled, being accessed precharged completion burst. generic READ commands used following illustrations, auto precharge disabled. During READ bursts, valid data-out element from starting column address will available following latency after READ command. Each subsequent dataout element will valid next positive clock edge. Figure page shows general timing each possible latency setting.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07 Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Upon completion burst, assuming other commands have been initiated, will High-Z. full-page burst will continue until terminated. page, will wrap column continue.) Data from READ burst truncated with subsequent READ command, data from fixed-length READ burst immediately followed data from READ command. either case, continuous flow data maintained. first data element from burst either follows last element completed burst last desired data element longer burst that being truncated. READ command should issued cycles before clock edge which last desired data element valid, where equals This shown Figure page data element either last burst four last desired longer burst. This 64Mb SDRAM uses pipelined architecture therefore does require rule associated with prefetch architecture. READ command initiated clock cycle following previous READ command. Full-speed random read accesses performed same bank, shown Figure page each subsequent READ performed different bank. Figure READ Command
HIGH
RAS#
CAS#
A0-A7
COLUMN ADDRESS
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE BANK ADDRESS
BA0,
DON'T CARE
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Figure Latency
COMMAND
READ
DOUT
COMMAND
READ
DOUT
COMMAND
READ
DOUT
DON'T CARE UNDEFINED
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Figure Consecutive READ Bursts
COMMAND
READ
READ cycles
ADDRESS
BANK,
BANK,
DOUT
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
READ
cycle
ADDRESS
BANK,
BANK,
DOUT
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
READ
cycles
ADDRESS
BANK,
BANK,
DOUT
DOUT
DOUT
DOUT
DOUT
DON'T CARE
Note:
Each READ command bank. LOW.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Figure Random READ Accesses
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
BANK,
BANK,
BANK,
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
BANK,
BANK,
BANK,
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
BANK,
BANK,
BANK,
DOUT
DOUT
DOUT
DOUT
DON'T CARE
Note:
Each READ command bank. LOW.
Data from READ burst truncated with subsequent WRITE command, data from fixed-length READ burst immediately followed data from WRITE command (subject turnaround limitations). WRITE burst initiated clock edge immediately following last last desired) data element from READ burst, provided that contention avoided. given system
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
design, there possibility that device driving input data will Low-Z before SDRAM High-Z. this case, least single-cycle delay should occur between last read data WRITE command. input used avoid contention, shown Figure Figure page signal must asserted (HIGH) least clocks prior WRITE command (DQM latency clocks output buffers) suppress data-out from READ. After WRITE command registered, will High-Z remain High-Z), regardless state signal; provided active clock just prior WRITE command that truncated READ command. not, second WRITE will invalid WRITE. example, during Figure then WRITEs would valid, while WRITE would invalid. signal must de-asserted prior WRITE command (DQM latency zero clocks input buffers) ensure that written data masked. Figure shows case where clock frequency allows contention avoided without adding cycle, Figure shows case where additional needed. Figure READ-to-WRITE
COMMAND ADDRESS
READ
WRITE
BANK,
BANK,
DOUT
DON'T CARE
Note:
used illustration. READ command bank, WRITE command bank.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Figure READ-to-WRITE With Extra Clock Cycle
COMMAND ADDRESS
READ
WRITE
BANK,
BANK,
DOUT
DON'T CARE
Note:
used illustration. READ command bank, WRITE command bank.
fixed-length READ burst followed truncated with, PRECHARGE command same bank (provided that auto precharge activated), fullpage burst truncated with PRECHARGE command same bank. PRECHARGE command should issued cycles before clock edge which last desired data element valid, where equals This shown Figure page each possible latency; data element either last burst four last desired longer burst. Following PRECHARGE command, subsequent command same bank cannot issued until met. Note that part precharge time hidden during access last data element(s). case fixed-length burst being executed completion, PRECHARGE command issued optimum time described above) provides same operation that would result from same fixed-length burst with auto precharge. disadvantage PRECHARGE command that requires that command address buses available appropriate time issue command; advantage PRECHARGE command that used truncate fixed-length full-page bursts. Full-page READ bursts truncated with BURST TERMINATE command, fixed-length READ bursts truncated with BURST TERMINATE command, provided that auto precharge activated. BURST TERMINATE command should issued cycles before clock edge which last desired data element valid, where equals This shown Figure page each possible latency; data element last desired data element longer burst.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Figure READ-to-PRECHARGE
COMMAND
READ
PRECHARGE cycles
ACTIVE
ADDRESS
BANK
BANK all)
BANK
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
PRECHARGE cycle
ACTIVE
ADDRESS
BANK
BANK all)
BANK
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
PRECHARGE
ACTIVE
cycles
ADDRESS
BANK
BANK all)
BANK
DOUT
DOUT
DOUT
DOUT
DON'T CARE
Note:
LOW.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Figure Terminating READ Burst
COMMAND
READ
BURST TERMINATE cycles
ADDRESS
BANK,
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
BURST TERMINATE cycle
ADDRESS
BANK,
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
BURST TERMINATE
cycles
ADDRESS
BANK,
DOUT
DOUT
DOUT
DOUT
DON'T CARE
Note:
LOW.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands WRITEs
WRITE bursts initiated with WRITE command, shown Figure starting column bank addresses provided with WRITE command, auto precharge either enabled disabled that access. auto precharge enabled, being accessed precharged completion burst. generic WRITE commands used following illustrations, auto precharge disabled. During WRITE bursts, first valid data-in element will registered coincident with WRITE command. Subsequent data elements will registered each successive positive clock edge. Upon completion fixed-length burst, assuming other commands have been initiated, will remain High-Z additional input data will ignored (see Figure page 30). full-page burst will continue until terminated page, will wrap column continue). Data WRITE burst truncated with subsequent WRITE command, data fixed-length WRITE burst immediately followed data WRITE command. WRITE command issued clock following previous WRITE command, data provided coincident with command applies command. example shown Figure page Data either last burst last desired longer burst. This 64Mb SDRAM uses pipelined architecture therefore does require rule associated with prefetch architecture. WRITE command initiated clock cycle following previous WRITE command. Full-speed random write accesses within page performed same bank, shown Figure page each subsequent WRITE performed different bank. Figure WRITE Command
HIGH
RAS#
CAS#
A0-A7
COLUMN ADDRESS
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BA0,
BANK ADDRESS
VALID ADDRESS
DON'T CARE
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Figure WRITE Burst
COMMAND
WRITE
ADDRESS
BANK,
DON'T CARE
Figure
WRITE-to-WRITE
COMMAND
WRITE
WRITE
ADDRESS
BANK,
BANK,
TRANSITIONING DATA
DON'T CARE
Note:
LOW. Each WRITE command bank.
Data WRITE burst truncated with subsequent READ command, data fixed-length WRITE burst immediately followed READ command. Once READ command registered, data inputs will ignored, writes will executed. example shown Figure page Data either last burst last desired longer burst. Data fixed-length WRITE burst followed truncated with, PRECHARGE command same bank (provided that auto precharge activated), full-page WRITE burst truncated with PRECHARGE command same bank. PRECHARGE command should issued after clock edge which last desired input data element registered. "two-clock" write-back requires least clock plus time, regardless frequency, auto precharge mode. addition, when truncating WRITE burst, signal must used mask input data clock edge prior clock edge coincident with, PRECHARGE command. example shown Figure page Data either last burst last desired longer burst. Following PRECHARGE command, subsequent command same bank cannot issued until met. precharge will actually begin coincident with clock-edge Figure "oneclock" sometime between first second clock "two-clock" (between Figure 21).
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
case fixed-length burst being executed completion, PRECHARGE command issued optimum time described above) provides same operation that would result from same fixed-length burst with auto precharge. disadvantage PRECHARGE command that requires that command address buses available appropriate time issue command; advantage PRECHARGE command that used truncate fixed-length full-page bursts. Figure Random WRITE Cycles
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
BANK,
BANK,
BANK,
DON'T CARE
Note:
Each WRITE command bank. LOW.
Figure
WRITE-to-READ
COMMAND
WRITE
READ
ADDRESS
BANK,
BANK,
DOUT
DOUT
TRANSITIONING DATA
DON'T CARE
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Figure WRITE-to-PRECHARGE
(tCK tWR)
COMMAND
WRITE
PRECHARGE
ACTIVE
ADDRESS
BANK
BANK all)
BANK
(when tCK)
COMMAND ADDRESS
WRITE
PRECHARGE
ACTIVE
BANK
BANK all)
BANK
DON'T CARE
Note:
could remain this example WRITE burst fixed length two.
Fixed-length full-page WRITE bursts truncated with BURST TERMINATE command. When truncating WRITE burst, input data applied coincident with BURST TERMINATE command will ignored. last data written (provided that that time) will input data applied clock previous BURST TERMINATE command. This shown Figure page where data last desired data element longer burst. PRECHARGE PRECHARGE command (Figure page used deactivate open particular bank open banks. bank(s) will available subsequent access some specified time (tRP) after PRECHARGE command issued. Input determines whether banks precharged, case where only bank precharged, inputs select bank. When banks precharged, inputs treated "Don't Care." Aftera bank been precharged, idle state must activated prior READ WRITE commands being issued that bank.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Power-Down Power-down occurs registered coincident with COMMAND INHIBIT when accesses progress (see Figure page 34). power-down occurs when banks idle, this mode referred precharge power-down; power-down occurs when there active either bank, this mode referred active power-down. Entering power-down deactivates input output buffers, excluding CKE, maximum power savings while standby. device remain power-down state longer than refresh period (64ms) since refresh operations performed this mode. power-down state exited registering COMMAND INHIBIT HIGH desired clock edge (meeting tCKS). Figure Terminating WRITE Burst
COMMAND
WRITE
BURST TERMINATE
NEXT COMMAND
ADDRESS
BANK,
(ADDRESS)
(DATA)
DON'T CARE
Note:
DQMs LOW.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Figure PRECHARGE Command
HIGH
RAS#
CAS#
A0-A9
Banks
Bank Selected
BA0,
BANK ADDRESS
DON'T CARE
Figure
Power-Down
tCKS
tCKS
COMMAND
ACTIVE
banks idle Input buffers gated Enter power-down mode. Exit power-down mode.
tRCD tRAS DON'T CARE
Clock Suspend clock suspend mode occurs when column access/burst progress registered LOW. clock suspend mode, internal clock deactivated, "freezing" synchronous logic. each positive clock edge which sampled LOW, next internal positive clock edge suspended. command data present input pins time suspended internal clock edge ignored; data present pins remains driven; burst counters incremented, long clock suspended (see examples Figures page 35).
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Clock suspend mode exited registering HIGH; internal clock related operation will resume subsequent positive clock edge. Burst Read/Single Write burst read/single write mode entered programming write burst mode (M9) mode register logic this mode, WRITE commands result access single column location (burst one), regardless programmed burst length. READ commands access columns according programmed burst length sequence, just normal mode operation Figure Clock Suspend During WRITE Burst
INTERNAL CLOCK
COMMAND
WRITE
ADDRESS
BANK,
DON'T CARE
Figure
Clock Suspend During READ Burst
INTERNAL CLOCK
COMMAND
READ
ADDRESS
BANK,
DOUT
DOUT
DOUT
DOUT
DON'T CARE
Note:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
this example, greater, LOW.
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Concurrent Auto Precharge access command (READ WRITE) another bank while access command with auto precharge enabled executing allowed SDRAMs, unless SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs defined below. READ with Auto Precharge Interrupted READ (with without auto precharge): READ bank will interrupt READ bank later. precharge bank will begin when READ bank registered (Figure 27). Interrupted WRITE (with without auto precharge): WRITE bank will interrupt READ bank when registered. should used clocks prior WRITE command prevent contention. precharge bank will begin when WRITE bank registered (Figure page 37). WRITE with Auto Precharge Interrupted READ (with without auto precharge): READ bank will interrupt WRITE bank when registered, with data-out appearing later. precharge bank will begin after met, where begins when READ bank registered. last valid WRITE bank will data-in registered clock prior READ bank (Figure page 37). Interrupted WRITE (with without auto precharge): WRITE bank will interrupt WRITE bank when registered. precharge bank will begin after met, where begins when WRITE bank registered. last valid data WRITE bank will data registered clock prior WRITE bank (Figure page 38). Figure READ with Auto Precharge Interrupted READ
READ BANK READ BANK
COMMAND BANK
Page Active
READ with Burst
Interrupt Burst, Precharge BANK
Idle BANK Precharge
Internal States
BANK
Page Active
READ with Burst
ADDRESS
BANK
BANK DOUT (BANK (BANK DOUT DOUT DOUT
DON'T CARE
Note:
LOW.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Figure READ with Auto Precharge Interrupted WRITE
READ BANK Page Active WRITE BANK
COMMAND BANK
READ with Burst
Interrupt Burst, Precharge BANK
Idle BANK Write-Back
Internal States
BANK
BANK
Page Active
WRITE with Burst
ADDRESS
BANK
DOUT (BANK
DON'T CARE
Notes:
HIGH prevent DOUT from contending with
Figure
WRITE with Auto Precharge Interrupted READ
WRITE BANK READ BANK
COMMAND BANK
Page Active
WRITE with Burst
Interrupt Burst, Write-Back BANK
Precharge BANK BANK
Internal States
BANK
Page Active
READ with Burst
ADDRESS
BANK
BANK DOUT (BANK DOUT
DON'T CARE
Note:
LOW.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Figure WRITE with Auto Precharge Interrupted WRITE
WRITE BANK WRITE BANK
COMMAND BANK
Page Active
WRITE with Burst
Interrupt Burst, Write-Back BANK
Precharge BANK BANK Write-Back
Internal States
BANK
Page Active
WRITE with Burst
ADDRESS
BANK
BANK
DON'T CARE
Note:
LOW.
Table
CKEn
Truth Table
Notes: apply entire table CKEn Current State Power-down Self refresh Clock suspend Power-down Self refresh Clock suspend banks idle banks idle Reading writing COMMANDn COMMAND INHIBIT COMMAND INHIBIT COMMAND INHIBIT AUTO REFRESH WRITE Table page ACTIONn Maintain power-down Maintain self refresh Maintain clock suspend Exit power-down Exit self refresh Exit clock suspend Power-down entry Self refresh entry Clock suspend entry Notes
Notes:
CKEn logic state clock edge CKEn state previous clock edge. Current state state SDRAM immediately prior clock edge COMMANDn command registered clock edge ACTIONn result COMMANDn. states sequences shown illegal reserved. Exiting power-down clock edge will device banks idle state time clock edge (provided that tCKS met). Exiting self refresh clock edge will device banks idle state after tXSR met. COMMAND INHIBIT commands should issued clock edges occurring during tXSR period. minimum commands must provided during tXSR period. After exiting clock suspend clock edge device will resume operation recognize next command clock edge
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Table Truth Table Current State Bank Command Bank
Notes apply entire table; notes appear below next page Current State Idle Notes: RAS# CAS# Command (Action) COMMAND INHIBIT (NOP/continue previous operation) OPERATION (NOP/continue previous operation) ACTIVE (Select activate row) AUTO REFRESH LOAD MODE REGISTER PRECHARGE READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE (Deactivate bank banks) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE (Truncate READ burst, start PRECHARGE) BURST TERMINATE READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE (Truncate WRITE burst, start PRECHARGE) BURST TERMINATE Notes
active
Read (auto precharge disabled) Write (auto precharge disabled)
This table applies when CKEn HIGH CKEn HIGH (see Table page after tXSR been previous state self refresh). This table bank-specific, except where noted; that current state specific bank commands shown those allowed issued that bank when that state. Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. active: bank been activated, tRCD been met. data bursts/ accesses register accesses progress. Read: READ burst been initiated, with auto precharge disabled, terminated been terminated. Write: WRITE burst been initiated, with auto precharge disabled, terminated been terminated. following states must interrupted command issued same bank. COMMAND INHIBIT commands allowable commands other bank should issued clock edge occurring during these states. Allowable commands other bank determined current state Table according Table page Precharging: activating: Read with auto precharge enabled: Starts with registration PRECHARGE command ends when met. After met, bank will idle state. Starts with registration ACTIVE command ends when tRCD met. After tRCD met, bank will active state. Starts with registration READ command with auto precharge enabled ends when been met. After met, bank will idle state. Starts with registration WRITE command with auto precharge enabled ends when been met. After met, bank will idle state.
Write w/auto precharge enabled:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
following states must interrupted executable command; COMMAND INHIBIT commands must applied each positive clock edge during these states. Starts with registration AUTO REFRESH command ends when met. After met, SDRAM will banks idle state. Accessing mode Starts with registration LOAD MODE REGISTER command register: ends when tMRD been met. After tMRD met, SDRAM will banks idle state. Precharging all: Starts with registration PRECHARGE command ends when met. After met, banks will idle state. states sequences shown illegal reserved. bank-specific; requires that banks idle. bank-specific; banks precharged, must valid state precharging. bank-specific; BURST TERMINATE affects most recent READ WRITE burst, regardless bank. READs WRITEs listed Command (Action) column include READs WRITEs with auto precharge enabled READs WRITEs with auto precharge disabled. Does affect state bank acts that bank. Refreshing:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
Table Truth Table Current State Bank Command Bank
Notes apply entire table; notes appear below next page Current State Idle activating, active, precharging Read (auto precharge disabled) Write (auto precharge disabled) Read (with auto precharge) Write (with auto precharge) Notes: RAS# CAS# Command (Action) COMMAND INHIBIT (NOP/continue previous operation) OPERATION (NOP/continue previous operation) command otherwise allowed Bank ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE Notes
This table applies when CKEn HIGH CKEn HIGH (see Table page after tXSR been previous state self refresh). This table describes alternate bank operations, except where noted; that current state bank commands shown those allowed issued bank (assuming that bank such state that given command allowable). Exceptions covered notes below. Current state definitions: Idle: active: Read: Write: Read w/auto precharge enabled: bank been precharged, been met. bank been activated, tRCD been met. data bursts/accesses register accesses progress. READ burst been initiated, with auto precharge disabled terminated been terminated. WRITE burst been initiated, with auto precharge disabled terminated been terminated. Starts with registration READ command with auto precharge enabled ends when been met. After met, bank will idle state. Starts with registration WRITE command with auto precharge enabled ends when been met. After met, bank will idle state.
Write w/auto precharge enabled:
AUTO REFRESH, SELF REFRESH, LOAD MODE REGISTER commands only issued when banks idle.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Commands
BURST TERMINATE command cannot issued another bank; applies bank represented current state only. states sequences shown illegal reserved. READs WRITEs bank listed Command (Action) column include READs WRITEs with auto precharge enabled READs WRITEs with auto precharge disabled. Concurrent auto precharge: bank will initiate AUTO PRECHARGE command when burst been interrupted bank burst. Burst bank continues initiated. READ without auto precharge interrupted READ (with without auto precharge), READ bank will interrupt READ bank later (Figure page 23). READ without auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt READ bank when registered (Figure page Figure page 26). should used clock prior WRITE command prevent contention. WRITE without auto precharge interrupted READ (with without auto precharge), READ bank will interrupt WRITE bank when registered (Figure page 31), with data-out appearing later. last valid WRITE bank will data-in registered clock prior READ bank WRITE without auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt WRITE bank when registered (Figure page 30). last valid WRITE bank will data-in registered clock prior READ bank READ with auto precharge interrupted READ (with without auto precharge), READ bank will interrupt READ bank later. precharge bank will begin when READ bank registered (Figure page 36). READ with auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt READ bank when registered. should used clocks prior WRITE command prevent contention. precharge bank will begin when WRITE bank registered (Figure page 37). WRITE with auto precharge interrupted READ (with without auto precharge), READ bank will interrupt WRITE bank when registered, with data-out appearing later. precharge bank will begin after met, where begins when READ bank registered. last valid WRITE bank will data-in registered clock prior READ bank (Figure page 37). WRITE with auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt WRITE bank when registered. precharge bank will begin after met, where begins when WRITE bank registered. last valid WRITE bank will data registered clock prior WRITE bank (Figure page 38).
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Electrical Specifications
Electrical Specifications
Stresses greater than those listed Table cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Table Absolute Maximum Ratings
Parameter Voltage VDD, VDDQ supply relative Voltage inputs, pins relative Operating temperature (commercial) (extended; parts) Storage temperature (plastic) Power dissipation +4.6 +4.6 +150 Units
Temperature Thermal Impedance
imperative that SDRAM device's temperature specifications, shown Table page maintained order ensure junction temperature proper operating range meet data sheet specifications. important step maintaining proper junction temperature using device's thermal impedances correctly. thermal impedances listed Table page applicable revision packages. These thermal impedance values vary according density, package, particular design used each device. Incorrectly using thermal impedances produce significant errors. Read Micron technical note TN-00-08, Thermal Applications prior using thermal impedances listed Table page ensure compatibility current future designs, contact Micron Applications Engineering confirm thermal impedance values. SDRAM device's safe junction temperature range maintained when specification exceeded. applications where device's ambient temperature high, forced and/or heat sinks required order satisfy case temperature specifications.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Electrical Specifications
Table Temperature Limits
Parameter Operating case temperature: Commercial Industrial Junction temperature: Commercial Industrial Ambient temperature: Commercial Industrial Peak reflow temperature Notes: Symbol Units Notes
TPEAK
operating case temperature, measured center package side device, shown Figures page Device functionality guaranteed device exceeds maximum during operation. Both temperature specifications must satisfied. case temperature should measured gluing thermocouple center component. This should done with bead conductive epoxy, defined JEDEC EIA/JESD51 standards. Care should taken ensure thermocouple bead touching case. Operating ambient temperature surrounding package.
Table
Revision
Thermal Impedance Simulated Values
Package 86-pin TSOP 90-ball FBGA Notes: Substrate 4-layer 2-layer 4-layer (°C/W) Airflow 0m/s 66.6 70.6 (°C/W) Airflow 1m/s 57.7 57.6 47.3 (°C/W) Airflow 2m/s 54.6 69.5 52.7 (°C/W) 53.6 35.7 35.2 (°C/W) 12.7 7.95
designs expected last beyond revision listed, contact Micron Applications Engineering confirm thermal impedance values. Thermal resistance data sampled from multiple lots values should viewed typical. These estimates; actual results vary.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Electrical Specifications
Figure Example Temperature Test Point Location, 86-Pin TSOP (Top View)
22.22mm 11.11mm Test point
10.16mm 5.08mm
Figure
Example Temperature Test Point Location, 90-Ball FBGA (Top View)
8.00mm 4.00mm
Test point
13.00mm
6.50mm
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Electrical Specifications
Table Electrical Characteristics Operating Conditions
Notes apply entire table; notes appear pages VDD, VDDQ +3.3V ±0.3V Parameter/Condition Supply voltage Input high voltage: Logic inputs Input voltage: Logic inputs Input leakage current: input (All other pins under test Output leakage current: disabled; VOUT VDDQ Output levels: Output high voltage (IOUT -4mA) Output voltage (IOUT 4mA) Symbol VDD, VDDQ -0.3 Units Notes
Table
Specifications Conditions
Notes apply entire table; notes appear pages VDD, VDDQ +3.3V ±0.3V
Parameter/Condition Operating current: Active mode; Burst READ WRITE; (MIN); Standby current: Power-down mode; banks idle; Standby current: Active mode; HIGH; HIGH; banks active after tRCD met; accesses progress Operating current: Burst mode; Continuous burst; READ WRITE; banks active; tRFC tRFC (MIN) Auto refresh current: CKE, HIGH Self refresh current: 0.2V
Symbol IDD1 IDD2 IDD3 IDD4 IDD5
Units
Notes
IDD6
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Electrical Specifications
Table
Parameter Input capacitance: Input capacitance: other input-only pins Input/output capacitance:
TSOP Capacitance
Note applies entire table; notes appear pages Symbol Units
Table
Parameter
VFBGA Capacitance
Note applies entire table; notes appear pages Symbol Units
Input capacitance: Input capacitance: other input-only balls Input/output capacitance:
Table
Electrical Characteristics Recommended Operating Conditions
Notes apply entire table; notes appear pages VDD, VDDQ +3.3V ±0.3V Symbol
Characteristics Parameter Access time from (positive edge) Address hold time Address setup time high-level width low-level width Clock cycle time 38.7
120k 38.7 16.5 120k
120k 2.75 2.75
120k Units Notes
hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out High-Z time Data-out Low-Z time Data-out hold time ACTIVE-to-PRECHARGE command ACTIVE-to-ACTIVE command period AUTO REFRESH period ACTIVE READ WRITE delay
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
tCKS tCMH
tRAS
tRCD
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Electrical Specifications
Table Electrical Characteristics Recommended Operating Conditions (continued)
Notes apply entire table; notes appear pages VDD, VDDQ +3.3V ±0.3V Characteristics Parameter Refresh period (4,096 rows) PRECHARGE command period ACTIVE bank ACTIVE bank command Transition time Write recovery time Symbol
16.5
1CLK 12ns
1CLK 14ns
Units Notes
Exit self refresh ACTIVE command
tXSR
Table
Parameter
Functional Characteristics
Notes apply entire table; notes appear pages Symbol
tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL
Units
Notes
READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data High-Z during READs WRITE command input data delay Data-in ACTIVE command Data-in PRECHARGE command Last data-in burst stop command Last data-in READ/WRITE command Last data-in PRECHARGE command LOAD MODE REGISTER command ACTIVE REFRESH command Data-out High-Z from PRECHARGE command
tDAL tDAL tDPL tBDL tCDL tRDL
tROH
tROH
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Notes
Notes
voltages referenced VSS. This parameter sampled. VDD, VDDQ +3.3V; MHz, 25°C; under test biased 1.4V. range from 6pF. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range (0°C +70°C -40°C +85°C parts) ensured. initial pause 100µs required after power-up, followed AUTO REFRESH commands, before proper device operation ensured (VDD VDDQ must powered simultaneously. VSSQ must same potential). AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load:
30pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have 0.25 2.75, with timing referenced 1.5V crossover point. Other input signals allowed transition more than once two-clock period otherwise valid levels. specifications tested after device properly initialized. Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate. Timing actually specified plus tRP; clock(s) (are) specified reference only minimum cycle rate. Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will decrease reduced. This fact that maximum cycle rate slower reduced. Address transitions average transition every clocks. must toggled minimum times during this period. Based -55, overshoot: VIH(MAX) VDDQ 1.2V pulse width 3ns, pulse width cannot greater than one-third cycle rate. undershoot: VIL(MIN) -1.2V pulse width 3ns, pulse width cannot greater than one-third cycle rate.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Notes
clock frequency must remain constant during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. JEDEC PC100 specify three clocks. 5.5ns -55, VDD(MIN) 3.135V -55, speed grades. Check factory availability specially screened devices having 10ns. slower (tCK 10ns higher) manual precharge.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Timing Diagrams
Figure Initialize Load Mode Register
tCKS
tCKH
tCMS tCMH
AUTO REFRESH
tCMS tCMH COMMAND
tCMS tCMH
PRECHARGE
AUTO REFRESH
LOAD MODE REGISTER
ACTIVE
A0-A9
CODE
BANKS SINGLE BANK
CODE
BA0,
BANKS
BANK
CODE
100µs (MIN) Power-up: stable
High-Z
tRFC tRFC tMRD
Precharge banks
AUTO REFRESH
AUTO REFRESH
Program Mode Register DON'T CARE UNDEFINED
Notes:
mode register loaded prior AUTO REFRESH cycles desired. Outputs guaranteed High-Z after command issued.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure Power-Down Mode
tCKS tCKS tCKH
tCKS
tCMS tCMH COMMAND
PRECHARGE
ACTIVE
A0-A9
BANKS
SINGLE BANK
BA0,
BANK(S)
BANK
High-Z
clock cycles Precharge active banks banks idle, enter power-down mode
Input buffers gated while power-down mode banks idle Exit power-down mode DON'T CARE UNDEFINED
Note:
Violating refresh requirements during power-down result loss data.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure
Clock Suspend Mode
tCKS tCKH
tCKS tCKH
tCMS tCMH COMMAND
READ WRITE
tCMS tCMH DQM0-3 A0-A9
COLUMN
COLUMN
BA0,
BANK BANK
DOUT
DOUT
DOUT
DOUT
DON'T CARE UNDEFINED
Notes:
this example, auto precharge disabled. "Don't Care."
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure Auto Refresh Mode
tCKS tCMS COMMAND tCKH tCMH
AUTO REFRESH
PRECHARGE
AUTO REFRESH
ACTIVE
A0-A9
BANKS
SINGLE BANK
BA0,
BANK(S)
tRFC tRFC
BANK
High-Z
Precharge active banks
DON'T CARE
UNDEFINED
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure Self Refresh Mode
tCKS
tRAS
tCKS tCMS COMMAND tCKH tCMH
AUTO REFRESH
tCKS
PRECHARGE
AUTO REFRESH
DQM0-3
A0-A9
BANKS
SINGLE BANK
BA0,
BANK(S)
High-Z Precharge active banks Enter self refresh mode
tXSR Exit self refresh mode (Restart refresh time base)
DON'T CARE UNDEFINED
stable prior exiting self refresh mode
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure Single READ
tCKS tCMS COMMAND tCMH tCMS DQML, DQMH A0-A9 BA0, BANK DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK COLUMN READ tCMH PRECHARGE ACTIVE tCKH
ACTIVE
BANKS
tRCD tRAS Latency
DOUT
DON'T CARE UNDEFINED
Notes:
this example, READ burst followed "manual" PRECHARGE. "Don't Care."
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure Single READ Without Auto Precharge
tCKS tCMS COMMAND tCMH
READ PRECHARGE ACTIVE
tCKH
ACTIVE
tCMS A0-A9 BA0,
tCMH
COLUMN
BANKS DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK
BANK
tRCD tRAS Latency
DOUT
DOUT
DOUT
DOUT
DON'T CARE UNDEFINED
Notes:
this example, READ followed "manual" PRECHARGE. "Don't Care."
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure READ with Auto Precharge
tCKS tCMS tCMH COMMAND
ACTIVE READ ACTIVE
tCKH
tCMS A0-A9
tCMH
COLUMN
ENABLE AUTO PRECHARGE
BA0,
BANK BANK
BANK
tRCD tRAS Latency
DOUT
DOUT
DOUT
DOUT
DON'T CARE UNDEFINED
Notes:
this example, "Don't Care."
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure Alternating Bank Read Accesses
tCKS tCMS COMMAND tCMH
READ ACTIVE READ ACTIVE
tCKH
ACTIVE
tCMS A0-A9
tCMH
COLUMN
COLUMN
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
BA0,
BANK BANK BANK BANK
BANK
tRCD BANK tRAS BANK BANK tRRD Latency BANK
DOUT
DOUT
DOUT
DOUT
DOUT
BANK
tRCD BANK
tRCD BANK
Latency BANK
DON'T CARE UNDEFINED
Notes:
this example, "Don't Care."
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure
tCKS tCMS COMMAND tCMH
READ
READ Full-Page Burst
tCKH
ACTIVE
BURST TERM
tCMS
tCMH
A0-A9
COLUMN
BA0,
BANK
BANK
tRCD Latency
Dout
DOUT
DOUT
DOUT
DOUT
DOUT
locations within same
Full page completed Full-page burst does self-terminate. BURST TERMINATE command.
DON'T CARE UNDEFINED
Notes:
this example, "Don't Care." Page left open; tRP.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure READ Operation
tCKS tCMS COMMAND tCMH
READ
tCKH
ACTIVE
tCMS A0-A9
tCMH
COLUMN ENABLE AUTO PRECHARGE
BA0,
BANK
DISABLE AUTO PRECHARGE BANK
tRCD Latency
DOUT
DOUT
DOUT
DON'T CARE UNDEFINED
Notes:
this example, "Don't Care."
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure Single WRITE
tCKS tCMS COMMAND tCMH
WRITE PRECHARGE ACTIVE
tCKH
ACTIVE
tCMS tCMH DQML, DQMH A0-A9
COLUMN BANKS DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK
BA0,
BANK
tRCD tRAS
DON'T CARE
Notes:
this example, WRITE burst followed "manual" PRECHARGE. 10ns required between <DIN PRECHARGE command, regardless frequency, meet tWR. "Don't Care."
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure WRITE Without Auto Precharge
tCKS tCMS COMMAND tCMH
WRITE PRECHARGE ACTIVE
tCKH
ACTIVE
tCMS tCMH A0-A9
COLUMN BANKs DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK
BA0,
BANK
tRCD tRAS
DON'T CARE UNDEFINED
Notes:
this example, WRITE burst followed "manual" PRECHARGE. Faster frequencies require clocks (when tCK). "Don't Care." available running slower. Check factory availability.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure
tCKS tCMS COMMAND tCMH
WRITE ACTIVE
WRITE with Auto Precharge
tCKH
ACTIVE
tCMS tCMH A0-A9
COLUMN ENABLE AUTO PRECHARGE
BA0,
BANK BANK
BANK
tRCD tRAS
DON'T CARE UNDEFINED
Notes:
this example, Faster frequencies require clocks (when tCK). "Don't Care."
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure
tCKS tCMS COMMAND tCMH
WRITE ACTIVE WRITE ACTIVE
Alternating Write Accesses
tCKH
ACTIVE
tCMS DQML, DQMH A0-A9
tCMH
COLUMN
COLUMN
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
BA0,
BANK BANK BANK BANK
BANK
tRCD BANK tRAS BANK BANK tRRD
tRCD BANK
BANK
BANK
tRCD BANK
BANK
DON'T CARE
Notes:
this example, Faster frequencies require clocks (when tCK). "Don't Care."
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure WRITE Full-Page Burst
tCKS tCMS COMMAND tCMH
WRITE
tCKH
ACTIVE
BURST TERM
tCMS tCMH
A0-A9
COLUMN
BA0,
BANK
BANK
tRCD
locations within same
Full-page burst does self-terminate. BURST TERMINATE command stop.2,
Full page completed
DON'T CARE UNDEFINED
Notes:
"Don't Care." must satisfied prior PRECHARGE command. Page left open; tRP.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Timing Diagrams
Figure WRITE Operation
tCKS tCMS COMMAND tCMH
WRITE
tCKH
ACTIVE
tCMS tCMH A0-A9
COLUMN ENABLE AUTO PRECHARGE
BA0,
DISABLE AUTO PRECHARGE BANK
BANK
tRCD
DON'T CARE UNDEFINED
Notes:
this example, "Don't Care."
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Package Dimensions
Package Dimensions
Figure 86-Pin Plastic TSOP (400 mil)
22.22 ±0.08 0.61 0.50 +0.07 0.20 -0.03 0.10 DETAIL
2.80 11.76 ±0.20 10.16 ±0.08
0.75 1.00 +0.03 0.15 -0.02 0.25 GAGE PLANE 0.10 1.20 PLATED LEAD FINISH: (90% (100% 0.01 ±0.005 THICK SIDE PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC PACKAGE WIDTH LENGTH INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25 SIDE. +0.10 0.10 -0.05 0.50 ±0.10 0.80 DETAIL
Notes:
dimensions millimeters. Package width length include mold protrusion; allowable mold protrusion 0.025mm side. "2X" means notch present locations (both ends device).
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.
64Mb: SDRAM Package Dimensions
Figure 90-Ball VFBGA (8mm 13mm)
0.65 ±0.05
SEATING PLANE
SOLDER BALL MATERIAL: 96.5% 3%Ag, 0.5% SOLDER MASK DEFINED BALL PADS:
0.10
±0.05 SOLDER BALL DIAMETER REFERS POST REFLOW CONDITION. PREREFLOW DIAMETER BALL
6.40 0.80
SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC
BALL
BALL BALL
0.80 11.20 ±0.10 13.00 ±0.10
5.60 ±0.05 6.50 ±0.05
3.20 ±0.05 4.00 ±0.05 1.00
8.00 ±0.10
Notes:
dimensions millimeters. Package width length include mold protrusion; allowable mold protrusion 0.025mm side. Recommended size 0.33mm ±0.025mm. Topside part marking decoder found tools/fbga/decoder.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, logo, Micron logo trademarks Micron Technology, Inc. other trademarks property their respective owners. This data sheet contains minimum maximum limits specified over complete power supply temperature range forth herein. Although considered final, these specifications subject change, further product development data characterization sometimes occur.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm Rev. 10/07
Micron Technology, Inc., reserves right change products specifications without notice. ©2001 Micron Technology, Inc. rights reserved.

Other recent searches


SST29EE010 - SST29EE010   SST29EE010 Datasheet
SST29LE010 - SST29LE010   SST29LE010 Datasheet
SST29VE010 - SST29VE010   SST29VE010 Datasheet
SCF5249PB - SCF5249PB   SCF5249PB Datasheet
MJF44H11 - MJF44H11   MJF44H11 Datasheet
MJF45H11 - MJF45H11   MJF45H11 Datasheet
CD4502BMS - CD4502BMS   CD4502BMS Datasheet
CD11I - CD11I   CD11I Datasheet
AT-33225 - AT-33225   AT-33225 Datasheet
AQF240U - AQF240U   AQF240U Datasheet
2SK0662G - 2SK0662G   2SK0662G Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive